Added support for L2 (4K) page tables and made the CPU driver change cachability attributes on request. Also got the DebugUncache infrastructure working for the first time. Looks like it works for the simple case. Checking in so we can get more eyes looking at the code.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9734 6f19259b-4bc3-4df7-8a09-765794883524

2 files changed, 17 insertions, 39 deletions

diff --git a/BeagleBoardPkg/BeagleBoardPkg.dsc b/BeagleBoardPkg/BeagleBoardPkg.dsc
index 6765fa8f0c..928224b101 100644
--- a/BeagleBoardPkg/BeagleBoardPkg.dsc
+++ b/BeagleBoardPkg/BeagleBoardPkg.dsc
@@ -40,6 +40,7 @@
 
 
   ArmLib|ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
   
   BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
   BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
@@ -90,7 +91,10 @@
   UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
   EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf
   
-  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+ # UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+  UncachedMemoryAllocationLib|ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf
+
+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
 
   TimerLib|BeagleBoardPkg/Library/BeagleBoardTimerLib/BeagleBoardTimerLib.inf  
   OmapLib|BeagleBoardPkg/Library/OmapLib/OmapLib.inf
@@ -206,49 +210,29 @@
   gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
 
 # DEBUG_ASSERT_ENABLED       0x01
-
 # DEBUG_PRINT_ENABLED        0x02
-
 # DEBUG_CODE_ENABLED         0x04
-
 # CLEAR_MEMORY_ENABLED       0x08
-
 # ASSERT_BREAKPOINT_ENABLED  0x10
-
 # ASSERT_DEADLOOP_ENABLED    0x20
 
   gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
 
 #  DEBUG_INIT      0x00000001  // Initialization
-
 #  DEBUG_WARN      0x00000002  // Warnings
-
 #  DEBUG_LOAD      0x00000004  // Load events
-
 #  DEBUG_FS        0x00000008  // EFI File system
-
 #  DEBUG_POOL      0x00000010  // Alloc & Free's
-
 #  DEBUG_PAGE      0x00000020  // Alloc & Free's
-
 #  DEBUG_INFO      0x00000040  // Verbose
-
 #  DEBUG_DISPATCH  0x00000080  // PEI/DXE Dispatchers
-
 #  DEBUG_VARIABLE  0x00000100  // Variable
-
 #  DEBUG_BM        0x00000400  // Boot Manager
-
 #  DEBUG_BLKIO     0x00001000  // BlkIo Driver
-
 #  DEBUG_NET       0x00004000  // SNI Driver
-
 #  DEBUG_UNDI      0x00010000  // UNDI Driver
-
 #  DEBUG_LOADFILE  0x00020000  // UNDI Driver
-
 #  DEBUG_EVENT     0x00080000  // Event messages
-
 #  DEBUG_ERROR     0x80000000  // Error
 
   gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000004
diff --git a/BeagleBoardPkg/Sec/Cache.c b/BeagleBoardPkg/Sec/Cache.c
index facc5deae4..d7c906244c 100755
--- a/BeagleBoardPkg/Sec/Cache.c
+++ b/BeagleBoardPkg/Sec/Cache.c
@@ -58,29 +58,23 @@ InitCache (
   MemoryTable[0].Length       = MemoryLength;

   MemoryTable[0].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;

 

-  // Uncached DDR Mirror

-  MemoryTable[1].PhysicalBase = MemoryBase;

-  MemoryTable[1].VirtualBase  = MemoryBase | UncachedMemoryMask;

-  MemoryTable[1].Length       = MemoryLength;

-  MemoryTable[1].Attributes   = DDR_ATTRIBUTES_UNCACHED;

-

   // SOC Registers. L3 interconnects

-  MemoryTable[2].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;

-  MemoryTable[2].VirtualBase  = SOC_REGISTERS_L3_PHYSICAL_BASE;

-  MemoryTable[2].Length       = SOC_REGISTERS_L3_PHYSICAL_LENGTH;

-  MemoryTable[2].Attributes   = SOC_REGISTERS_L3_ATTRIBUTES;

+  MemoryTable[1].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;

+  MemoryTable[1].VirtualBase  = SOC_REGISTERS_L3_PHYSICAL_BASE;

+  MemoryTable[1].Length       = SOC_REGISTERS_L3_PHYSICAL_LENGTH;

+  MemoryTable[1].Attributes   = SOC_REGISTERS_L3_ATTRIBUTES;

   

   // SOC Registers. L4 interconnects

-  MemoryTable[3].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;

-  MemoryTable[3].VirtualBase  = SOC_REGISTERS_L4_PHYSICAL_BASE;

-  MemoryTable[3].Length       = SOC_REGISTERS_L4_PHYSICAL_LENGTH;

-  MemoryTable[3].Attributes   = SOC_REGISTERS_L4_ATTRIBUTES;

+  MemoryTable[2].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;

+  MemoryTable[2].VirtualBase  = SOC_REGISTERS_L4_PHYSICAL_BASE;

+  MemoryTable[2].Length       = SOC_REGISTERS_L4_PHYSICAL_LENGTH;

+  MemoryTable[2].Attributes   = SOC_REGISTERS_L4_ATTRIBUTES;

 

   // End of Table

-  MemoryTable[4].PhysicalBase = 0;

-  MemoryTable[4].VirtualBase  = 0;

-  MemoryTable[4].Length       = 0;

-  MemoryTable[4].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;

+  MemoryTable[3].PhysicalBase = 0;

+  MemoryTable[3].VirtualBase  = 0;

+  MemoryTable[3].Length       = 0;

+  MemoryTable[3].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;

   

   ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);