diff options
| author | Guo Mang <mang.guo@intel.com> | 2016-06-02 09:16:34 +0800 |
|---|---|---|
| committer | Hao Wu <hao.a.wu@intel.com> | 2016-06-07 09:56:11 +0800 |
| commit | b3e529bfb2213e5b834933163aaf04edff09aa22 (patch) | |
| tree | af2b48f962b9de27e00a76fac809351e973bbaf9 /BraswellPlatformPkg/Board | |
| parent | d156e32574278b4dab301c610e5cf0b43a110fc2 (diff) | |
| download | edk2-platforms-b3e529bfb2213e5b834933163aaf04edff09aa22.tar.xz | |
BraswellPlatformPkg: Add BraswellCherryHill Board support.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Diffstat (limited to 'BraswellPlatformPkg/Board')
27 files changed, 4271 insertions, 0 deletions
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Acpi.c b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Acpi.c new file mode 100644 index 0000000000..089a1d7daa --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Acpi.c @@ -0,0 +1,261 @@ +/** @file
+ ACPI Platform Driver
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <Protocol/AcpiTable.h>
+#include <Guid/PlatformInfo.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <IndustryStandard/Acpi.h>
+
+//
+// Function definitions
+//
+EFI_STATUS
+LocateSupportProtocol (
+ IN EFI_GUID *Protocol,
+ IN EFI_GUID gEfiAcpiMultiTableStorageGuid,
+ OUT VOID **Instance,
+ IN BOOLEAN Type
+ );
+
+/**
+ Locate the first instance of a protocol. If the protocol requested is an
+ FV protocol, then it will return the first FV that contains the ACPI table
+ storage file.
+
+ @param[in] Protocol The protocol to find.
+ @param[in] Instance Return pointer to the first instance of the protocol.
+ @param[in] Type TRUE if the desired protocol is a FV protocol.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NOT_FOUND The protocol could not be located.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol.
+
+**/
+EFI_STATUS
+LocateSupportProtocol (
+ IN EFI_GUID *Protocol,
+ IN EFI_GUID gEfiAcpiMultiTableStorageGuid,
+ OUT VOID **Instance,
+ IN BOOLEAN Type
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN NumberOfHandles;
+ EFI_FV_FILETYPE FileType;
+ UINT32 FvStatus;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ UINTN Size;
+ UINTN i;
+
+ //
+ // Locate protocol.
+ //
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ Protocol,
+ NULL,
+ &NumberOfHandles,
+ &HandleBuffer
+ );
+ if (EFI_ERROR (Status)) {
+
+ //
+ // Defined errors at this time are not found and out of resources.
+ //
+ return Status;
+ }
+
+ //
+ // Looking for FV with ACPI storage file
+ //
+ for (i = 0; i < NumberOfHandles; i++) {
+
+ //
+ // Get the protocol on this handle
+ // This should not fail because of LocateHandleBuffer
+ //
+ Status = gBS->HandleProtocol (
+ HandleBuffer[i],
+ Protocol,
+ Instance
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (!Type) {
+
+ //
+ // Not looking for the FV protocol, so find the first instance of the
+ // protocol. There should not be any errors because our handle buffer
+ // should always contain at least one or LocateHandleBuffer would have
+ // returned not found.
+ //
+ break;
+ }
+
+ //
+ // See if it has the ACPI storage file
+ //
+ Size = 0;
+ FvStatus = 0;
+ Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL *) (*Instance))->ReadFile (
+ *Instance,
+ &gEfiAcpiMultiTableStorageGuid,
+ NULL,
+ &Size,
+ &FileType,
+ &Attributes,
+ &FvStatus
+ );
+
+ //
+ // If we found it, then we are done
+ //
+ if (Status == EFI_SUCCESS) {
+ break;
+ }
+ }
+
+ //
+ // Our exit status is determined by the success of the previous operations
+ // If the protocol was found, Instance already points to it.
+ //
+ //
+ // Free any allocated buffers
+ //
+ FreePool (HandleBuffer);
+
+ return Status;
+}
+
+EFI_STATUS
+PublishAcpiTablesFromFv (
+ IN EFI_GUID gEfiAcpiMultiTableStorageGuid
+ )
+{
+ EFI_STATUS Status;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
+ EFI_ACPI_COMMON_HEADER *CurrentTable;
+ UINT32 FvStatus;
+ UINTN Size;
+ UINTN TableHandle;
+ INTN Instance;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+
+ Instance = 0;
+ TableHandle = 0;
+ CurrentTable = NULL;
+ FwVol = NULL;
+
+ //
+ // Find the AcpiSupport protocol
+ //
+ Status = LocateSupportProtocol (
+ &gEfiAcpiTableProtocolGuid,
+ gEfiAcpiMultiTableStorageGuid,
+ &AcpiTable,
+ FALSE
+ );
+
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Locate the firmware volume protocol
+ //
+ Status = LocateSupportProtocol (
+ &gEfiFirmwareVolume2ProtocolGuid,
+ gEfiAcpiMultiTableStorageGuid,
+ &FwVol,
+ TRUE
+ );
+
+ //
+ // Read tables from the storage file.
+ //
+
+ while (Status == EFI_SUCCESS) {
+ Status = FwVol->ReadSection (
+ FwVol,
+ &gEfiAcpiMultiTableStorageGuid,
+ EFI_SECTION_RAW,
+ Instance,
+ &CurrentTable,
+ &Size,
+ &FvStatus
+ );
+
+ if (!EFI_ERROR (Status)) {
+ //
+ // Add the table
+ //
+ TableHandle = 0;
+
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ CurrentTable,
+ CurrentTable->Length,
+ &TableHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Increment the instance
+ //
+ Instance++;
+ CurrentTable = NULL;
+ }
+ }
+
+ //
+ // Finished
+ //
+ return EFI_SUCCESS;
+}
+
+/**
+ ACPI Platform driver installation function.
+
+ @param[in] ImageHandle Handle for this drivers loaded image protocol.
+ @param[in] SystemTable EFI system table.
+
+ @retval EFI_SUCCESS The driver installed without error.
+ @retval EFI_ABORTED The driver encountered an error and could not complete installation of
+ the ACPI tables.
+
+**/
+EFI_STATUS
+InstallAcpiBraswellCherryHill (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_PLATFORM_INFO_HOB *PlatformInfoHob;
+
+ PlatformInfoHob = PcdGetPtr (PcdPlatformInfo);
+ if (PlatformInfoHob->BoardId != BOARD_ID_BSW_CH) {
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // Platform ACPI Tables
+ //
+ PublishAcpiTablesFromFv(gEfiCallerIdGuid);
+
+ return EFI_SUCCESS;
+}
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Acpi.inf b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Acpi.inf new file mode 100644 index 0000000000..51fb5d964b --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Acpi.inf @@ -0,0 +1,58 @@ +## @file
+# ACPI module for Intel(R) Atom(TM) x5 Processor Series.
+#
+# This module will get ACPI table from FV.
+#
+# Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AcpiBraswellCherryHill
+ FILE_GUID = 3F79C905-4309-4e1a-920D-95897FD3D190
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InstallAcpiBraswellCherryHill
+
+[Sources.common]
+ Acpi.c
+ Ssdt.asl
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ChvRefCodePkg/ChvRefCodePkg.dec
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseLib
+ DebugLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ BaseMemoryLib
+ MemoryAllocationLib
+
+[Pcd]
+ gEfiEdkIIPlatformTokenSpaceGuid.PcdPlatformInfo ## CONSUMES
+
+[Protocols]
+ gEfiAcpiTableProtocolGuid ## CONSUMES
+ gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
+
+[Depex]
+ gEfiAcpiTableProtocolGuid AND
+ gEfiFirmwareVolume2ProtocolGuid AND
+ gEfiMpServiceProtocolGuid AND
+ gEfiPciRootBridgeIoProtocolGuid AND
+ gEfiVariableArchProtocolGuid AND
+ gEfiVariableWriteArchProtocolGuid
+
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Audio/Audio.asl b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Audio/Audio.asl new file mode 100644 index 0000000000..4271301048 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Audio/Audio.asl @@ -0,0 +1,60 @@ +/** @file
+ ACPI DSDT table
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ //<<<<Additional Audio Modules --For Android
+ Device (AMCR)
+ {
+ Name (_HID, "AMCR22A8") // _HID: Hardware ID
+ Name (_CID, "AMCR22A8") // _CID: Compatible ID
+ Name (_DDN, "Intel(R) Audio Machine Driver - AMCR0F28") // _DDN: DOS Device Name
+ Name (_UID, One) // _UID: Unique ID
+ Name (_DEP, Package (0x02) {\_SB.GPO2, \_SB.PCI0.I2C2.RTEK})
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ // Codec GPIO
+ GpioInt (Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0x0000,
+ "\\_SB.GPO3", 0x00, ResourceConsumer, ,
+ )
+ { // Pin list
+ 77 // AUDIO_CODEC_INT to SoC GPIO_ALERT(SE77)
+ }
+ // Dock GPIO
+ GpioInt (Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0x0000,
+ "\\_SB.GPO1", 0x00, ResourceConsumer, ,
+ )
+ { // Pin list
+ 0x0006 //
+ }
+ // Jack GPIO
+ GpioInt (Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0x0000,
+ "\\_SB.GPO1", 0x00, ResourceConsumer, ,
+ )
+ { // Pin list
+ 0x0006 // JACK_DET_FB to SoC GPIO_DFX8(N06), un-staff R1H5 & staff R1H6
+ }
+ })
+ Return (RBUF)
+ }
+ Method(_STA, 0x0, NotSerialized) {
+ If (LEqual(LPES, 2)) // LPE Audio ACPI Mode = 2
+ {
+ Return (0xF)
+ }
+ Return (0x0)
+ }
+ }
+ /////Additional Audio Modules --For Android >>>>
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Audio/Realtek.asl b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Audio/Realtek.asl new file mode 100644 index 0000000000..1879db28f8 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Audio/Realtek.asl @@ -0,0 +1,71 @@ +/** @file
+ ACPI DSDT table
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ External(\CKC3, IntObj)
+ External(\LPES, IntObj)
+
+ //
+ // Realtek Audio Codec
+ //
+ Device (RTEK) //Audio Codec driver I2C
+ {
+ Name (_ADR, 0)
+ Name (_HID, "10EC5670")
+ Name (_CID, "10EC5670")
+ Name (_DDN, "RTEK Codec Controller " )
+ Name (_UID, 1)
+
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Name(SBUF,ResourceTemplate ()
+ {
+ I2CSerialBus(
+ 0x1C, // SlaveAddress: bus address
+ , // SlaveMode: default to ControllerInitiated
+ 400000, // ConnectionSpeed: in Hz
+ , // Addressing Mode: default to 7 bit
+ "\\_SB.PCI0.I2C2", // ResourceSource: I2C bus controller name
+ , // Descriptor Name: creates name for offset of resource descriptor
+ ) //VendorData
+ ///Interrupt (ResourceConsumer, Edge, ActiveHigh, ExclusiveAndWake, , , ) {92} // SE77 Line#0 route to IOAPIC IRQ 92
+ GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO3") {77} // SE77: GPIO_ALERT from AUDIO_CODEC_INT
+ })
+ Return (SBUF)
+ }
+
+ Method (_PS3, 0, NotSerialized) // _PS3: Power State 3
+ {
+ Store (Zero, CKC3)
+ }
+
+ Method (_PS0, 0, NotSerialized) // _PS0: Power State 0
+ {
+ Store (One, CKC3)
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method(_STA, 0x0, NotSerialized)
+ {
+ If (LEqual(LPES, 2)) // LPE Audio ACPI Mode = 2
+ {
+ Return (0xF)
+ }
+ Return (0x0)
+ }
+
+ } // Device (RTEK)
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Bluetooth/Broadcom.asl b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Bluetooth/Broadcom.asl new file mode 100644 index 0000000000..e81c67c943 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Bluetooth/Broadcom.asl @@ -0,0 +1,83 @@ +/** @file
+ ACPI DSDT table
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ //
+ // Bluetooth controller using serial interface
+ //
+ Device(BTH0) // Bluetooth for Android
+ {
+ Name (_HID, "BCM2E1A") // Vendor BRCM request to change to 2E1A for CHT, #4753211
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return(0)
+ } // _STA
+
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Name(UBUF, ResourceTemplate () {
+ // UARTSerial Bus Connection Descriptor
+ UARTSerialBus(115200, // InitialBaudRate: in bits ber second
+ , // BitsPerByte: default to 8 bits
+ , // StopBits: Defaults to one bit
+ 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled
+ , // IsBigEndian: default to LittleEndian
+ , // Parity: Defaults to no parity
+ , // FlowControl: Defaults to no flow control
+ 32, // ReceiveBufferSize
+ 32, // TransmitBufferSize
+ "\\_SB.PCIO.URT1", // ResourceSource: UART bus controller name
+ ,) // DescriptorName: creates name for offset of resource descriptor
+ // Interrupt (ResourceConsumer, Edge, ActiveHigh, ExclusiveAndWake, , , ) {94} // SE60 INT Line#2, IOAPIC 94
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO3", ) {62} // GPIO SE62, COMBO_BT_WAKEUP
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO3", ) {64} // GPIO SE64, COMBO_BT_RESET_N
+ GpioInt(Level, ActiveHigh, Exclusive, PullNone, 0, "\\_SB.GPO3", ) {60} // GPIO SE60, COMBO_UART_WAKE_R
+ })
+ Return(UBUF)
+ }
+ } // Device BTH0
+
+ Device (BTH1) // Bluetooth for Windows OS
+ {
+ Name (_HID, "BCM2E64")
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0)
+ } // _STA
+
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Name(BBUF, ResourceTemplate () { //For Cherrytrail CRB
+ // UARTSerial Bus Connection Descriptor
+ UARTSerialBus(115200, // InitialBaudRate: in bits ber second
+ , // BitsPerByte: default to 8 bits
+ , // StopBits: Defaults to one bit
+ 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled
+ , // IsBigEndian: default to LittleEndian
+ , // Parity: Defaults to no parity
+ , // FlowControl: Defaults to no flow control
+ 32, // ReceiveBufferSize
+ 32, // TransmitBufferSize
+ "\\_SB.PCI0.URT1", // ResourceSource: UART bus controller name
+ ,) // DescriptorName: creates name for offset of resource descriptor
+ //Interrupt (ResourceConsumer, Edge, ActiveHigh, ExclusiveAndWake, , , ) {94} // SE60 INT Line#2, IOAPIC 94
+ GpioInt(Level, ActiveLow, Exclusive, PullNone, 0, "\\_SB.GPO3", ) {60} // GPIO SE60, COMBO_UART_WAKE_R
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO3", ) {62} // GPIO SE62, COMBO_BT_WAKEUP
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO3", ) {64} // GPIO SE64, COMBO_BT_RESET_N
+ })
+ Return(BBUF)
+ }
+ } // Device BTH1
+
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Camera/Camera.asl b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Camera/Camera.asl new file mode 100644 index 0000000000..256c4f3397 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Camera/Camera.asl @@ -0,0 +1,260 @@ +/** @file
+ ACPI DSDT table
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ External(\RCAM, IntObj)
+ External(CLK0, PowerResObj)
+
+ Device (CAMD)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_HID, "INT33F7") // _HID: Hardware ID
+ Name (_CID, "INT33F7") // _CID: Compatible ID
+ Name (_SUB, "INTL0000") // _SUB: Subsystem ID
+ Name (_DDN, "OV2724") // _DDN: DOS Device Name
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PR0, Package (1) // _PR0: Power Resources for D0
+ {
+ CLK0
+ })
+ Name (PLDB, Package (0x01)
+ {
+ Buffer (0x14)
+ {
+ /* 0000 */ 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0008 */ 0x61, 0x0C, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
+ /* 0010 */ 0xFF, 0xFF, 0xFF, 0xFF
+ }
+ })
+ Method (_PLD, 0, Serialized) // _PLD: Physical Location of Device
+ {
+ Return (PLDB)
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If (LEqual (RCAM, 1)) { // CRD_B v2.1 OV5693 + OV2724
+ Return (0x0F)
+ }
+ Return (0)
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (SBUF, ResourceTemplate () // I2C Resource define
+ {
+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
+ "\\_SB.GPO1", 0x00, ResourceConsumer, ,
+ )
+ { // Pin list
+ 0x0035 // N"53" DOVDD18
+ }
+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
+ "\\_SB.GPO1", 0x00, ResourceConsumer, ,
+ )
+ { // Pin list
+ 0x002E // N"46" AVDD28
+ }
+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
+ "\\_SB.GPO1", 0x00, ResourceConsumer, ,
+ )
+ { // Pin list
+ 0x0034 // N"52" RESET
+ }
+
+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
+ "\\_SB.GPO1", 0x00, ResourceConsumer, ,
+ )
+ { // Pin list
+ 0x0030 // N"48" DVDD12
+ }
+ I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80,
+ AddressingMode7Bit, "\\_SB.PCI0.I2C3",
+ 0x00, ResourceConsumer, ,
+ )
+ })
+ Return (SBUF)
+ }
+
+ Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+ {
+ If (LEqual (Arg0, Buffer (0x10)
+ {
+ /* 0000 */ 0x6A, 0xA7, 0x7B, 0x37, 0x90, 0xF3, 0xFF, 0x4A,
+ /* 0008 */ 0xAB, 0x38, 0x9B, 0x1B, 0xF3, 0x3A, 0x30, 0x15
+ }))
+ {
+ Return ("INT33F7")
+ }
+
+ If (LEqual (Arg0, Buffer (0x10)
+ {
+ /* 0000 */ 0xAA, 0xAA, 0x62, 0x3C, 0xE0, 0xD8, 0x1A, 0x40,
+ /* 0008 */ 0x84, 0xC3, 0xFC, 0x05, 0x65, 0x6F, 0xA2, 0x8C
+ }))
+ {
+ Return ("OV2724")
+ }
+
+ If (LEqual (Arg0, Buffer (0x10)
+ {
+ /* 0000 */ 0x8F, 0xCE, 0x2A, 0x82, 0x14, 0x28, 0x74, 0x41,
+ /* 0008 */ 0xA5, 0x6B, 0x5F, 0x02, 0x9F, 0xE0, 0x79, 0xEE
+ }))
+ {
+ Return ("3SF201T2") // IHV Part Numbe
+ }
+
+ If (LEqual (Arg0, Buffer (0x10)
+ {
+ /* 0000 */ 0x2A, 0x51, 0x59, 0x29, 0x8C, 0x02, 0x46, 0x46,
+ /* 0008 */ 0xB7, 0x3D, 0x4D, 0x1B, 0x56, 0x72, 0xFA, 0xD8
+ }))
+ {
+ Return ("BSW_ITL_RVP")
+ }
+
+ If (LEqual (Arg0, Buffer (0x10) // mipiport
+ {
+ /* 0000 */ 0xD8, 0x7B, 0x3B, 0xEA, 0x9B, 0xE0, 0x39, 0x42,
+ /* 0008 */ 0xAD, 0x6E, 0xED, 0x52, 0x5F, 0x3F, 0x26, 0xAB
+ }))
+ {
+ Return (0x1021)
+ }
+
+ If (LEqual (Arg0, Buffer (0x10) // func
+ {
+ /* 0000 */ 0x92, 0xC4, 0x5A, 0xB6, 0x30, 0x9E, 0x60, 0x4D,
+ /* 0008 */ 0xB5, 0xB2, 0xF4, 0x97, 0xC7, 0x90, 0xD9, 0xCF
+ }))
+ {
+ Return (Zero)
+ }
+
+ If (LEqual (Arg0, Buffer (0x10) // rom
+ {
+ /* 0000 */ 0x0F, 0xAB, 0x70, 0xE7, 0x44, 0x26, 0xAB, 0x4B,
+ /* 0008 */ 0x86, 0x28, 0xD6, 0x2F, 0x16, 0x83, 0xFB, 0x9D
+ }))
+ {
+ Return (Zero)
+ }
+
+ If (LEqual (Arg0, Buffer (0x10) // power
+ {
+ /* 0000 */ 0xB2, 0x4A, 0xA5, 0x1E, 0x84, 0xCD, 0xCC, 0x48,
+ /* 0008 */ 0x9D, 0xD4, 0x7F, 0x59, 0x4E, 0xC3, 0xB0, 0x15
+ }))
+ {
+ Return (0x2)
+ }
+
+ If (LEqual (Arg0, Buffer (0x10) // mclk
+ {
+ /* 0000 */ 0x39, 0xA6, 0xC9, 0x75, 0x8A, 0x5C, 0x00, 0x4A,
+ /* 0008 */ 0x9F, 0x48, 0xA9, 0xC3, 0xB5, 0xDA, 0x78, 0x9F
+ }))
+ {
+ Return (Zero)
+ }
+
+ // Dsm2PlatformStr
+ If(LEqual(Arg0, ToUUID("2FA9BB94-9C5D-4AEB-8E6E-27434F81E3D3")))
+ {
+ Return ("BSW")
+ }
+
+ // Dsm2PlatformSubStr
+ If(LEqual(Arg0, ToUUID("647A6CA2-8B29-49AC-8806-D58B3D2D3EF5")))
+ {
+ Return ("FFD")
+ }
+
+ // Dsm2SiliconStr
+ If(LEqual(Arg0, ToUUID("A6E922A1-F7B3-4399-B56A-406AE416843B")))
+ {
+ Return ("BSW")
+ }
+
+ // Dsm2PlatformStr
+ If(LEqual(Arg0, ToUUID("5960313B-0AB0-4940-8840-2CAFA420C015")))
+ {
+ Return ("INTEL")
+ }
+
+ // Dsm2Info
+ If(LEqual(Arg0, ToUUID("F486D39F-D657-484B-84A6-42A565712B92")))
+ {
+ Return (Buffer (32)
+ {
+ 0x01, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x07, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+ }
+
+ If (LEqual (Arg0, Buffer (0x10) // I2C
+ {
+ /* 0000 */ 0x49, 0x75, 0x25, 0x26, 0x71, 0x92, 0xA4, 0x4C,
+ /* 0008 */ 0xBB, 0x43, 0xC4, 0x89, 0x9D, 0x5A, 0x48, 0x81
+ }))
+ {
+ If (LEqual (Arg2, One)) // total number
+ {
+ Return (One)
+ }
+
+ If (LEqual (Arg2, 0x02)) // bus4 cmos 0x10 400000
+ {
+ Return (0x02003600)
+ }
+ }
+
+ If (LEqual (Arg0, Buffer (0x10) // gpio
+ {
+ /* 0000 */ 0x40, 0x46, 0x23, 0x79, 0x10, 0x9E, 0xEA, 0x4F,
+ /* 0008 */ 0xA5, 0xC1, 0xB5, 0xAA, 0x8B, 0x19, 0x75, 0x6F
+ }))
+ {
+ If (LEqual (Arg2, One)) // total number
+ {
+ Return (0x04)
+ }
+
+ If (LEqual (Arg2, 0x02))
+ {
+ Return (0x01003507) // 1.8V
+ }
+ If (LEqual (Arg2, 0x03))
+ {
+ Return (0x01002E08) // 2.8V
+ }
+
+ If (LEqual (Arg2, 0x04))
+ {
+ Return (0x01003400) // RESET
+ }
+
+ If (LEqual (Arg2, 0x05))
+ {
+ Return (0x01003001) // 1.2V
+ }
+ }
+
+ Return (Zero)
+ }
+ }
+
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Camera/Camera2.asl b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Camera/Camera2.asl new file mode 100644 index 0000000000..4d14a7c334 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Camera/Camera2.asl @@ -0,0 +1,817 @@ +/** @file
+ ACPI DSDT table
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ External(CLK0, PowerResObj)
+ External(CLK1, PowerResObj)
+
+ //
+ // Device CAM1-----Back Camera
+ //
+ Device (CAM1)
+ {
+ Name(_ADR, 0x00)
+ Name(_HID, "INTCF1A")
+ Name(_CID, "INTCF1A")
+ Name(_SUB, "INTL0000")
+ Name(_DDN, "Sony IMX175")
+ Name(_UID, 0x01)
+
+ Name (_PR0, Package (1) // _PR0: Power Resources for D0
+ {
+ CLK0
+ })
+
+ Name (PLDB, Package(1)
+ {
+ Buffer(0x14)
+ {
+ 0x82,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,
+ 0x69,0x0c,0x00,0x00,
+ 0x03,0x00,0x00,0x00,
+ 0xFF,0xFF,0xFF,0xFF
+ }
+ })
+
+ Method(_PLD,0,Serialized)
+ {
+ Return (PLDB)
+ }
+
+ Method (_STA, 0, NotSerialized) {
+ If (LEqual (RCAM, 0)) { // Cynthiana_A IMX175 + OV2722
+ Return (0x0F)
+ }
+ Return (0)
+ }
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ Name(SBUF,ResourceTemplate ()
+ {
+ //GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {49} // MUX_CAM1_PWRDWN
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {52} // CAM_1_RST_N
+ //GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {48} // MUX_CAM_ACT_LED
+
+ I2CSerialBus(0x10, //SlaveAddress: bus address
+ , //SlaveMode: default to ControllerInitiated
+ 400000, //ConnectionSpeed: in Hz
+ , //Addressing Mode: default to 7 bit
+ "\\_SB.PCI0.I2C4", //ResourceSource: I2C bus controller name
+ , //ResourceSourceIndex: defaults to 0
+ , //ResourceUsage: Defaults to ResourceConsumer
+ , //Descriptor Name: creates name for offset of resource descriptor
+ ) //VendorData
+ I2CSerialBus(0xC, //SlaveAddress: bus address
+ , //SlaveMode: default to ControllerInitiated
+ 400000, //ConnectionSpeed: in Hz
+ , //Addressing Mode: default to 7 bit
+ "\\_SB.PCI0.I2C4", //ResourceSource: I2C bus controller name
+ , //ResourceSourceIndex: defaults to 0
+ , //ResourceUsage: Defaults to ResourceConsumer
+ , //Descriptor Name: creates name for offset of resource descriptor
+ ) //VendorData
+ I2CSerialBus(0x54, //SlaveAddress: bus address
+ , //SlaveMode: default to ControllerInitiated
+ 400000, //ConnectionSpeed: in Hz
+ , //Addressing Mode: default to 7 bit
+ "\\_SB.PCI0.I2C4", //ResourceSource: I2C bus controller name
+ , //ResourceSourceIndex: defaults to 0
+ , //ResourceUsage: Defaults to ResourceConsumer
+ , //Descriptor Name: creates name for offset of resource descriptor
+ ) //VendorData
+ })
+ Return (SBUF)
+ }
+
+ Method(_DSM, 0x4, NotSerialized)
+ {
+ If(LEqual(Arg0, ToUUID("377BA76A-F390-4AFF-AB38-9B1BF33A3015"))) // HWID
+ {
+ Return("INTCF1A");
+ }
+ If(LEqual(Arg0, ToUUID("3C62AAAA-D8E0-401A-84C3-FC05656FA28C"))) // Sensor CMOS Name
+ {
+ Return("IMX175")
+ }
+ If(LEqual(Arg0, ToUUID("822ACE8F-2814-4174-A56B-5F029FE079EE"))) // module name
+ {
+ Return("13P2BA807")
+ }
+ If(LEqual(Arg0, ToUUID("2959512A-028C-4646-B73D-4D1B5672FAD8"))) // Customer/platform info string
+ {
+ Return("INTEL_RVP")
+ }
+ If(LEqual(Arg0, ToUUID("918AB242-C37C-450A-9D0F-F47AB97C3DEA"))) // MIPI lanes count
+ {
+ Return(0x0104) // 4 lanes
+ }
+ If(LEqual(Arg0, ToUUID("EA3B7BD8-E09B-4239-AD6E-ED525F3F26AB"))) //MIPI Port
+ {
+ Return(0x01) // csi portx4
+ }
+ If(LEqual(Arg0, ToUUID("B65AC492-9E30-4D60-B5B2-F497C790D9CF"))) //DIR
+ {
+ Return(0x0) // degree 0
+ }
+ If(LEqual(Arg0, ToUUID("E770AB0F-2644-4BAB-8628-D62F1683FB9D"))) //ROM
+ {
+ Return(0x2) // eeprom
+ }
+ If(LEqual(Arg0, ToUUID("1EA54AB2-CD84-48CC-9DD4-7F594EC3B015"))) // old power option
+ {
+ Return(0x00)
+ }
+ If(LEqual(Arg0, ToUUID("8DBE2651-70C1-4C6F-AC87-A37CB46E4AF6"))) // old mclk option
+ {
+ Return(0x00)
+ }
+ If(LEqual(Arg0, ToUUID("75C9A639-5C8A-4A00-9F48-A9C3B5DA789F"))) //Reserved, default return 0x0
+ {
+ Return(0x0)
+ }
+ If(LEqual(Arg0, ToUUID("26257549-9271-4CA4-BB43-C4899D5A4881"))) //I2c
+ {
+ if(LEqual(Arg2, 1)) // Count
+ {
+ Return(0x3);
+ }
+ if(LEqual(Arg2, 2)) // Function 1 - general
+ {
+ Return(0x04001000);
+ }
+ if(LEqual(Arg2, 3)) // Function 2 - vcm
+ {
+ Return(0x04000c01);
+ }
+ if(LEqual(Arg2, 4)) // Function 3 - eeprom
+ {
+ Return(0x04005402);
+ }
+ }
+ If(LEqual(Arg0, ToUUID("79234640-9E10-4FEA-A5C1-B5AA8B19756F"))) //GPIO
+ {
+ if(LEqual(Arg2, 1)) // Count
+ {
+ Return(0x1);
+ }
+ if(LEqual(Arg2, 2)) // Function 1 - RST
+ {
+ Return(0x01001800);
+ }
+ }
+ Return(0x00)
+ }
+ } // End CAM1
+
+ //
+ // Device CAM2---Front Camera
+ //
+ Device (CAM2)
+ {
+ Name(_ADR, 0x00)
+ Name(_HID, "INT33FB")
+ Name(_CID, "INT33FB")
+ Name(_SUB, "INTL0000")
+ Name(_DDN, "OV2722")
+ Name(_UID, 0x01)
+ Name (_PR0, Package (1) // _PR0: Power Resources for D0
+ {
+ CLK1
+ })
+
+ Name (PLDB, Package(1)
+ {
+ Buffer(0x14)
+ {
+ 0x82,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,
+ 0x61,0x0c,0x00,0x00,
+ 0x03,0x00,0x00,0x00,
+ 0xFF,0xFF,0xFF,0xFF
+ }
+ })
+
+ Method(_PLD,0,Serialized)
+ {
+ Return (PLDB)
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ If (LEqual (RCAM, 0)) { // Cynthiana_A IMX175 + OV2722
+ Return (0x0F)
+ }
+ Return (0)
+ }
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ Name(SBUF,ResourceTemplate ()
+ {
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {54} //MUX_CAM2_PWRDWN
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {50} //CAM_2_RST_N
+ I2CSerialBus(0x36, //SlaveAddress: bus address
+ , //SlaveMode: default to ControllerInitiated
+ 400000, //ConnectionSpeed: in Hz
+ , //Addressing Mode: default to 7 bit
+ "\\_SB.PCI0.I2C4", //ResourceSource: I2C bus controller name
+ , //ResourceSourceIndex: defaults to 0
+ , //ResourceUsage: Defaults to ResourceConsumer
+ , //Descriptor Name: creates name for offset of resource descriptor
+ ) //VendorData
+ })
+ Return (SBUF)
+ }
+
+ Method(_DSM, 0x4, NotSerialized)
+ {
+ If(LEqual(Arg0, ToUUID("377BA76A-F390-4AFF-AB38-9B1BF33A3015"))) // HWID
+ {
+ Return("INT33FB");
+ }
+ If(LEqual(Arg0, ToUUID("3C62AAAA-D8E0-401A-84C3-FC05656FA28C"))) // Sensor CMOS Name
+ {
+ Return("OV2722")
+ }
+ If(LEqual(Arg0, ToUUID("822ACE8F-2814-4174-A56B-5F029FE079EE"))) // module name
+ {
+ Return("12P2SF220")
+ }
+ If(LEqual(Arg0, ToUUID("2959512A-028C-4646-B73D-4D1B5672FAD8"))) // Customer/platform info string
+ {
+ Return("INTEL_RVP")
+ }
+ If(LEqual(Arg0, ToUUID("918AB242-C37C-450A-9D0F-F47AB97C3DEA"))) // MIPI lanes count
+ {
+ Return(0x0101) // 1 lanes
+ }
+ If(LEqual(Arg0, ToUUID("EA3B7BD8-E09B-4239-AD6E-ED525F3F26AB"))) // MIPI Port
+ {
+ Return(0x00) // csi portx1
+ }
+ If(LEqual(Arg0, ToUUID("B65AC492-9E30-4D60-B5B2-F497C790D9CF"))) // DIR
+ {
+ Return(0x0) // degree 0
+ }
+ If(LEqual(Arg0, ToUUID("E770AB0F-2644-4BAB-8628-D62F1683FB9D"))) // ROM
+ {
+ Return(0x0) // none
+ }
+ If(LEqual(Arg0, ToUUID("1EA54AB2-CD84-48CC-9DD4-7F594EC3B015"))) // old power option
+ {
+ Return(0x00)
+ }
+ If(LEqual(Arg0, ToUUID("8DBE2651-70C1-4C6F-AC87-A37CB46E4AF6"))) // old mclk option
+ {
+ Return(0x01)
+ }
+ If(LEqual(Arg0, ToUUID("75C9A639-5C8A-4A00-9F48-A9C3B5DA789F"))) // Reserved, default return 0x0
+ {
+ Return(0x0)
+ }
+ If(LEqual(Arg0, ToUUID("26257549-9271-4CA4-BB43-C4899D5A4881"))) // I2C
+ {
+ if(LEqual(Arg2, 1)) // Count
+ {
+ Return(0x1);
+ }
+ if(LEqual(Arg2, 2)) // Function 1 - general
+ {
+ Return(0x04003600);
+ }
+ }
+ If(LEqual(Arg0, ToUUID("79234640-9E10-4FEA-A5C1-B5AA8B19756F"))) // GPIO
+ {
+ if(LEqual(Arg2, 1)) // Count
+ {
+ Return(0x2);
+ }
+ if(LEqual(Arg2, 2)) // Function 1 - RST
+ {
+ Return(0x01001600);
+ }
+ if(LEqual(Arg2, 3)) // Function 2 - PWDN
+ {
+ Return(0x01001901);
+ }
+ }
+ Return(0x00)
+ }
+ } // End CAM2
+
+ //
+ // Device STRA
+ //
+ Device (STRA)
+ {
+ Name(_ADR, 0x00)
+ Name(_HID, "INTCF1C")
+ Name(_CID, "INTCF1C")
+ Name(_SUB, "INTL0000")
+ Name(_DDN, "Flash LM3554")
+ Name(_UID, 0x01)
+ //Return the PowerResource of D0 & D3, used for OS
+ //Name(_PR0,Package(){P28X, P18X})
+
+ Method (_STA, 0, NotSerialized) {
+ If (LEqual (RCAM, 0)) { // Flash for Cynthiana_A IMX175 + OV2722
+ Return (0x0F)
+ }
+ Return (0)
+ }
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ Name(SBUF,ResourceTemplate ()
+ {
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {56} // MUX_FLASH_TRIG
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {47} // MUX_FLASH_TORCH
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {53} // MUX_FLASH_RESET_N
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {46} // MUX_GP_CAMERASB02
+ I2CSerialBus(0x53, //SlaveAddress: bus address
+ , //SlaveMode: default to ControllerInitiated
+ 400000, //ConnectionSpeed: in Hz
+ , //Addressing Mode: default to 7 bit
+ "\\_SB.PCI0.I2C4", //ResourceSource: I2C bus controller name
+ , //ResourceSourceIndex: defaults to 0
+ , //ResourceUsage: Defaults to ResourceConsumer
+ , //Descriptor Name: creates name for offset of resource descriptor
+ ) //VendorData
+ })
+ Return (SBUF)
+ }
+
+ Method(_DSM, 0x4, NotSerialized)
+ {
+ If(LEqual(Arg0, ToUUID("377BA76A-F390-4AFF-AB38-9B1BF33A3015"))) //HWID
+ {
+ Return("INTCF1C");
+ }
+ If(LEqual(Arg0, ToUUID("822ACE8F-2814-4174-A56B-5F029FE079EE"))) //module name
+ {
+ Return("LM3554")
+ }
+ If(LEqual(Arg0, ToUUID("2959512A-028C-4646-B73D-4D1B5672FAD8"))) //Customer/platform info string
+ {
+ Return("INTEL_RVP")
+ }
+ If(LEqual(Arg0, ToUUID("75C9A639-5C8A-4A00-9F48-A9C3B5DA789F"))) //Reserved, default return 0x0
+ {
+ Return(0x0)
+ }
+ If(LEqual(Arg0, ToUUID("26257549-9271-4CA4-BB43-C4899D5A4881"))) //I2c
+ {
+ if(LEqual(Arg2, 1)) // Count
+ {
+ Return(0x1);
+ }
+ if(LEqual(Arg2, 2)) // Function 1 - general
+ {
+ Return(0x04005300);
+ }
+ }
+ If(LEqual(Arg0, ToUUID("79234640-9E10-4FEA-A5C1-B5AA8B19756F"))) //GPIO
+ {
+ if(LEqual(Arg2, 1)) // Count
+ {
+ Return(0x4);
+ }
+ if(LEqual(Arg2, 2)) // Function 1 - Strobe
+ {
+ Return(0x01001302);
+ }
+ if(LEqual(Arg2, 3)) // Function 2 - Torch
+ {
+ Return(0x01001403);
+ }
+ if(LEqual(Arg2, 4)) // Function 3 - Strobe
+ {
+ Return(0x01001001);
+ }
+ if(LEqual(Arg2, 5)) // Function 4 - Torch
+ {
+ Return(0x01001104);
+ }
+ }
+ Return(0x00)
+ }
+ } //End STRA
+
+ //
+ // Device CAM3-----Rear Camera
+ //
+ Device (CAM3)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_HID, "INT33BE") // _HID: Hardware ID
+ Name (_CID, "INT33BE") // _CID: Compatible ID
+ Name (_SUB, "INTL0000") // _SUB: Subsystem ID
+ Name (_DDN, "OV5693") // _DDN: DOS Device Name
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PR0, Package (1) // _PR0: Power Resources for D0
+ {
+ CLK1
+ })
+ Name (PLDB, Package (0x01)
+ {
+ Buffer (0x14)
+ {
+ /* 0000 */ 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 0008 */ 0x69, 0x0C, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
+ /* 0010 */ 0xFF, 0xFF, 0xFF, 0xFF
+ }
+ })
+ Method (_PLD, 0, Serialized) // _PLD: Physical Location of Device
+ {
+ Return (PLDB)
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If (LEqual (RCAM, 1)) { // CRD_B v2.1 OV5693 + OV2724
+ Return (0x0F)
+ }
+ Return (0)
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (SBUF, ResourceTemplate () // I2C Resource define
+ {
+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
+ "\\_SB.GPO1", 0x00, ResourceConsumer, ,
+ )
+ { // Pin list
+ 0x0032 // GPIO N"50"
+ }
+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
+ "\\_SB.GPO1", 0x00, ResourceConsumer, ,
+ )
+ { // Pin list
+ 0x0033 // GPIO dvdd12 camerasb03 N"51"
+ }
+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
+ "\\_SB.GPO1", 0x00, ResourceConsumer, ,
+ )
+ { // Pin list
+ 0x0038 // GPIO dvdd18 camerasb04 N"56"
+ }
+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
+ "\\_SB.GPO1", 0x00, ResourceConsumer, ,
+ )
+ { // Pin list
+ 0x002D // GPIO avdd28 camerasb08 N"45"
+ }
+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
+ "\\_SB.GPO1", 0x00, ResourceConsumer, ,
+ )
+ { // Pin list
+ 0x0031 // GPIO vcm camerasb06 N"49"
+ }
+ I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80,
+ AddressingMode7Bit, "\\_SB.PCI0.I2C4",
+ 0x00, ResourceConsumer, ,
+ )
+ I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80,
+ AddressingMode7Bit, "\\_SB.PCI0.I2C4",
+ 0x00, ResourceConsumer, ,
+ )
+ I2cSerialBus (0x0054, ControllerInitiated, 0x00061A80,
+ AddressingMode7Bit, "\\_SB.PCI0.I2C4",
+ 0x00, ResourceConsumer, ,
+ )
+ })
+ Return (SBUF)
+ }
+
+ Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+ {
+ If (LEqual (Arg0, Buffer (0x10)
+ {
+ /* 0000 */ 0x6A, 0xA7, 0x7B, 0x37, 0x90, 0xF3, 0xFF, 0x4A,
+ /* 0008 */ 0xAB, 0x38, 0x9B, 0x1B, 0xF3, 0x3A, 0x30, 0x15
+ }))
+ {
+ Return ("INT33BE")
+ }
+
+ If (LEqual (Arg0, Buffer (0x10)
+ {
+ /* 0000 */ 0xAA, 0xAA, 0x62, 0x3C, 0xE0, 0xD8, 0x1A, 0x40,
+ /* 0008 */ 0x84, 0xC3, 0xFC, 0x05, 0x65, 0x6F, 0xA2, 0x8C
+ }))
+ {
+ Return ("OV5693")
+ }
+
+ If (LEqual (Arg0, Buffer (0x10)
+ {
+ /* 0000 */ 0x8F, 0xCE, 0x2A, 0x82, 0x14, 0x28, 0x74, 0x41,
+ /* 0008 */ 0xA5, 0x6B, 0x5F, 0x02, 0x9F, 0xE0, 0x79, 0xEE
+ }))
+ {
+ Return ("13P2BA540") // IHV Part Numbe
+ }
+
+ If (LEqual (Arg0, Buffer (0x10)
+ {
+ /* 0000 */ 0x2A, 0x51, 0x59, 0x29, 0x8C, 0x02, 0x46, 0x46,
+ /* 0008 */ 0xB7, 0x3D, 0x4D, 0x1B, 0x56, 0x72, 0xFA, 0xD8
+ }))
+ {
+ Return ("BSW_ITL_RVP")
+ }
+
+ If (LEqual (Arg0, Buffer (0x10)
+ {
+ /* 0000 */ 0xD8, 0x7B, 0x3B, 0xEA, 0x9B, 0xE0, 0x39, 0x42,
+ /* 0008 */ 0xAD, 0x6E, 0xED, 0x52, 0x5F, 0x3F, 0x26, 0xAB
+ }))
+ {
+ Return (0x1020)
+ }
+
+ If (LEqual (Arg0, Buffer (0x10)
+ {
+ /* 0000 */ 0x92, 0xC4, 0x5A, 0xB6, 0x30, 0x9E, 0x60, 0x4D,
+ /* 0008 */ 0xB5, 0xB2, 0xF4, 0x97, 0xC7, 0x90, 0xD9, 0xCF
+ }))
+ {
+ Return (Zero)
+ }
+
+ If (LEqual (Arg0, Buffer (0x10)
+ {
+ /* 0000 */ 0x0F, 0xAB, 0x70, 0xE7, 0x44, 0x26, 0xAB, 0x4B,
+ /* 0008 */ 0x86, 0x28, 0xD6, 0x2F, 0x16, 0x83, 0xFB, 0x9D
+ }))
+ {
+ Return (One)
+ }
+
+ If (LEqual (Arg0, Buffer (0x10)
+ {
+ /* 0000 */ 0xB2, 0x4A, 0xA5, 0x1E, 0x84, 0xCD, 0xCC, 0x48,
+ /* 0008 */ 0x9D, 0xD4, 0x7F, 0x59, 0x4E, 0xC3, 0xB0, 0x15
+ }))
+ {
+ Return (0x2)
+ }
+
+ If (LEqual (Arg0, Buffer (0x10) // mclk
+ {
+ /* 0000 */ 0x39, 0xA6, 0xC9, 0x75, 0x8A, 0x5C, 0x00, 0x4A,
+ /* 0008 */ 0x9F, 0x48, 0xA9, 0xC3, 0xB5, 0xDA, 0x78, 0x9F
+ }))
+ {
+ Return ("AD5823")
+ }
+
+ //Dsm2PlatformStr
+ If(LEqual(Arg0, ToUUID("2FA9BB94-9C5D-4AEB-8E6E-27434F81E3D3")))
+ {
+ Return ("BSW")
+ }
+
+ //Dsm2PlatformSubStr
+ If(LEqual(Arg0, ToUUID("647A6CA2-8B29-49AC-8806-D58B3D2D3EF5")))
+ {
+ Return ("FFD")
+ }
+
+ //Dsm2SiliconStr
+ If(LEqual(Arg0, ToUUID("A6E922A1-F7B3-4399-B56A-406AE416843B")))
+ {
+ Return ("BSW")
+ }
+
+ //Dsm2PlatformStr
+ If(LEqual(Arg0, ToUUID("5960313B-0AB0-4940-8840-2CAFA420C015")))
+ {
+ Return ("INTEL")
+ }
+
+ //Dsm2Info
+ If(LEqual(Arg0, ToUUID("F486D39F-D657-484B-84A6-42A565712B92")))
+ {
+ Return (Buffer (32)
+ {
+ 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x02,
+ 0x07, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ })
+ }
+
+ If (LEqual (Arg0, Buffer (0x10) // I2C
+ {
+ /* 0000 */ 0x49, 0x75, 0x25, 0x26, 0x71, 0x92, 0xA4, 0x4C,
+ /* 0008 */ 0xBB, 0x43, 0xC4, 0x89, 0x9D, 0x5A, 0x48, 0x81
+ }))
+ {
+ If (LEqual (Arg2, One))
+ {
+ Return (0x03)
+ }
+
+ If (LEqual (Arg2, 0x02))
+ {
+ Return (0x04001000)
+ }
+
+ If (LEqual (Arg2, 0x03))
+ {
+ Return (0x04000C01)
+ }
+
+ If (LEqual (Arg2, 0x04))
+ {
+ Return (0x04005402)
+ }
+ }
+
+ If (LEqual (Arg0, Buffer (0x10) // GPIO
+ {
+ /* 0000 */ 0x40, 0x46, 0x23, 0x79, 0x10, 0x9E, 0xEA, 0x4F,
+ /* 0008 */ 0xA5, 0xC1, 0xB5, 0xAA, 0x8B, 0x19, 0x75, 0x6F
+ }))
+ {
+ If (LEqual (Arg2, One))
+ {
+ Return (0x5) // total number
+ }
+
+ If (LEqual (Arg2, 0x02))
+ {
+ Return (0x01003200) // GPIO N"50" HIGH POWER EFFECITVE
+ }
+ If (LEqual (Arg2, 0x03))
+ {
+ Return (0x01003301) // GPIO N"51" HIGH POWER 12 EFFECITVE
+ }
+ If (LEqual (Arg2, 0x04))
+ {
+ Return (0x01003807) // GPIO N"56" HIGH POWER 18 EFFECITVE
+ }
+ If (LEqual (Arg2, 0x05))
+ {
+ Return (0x01002D08) // GPIO N"45" HIGH POWER 28 EFFECITVE
+ }
+ If (LEqual (Arg2, 0x06))
+ {
+ Return (0x01003109) // GPIO N"49" HIGH POWER 28 EFFECITVE
+ }
+ }
+ Return (Zero)
+ }
+ }
+
+ //
+ // Device STRB
+ //
+ Device (STRB)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_HID, "INTCF1C") // _HID: Hardware ID
+ Name (_CID, "INTCF1C") // _CID: Compatible ID
+ Name (_SUB, "INTL0000") // _SUB: Subsystem ID
+ Name (_DDN, "Flash LM3554") // _DDN: DOS Device Name
+ Name (_UID, One) // _UID: Unique ID
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If (LEqual (RCAM, 1)) { // Flash for CRD_B v2.1 OV5693 + OV2724
+ Return (0x0F)
+ }
+ Return (0)
+ }
+
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (SBUF, ResourceTemplate ()
+ {
+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
+ "\\_SB.GPO1", 0x00, ResourceConsumer, ,
+ )
+ { // Pin list
+ 0x0036
+ }
+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
+ "\\_SB.GPO1", 0x00, ResourceConsumer, ,
+ )
+ { // Pin list
+ 0x002F
+ }
+
+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
+ "\\_SB.GPO1", 0x00, ResourceConsumer, ,
+ )
+ { // Pin list
+ 0x0037 //for camera led camerasb11
+ }
+
+ I2cSerialBus (0x0053, ControllerInitiated, 0x00061A80,
+ AddressingMode7Bit, "\\_SB.PCI0.I2C4",
+ 0x00, ResourceConsumer, ,
+ )
+ })
+ Return (SBUF)
+ }
+
+ Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+ {
+ If (LEqual (Arg0, Buffer (0x10)
+ {
+ /* 0000 */ 0x6A, 0xA7, 0x7B, 0x37, 0x90, 0xF3, 0xFF, 0x4A,
+ /* 0008 */ 0xAB, 0x38, 0x9B, 0x1B, 0xF3, 0x3A, 0x30, 0x15
+ }))
+ {
+ Return ("INTCF1C")
+ }
+
+ If (LEqual (Arg0, Buffer (0x10)
+ {
+ /* 0000 */ 0x8F, 0xCE, 0x2A, 0x82, 0x14, 0x28, 0x74, 0x41,
+ /* 0008 */ 0xA5, 0x6B, 0x5F, 0x02, 0x9F, 0xE0, 0x79, 0xEE
+ }))
+ {
+ Return ("LM3554")
+ }
+
+ If (LEqual (Arg0, Buffer (0x10)
+ {
+ /* 0000 */ 0x2A, 0x51, 0x59, 0x29, 0x8C, 0x02, 0x46, 0x46,
+ /* 0008 */ 0xB7, 0x3D, 0x4D, 0x1B, 0x56, 0x72, 0xFA, 0xD8
+ }))
+ {
+ Return ("BSW_ITL_RVP")
+ }
+
+ If (LEqual (Arg0, Buffer (0x10)
+ {
+ /* 0000 */ 0x39, 0xA6, 0xC9, 0x75, 0x8A, 0x5C, 0x00, 0x4A,
+ /* 0008 */ 0x9F, 0x48, 0xA9, 0xC3, 0xB5, 0xDA, 0x78, 0x9F
+ }))
+ {
+ Return (Zero)
+ }
+
+ If (LEqual (Arg0, Buffer (0x10)
+ {
+ /* 0000 */ 0x49, 0x75, 0x25, 0x26, 0x71, 0x92, 0xA4, 0x4C,
+ /* 0008 */ 0xBB, 0x43, 0xC4, 0x89, 0x9D, 0x5A, 0x48, 0x81
+ }))
+ {
+ If (LEqual (Arg2, One))
+ {
+ Return (One)
+ }
+
+ If (LEqual (Arg2, 0x02))
+ {
+ Return (0x04005300)
+ }
+ }
+
+ If (LEqual (Arg0, Buffer (0x10)
+ {
+ /* 0000 */ 0x40, 0x46, 0x23, 0x79, 0x10, 0x9E, 0xEA, 0x4F,
+ /* 0008 */ 0xA5, 0xC1, 0xB5, 0xAA, 0x8B, 0x19, 0x75, 0x6F
+ }))
+ {
+ If (LEqual (Arg2, One))
+ {
+ Return (0x03)
+ }
+
+ If (LEqual (Arg2, 0x02))
+ {
+ Return (0x01003601)
+ }
+
+ If (LEqual (Arg2, 0x03))
+ {
+ Return (0x01002F02)
+ }
+ If (LEqual (Arg2, 0x04))
+ {
+ Return (0x01003705)
+ }
+ }
+
+ Return (Zero)
+ }
+ } // End STRB
+
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/FingerPrint/AuthenTec.asl b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/FingerPrint/AuthenTec.asl new file mode 100644 index 0000000000..7b4c6317a9 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/FingerPrint/AuthenTec.asl @@ -0,0 +1,48 @@ +/** @file
+ ACPI DSDT table
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Device(FPNT)
+ {
+ Name(_HID, "AUTH2750") // AuthenTec AES2750
+ Name(_DDN, "AuthenTec AES2750")
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ // SpiSerial Bus Connection Descriptor
+ Name(UBUF, ResourceTemplate () {
+ SPISerialBus(
+ 1, // Device selection
+ PolarityLow, // Device selection polarity
+ FourWireMode, // wiremode
+ 8, // databit len
+ ControllerInitiated, // slave mode
+ 8000000, // Connection speed
+ ClockPolarityLow, // Clock polarity
+ ClockPhaseSecond, // clock phase
+ "\\_SB.PCI0.SPI1", // ResourceSource: SPI bus controller name
+ 0, // ResourceSourceIndex
+ ResourceConsumer, // Resource usage
+ , // DescriptorName: creates name for offset of resource descriptor
+ ) // Vendor Data
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {72}
+ //GpioInt(Edge, ActiveHigh, Exclusive, PullNone, 0, "\\_SB.GPO2", ) {1}
+ })
+ Return (UBUF)
+ }
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0x0)
+ }
+ } // Device(FPNT)
+
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Gps/Broadcom.asl b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Gps/Broadcom.asl new file mode 100644 index 0000000000..cc6186305e --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Gps/Broadcom.asl @@ -0,0 +1,89 @@ +/** @file
+ ACPI DSDT table
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Device(GPS0) // GPS for Android OS
+ {
+ Name(_HID, "BCM4752")
+ Name(_HRV, 0)
+ Name (UART, One)
+ Name (ENAB, Zero)
+ Name (HSTW, One)
+
+ Method(_STA, 0x0, NotSerialized)
+ {
+ Return(0)
+ }
+
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ // UARTSerial Bus Connection Descriptor
+
+ Name(UBUF, ResourceTemplate () { // Resource for BSW RVP board
+ UARTSerialBus(
+ 115200, // InitialBaudRate: in bits ber second
+ , // BitsPerByte: default to 8 bits
+ , // StopBits: Defaults to one bit
+ 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled
+ , // IsBigEndian: default to LittleEndian
+ , // Parity: Defaults to no parity
+ FlowControlHardware, // FlowControl: Defaults to no flow control
+ 32, // ReceiveBufferSize
+ 32, // TransmitBufferSize
+ "\\_SB.PCI0.URT2", // ResourceSource: UART bus controller name
+ ,) // DescriptorName: creates name for offset of resource descriptor
+
+ GpioInt(Level, ActiveHigh, Exclusive, PullNone, 0, "\\_SB.GPO3", ) {7} // GPS_HOSTREQ SE07
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO3", ) {3} // GPS_R_WAKEUP SE03
+ //GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO3", ) {6} // COMBO_GPS_RESET_N SE06
+ })
+ Return (UBUF)
+ }
+ } // Device GPS0
+ Device(GPS1)//GPS for Windows OS.
+ {
+ Name(_HID, "BCM4752") // Vendor: test GPS device for CHT
+ Name(_HRV, 1)
+
+ Method(_STA, 0x0, NotSerialized)
+ {
+ Return (0)
+ }
+
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ // UARTSerial Bus Connection Descriptor
+
+ Name(BBUF, ResourceTemplate () { // Resource for BSW RVP board
+ UARTSerialBus(
+ 115200, // InitialBaudRate: in bits ber second
+ , // BitsPerByte: default to 8 bits
+ , // StopBits: Defaults to one bit
+ 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled
+ , // IsBigEndian: default to LittleEndian
+ , // Parity: Defaults to no parity
+ FlowControlHardware, // FlowControl: Defaults to no flow control
+ 32, // ReceiveBufferSize
+ 32, // TransmitBufferSize
+ "\\_SB.PCI0.URT2", // ResourceSource: UART bus controller name
+ ,) // DescriptorName: creates name for offset of resource descriptor
+ //GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO3", ) {6} // COMBO_GPS_RESET_N SE06
+ //Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {62} // GPS_HOSTREQ SE07 Line1 maps to direct IRQ 62
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO3", ) {3} // GPS_R_WAKEUP SE03
+ })
+ Return (BBUF)
+ }
+ } // Device GPS1
+
+
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Nfc/Nxp1.asl b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Nfc/Nxp1.asl new file mode 100644 index 0000000000..307524d504 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Nfc/Nxp1.asl @@ -0,0 +1,53 @@ +/** @file
+ ACPI DSDT table
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ External(\NFCS, IntObj)
+
+ //
+ // NFC Device
+ //
+ Device (NFC1)
+ {
+ Name (_ADR, 0x00)
+ Name (_HID, "NXP7471")
+ Name (_CID, "NXP7471")
+ Name (_DDN, "NXP NFC" )
+ Name (_UID, 0x01)
+
+ Method (_CRS, 0, NotSerialized) {
+ Name(SBUF,ResourceTemplate ()
+ {
+ I2CSerialBus(
+ 0x29, // SlaveAddress: bus address // liuzhi: for PinoleC, it's TI's fuel guage.
+ , // SlaveMode: default to ControllerInitiated
+ 400000, // ConnectionSpeed: in Hz
+ , // Addressing Mode: default to 7 bit
+ "\\_SB.PCI0.I2C7", // ResourceSource: I2C bus controller name
+ , // Descriptor Name: creates name for offset of resource descriptor
+ ) // VendorData
+
+ GpioInt(Level, ActiveHigh, Exclusive, PullNone, 0, "\\_SB.GPO1", ) {23} // N23, NFC_HOST_INT
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {27} // N27, NFC_RST_N
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {16} // N16, NFC_ENABLE_N
+ })
+ Return (SBUF)
+ }
+ Method (_STA)
+ {
+ Return (0x0)
+ }
+ } // End Device (NFC1)
+
+
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Nfc/Nxp2.asl b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Nfc/Nxp2.asl new file mode 100644 index 0000000000..ca160d2ac4 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Nfc/Nxp2.asl @@ -0,0 +1,33 @@ +/** @file
+ ACPI DSDT table
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Device (NFC2)
+ {
+ Name (_ADR, Zero)
+ Name (_HID, "NXP1002")
+ Name (_CID, "NXP1002")
+ Name (_DDN, "NXP NFC")
+ Name (_UID, One)
+ Method (_STA, 0, NotSerialized)
+ {
+ If (LEqual(NFCS, 2))
+ {
+ Return (0xF)
+ }
+ Return (0x0)
+ }
+ }
+
+
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Rfid/Impinj.asl b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Rfid/Impinj.asl new file mode 100644 index 0000000000..971057ac94 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Rfid/Impinj.asl @@ -0,0 +1,86 @@ +/** @file
+ ACPI DSDT table
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ External(\PSDE, IntObj)
+
+ //
+ // PSS Device
+ //
+ Device (IMP2) //Pss Driver I2c
+ {
+ Name (_ADR, 0)
+ Name (_HID, "IMPJ0002")
+ Name (_CID, "IMPJ0002")
+ Name (_UID, 0x1)
+
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Name (SBUF, ResourceTemplate ()
+ {
+ I2cSerialBus (
+ 0x6F, //SlaveAddress
+ ControllerInitiated, //SlaveMode
+ 100000, //ConnectionSpeed
+ AddressingMode7Bit, //Addressing Mode
+ "\\_SB.PCI0.I2C2", //ResourceSource
+ 0x00, //Descriptor Name
+ ResourceConsumer,
+ ,
+ )
+ })
+ Return (SBUF)
+ }
+
+ Method(_STA, 0x0, NotSerialized)
+ {
+ Return(0)
+ } //_STA
+ } // Device (Pss Chip 1)
+
+ //
+ // Pss Chip (Monza 8k Dura)
+ //
+ Device (IMP3)
+ {
+ Name (_ADR, 0) // _ADR: Address
+ Name (_HID, "IMPJ0003") // _HID: Hardware ID
+ Name (_CID, "IMPJ0003") // _CID: Compatible ID
+ Name (_UID, 1) // _UID: Unique ID
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Name (SBUF, ResourceTemplate ()
+ {
+ I2cSerialBus (
+ 0x6E, //SlaveAddress
+ ControllerInitiated, //SlaveMode
+ 100000, //ConnectionSpeed
+ AddressingMode7Bit, //Addressing Mode
+ "\\_SB.PCI0.I2C2", //ResourceSource
+ 0x00, //Descriptor Name
+ ResourceConsumer,
+ ,
+ )
+ })
+ Return (SBUF)
+ } //_CRS
+
+ Method(_STA, 0x0, NotSerialized)
+ {
+ Return(0)
+ } //_STA
+ } // End of Device IMP3
+
+
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/SensorHub/STMicroelectronics.asl b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/SensorHub/STMicroelectronics.asl new file mode 100644 index 0000000000..300ebcb692 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/SensorHub/STMicroelectronics.asl @@ -0,0 +1,85 @@ +/** @file
+ ACPI DSDT table
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ External(\GBA2, IntObj)
+ External(\_SB.GPO2.AVBL, IntObj)
+ External(\_SB.GPO2.SHD3, IntObj)
+
+ //
+ // Sensor hub
+ //
+ Device(SHUB)
+ {
+ Name (_ADR, 0x0)
+ Name (_HID, "SMO91D0")
+ Name (_CID, "PNP0C50")
+ Name (_DDN, "STM32F103RD")
+ Name (_UID, 0x1)
+ Name (_S0W, 3) // Put device to 0=D0, 3=D3 Hot, 4=D3 Cold during S0 idle
+ Name (_DEP, Package() {\_SB.GPO2})
+ Method (_DSM, 0x4, Serialized) {
+ Return (CDSM (Arg0, Arg1, Arg2, Arg3, 1)) // HID Descriptor Address = 1 (IHV Specific)
+ }
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0x0)
+ }
+
+ OperationRegion (GPM2, SystemMemory, Or(\GBA2, 0x4820), 4)
+ Field (GPM2, DWordAcc, Lock, Preserve) {
+ , 1,
+ SHD3, 1 // [1] GPIO Tx State of GPIO E19: SENSOR_HUB_RESET
+ }
+
+ Method (_PS3, 0, Serialized) {
+ If (\_OSI ("Android")) {
+ If (LEqual (\_SB.GPO2.AVBL, 1)) {
+ Store (0x00, \_SB.GPO2.SHD3 ) // SENSOR_HUB_RESET = 0 puts the device in reset state
+ }
+ } Else {
+ Store (0, ^SHD3) // SENSOR_HUB_RESET = 0 for WOS
+ }
+ }
+ Method (_PS0, 0, Serialized) {
+ If (\_OSI ("Android")) {
+ If (LEqual (\_SB.GPO2.AVBL, 1)) {
+ Store (0x01, \_SB.GPO2.SHD3 ) // SENSOR_HUB_RESET = 1 put the device to normal state
+ }
+ } Else {
+ Store (1, ^SHD3) // SENSOR_HUB_RESET = 1 for WOS
+ }
+ Sleep (100)
+ }
+
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Name(SBUF,ResourceTemplate () {
+ I2CSerialBus (0x40, // SlaveAddress: bus address
+ , // SlaveMode: default to ControllerInitiated
+ 400000, // ConnectionSpeed: in Hz
+ , // Addressing Mode: default to 7 bit
+ "\\_SB.PCI0.I2C1", // ResourceSource: I2C bus controller name
+ , // Descriptor Name: creates name for offset of resource descriptor
+ ) // VendorData
+ //Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {67}
+ GpioInt(Level, ActiveLow, Exclusive, PullUp, 0, "\\_SB.GPO2", ) {22} // E22, SENSOR_HUB_INT
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO2", ) {19} // E19, SENSOR_HUB_RESET
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO2", ) {16} // E16, SENSOR_HUB_WAKE
+ })
+ Return (SBUF)
+ }
+ } // Device SHUB
+
+
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/TouchPad/Atmel.asl b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/TouchPad/Atmel.asl new file mode 100644 index 0000000000..b674800fb7 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/TouchPad/Atmel.asl @@ -0,0 +1,133 @@ +/** @file
+ ACPI DSDT table
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ External(\_SB.GPO0, DeviceObj)
+ External(\_SB.GPO0.AVBL, IntObj)
+ External(\_SB.GPO0.TSR2, IntObj)
+ External(\_SB.GPO0.TSRS, IntObj)
+ External(\FBID, IntObj)
+
+ // Common _PS3 method for I2C Panel devices
+ Method (TPS3, 0, Serialized) {
+ If (LEqual (\_SB.GPO0.AVBL, 1)) {
+ If (LEqual(FBID, 2)) { // If it's BSW RVP FAB 2 board
+ Store( 0, \_SB.GPO0.TSR2 ) // Reset BSW RVP FAB 2 TOUCH
+ } Else {
+ Store( 0, \_SB.GPO0.TSRS ) // Reset BSW RVP FAB 2 TOUCH
+ }
+ }
+ }
+
+ // Common _PS0 method for I2C Panel devices
+ Method (TPS0, 0, Serialized) {
+ If (LEqual (\_SB.GPO0.AVBL, 1)) {
+ If (LEqual(FBID, 2)) { // If it's BSW RVP FAB 2 board
+ Store( 1, \_SB.GPO0.TSR2 ) // Reset BSW RVP FAB 2 TOUCH Done
+ } Else {
+ Store( 1, \_SB.GPO0.TSRS ) // Reset BSW RVP FAB 2 TOUCH Done
+ }
+ }
+ Sleep(100)
+ }
+
+ // Common _CRS method for I2C Panel devices
+ // Arg0 - Panel's Slave Address
+ Method (TCRS, 0x1, Serialized)
+ {
+ Name (RSTL, ResourceTemplate () // Resource for BSW RVP FAB 1 2 & CR board
+ {
+ I2cSerialBus (
+ 0x4A, // SlaveAddress: bus address
+ ControllerInitiated, // SlaveMode: Default to ControllerInitiated
+ 400000, // ConnectionSpeed: in Hz
+ AddressingMode7Bit, // Addressing Mode: default to 7 bit
+ "\\_SB.PCI0.I2C6", // ResourceSource: I2C bus controller name
+ , // ResourceSourceIndex: defaults to 0
+ , // ResourceUsage: Defaults to ResourceConsumer
+ PI2C // Descriptor Name: creates name for offset of resource descriptor
+ ) // VendorData
+ ///Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , ,) {59} // SW76, Line0, IRQ 59
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO0",,, TRST) {75} // SW75, TOUCH_RST_N
+ GpioInt(Level, ActiveLow, Shared, PullDefault, 0, "\\_SB.GPO0", ) {76} // SW76, TOUCH_INT_N
+ })
+ CreateByteField (RSTL, PI2C._ADR, VAL0) // Panel's Slave Address Connection Descriptor
+ Store (Arg0, VAL0) // Set Panel's Slave Address from Arg0
+ CreateByteField (RSTL, TRST._PIN, VAL1) // TOUCH_RST_N Connection Descriptor
+ If (LEqual (FBID, 2)) { // If it's BSW RVP FAB2 board
+ Store (78, VAL1) // SW78 to BSW RVP FAB2 TOUCH_RST_N
+ } Else { // If it's BSW RVP FAB1 board
+ Store (80, VAL1) // SW80 to BSW RVP FAB1 TOUCH_RST_N
+ }
+ Return (RSTL)
+ }
+
+ //------------------------
+ // Atmel Touch Panel using ATMEL7000 over SHARP display
+ // Model name currently not known
+ //------------------------
+ Device (TSC0)
+ {
+ Name (_HID, "ATML7000")
+ Name (_CID, "PNP0C50")
+ Name (HIDA, 0x00) // HID Descriptor Address
+ Name (_S0W, 3) // Put device to 0=D0, 3=D3 Hot, 4=D3 Cold during S0 idle
+ Name (_DEP, Package () {\_SB.GPO0})
+ Method (_DSM, 0x4, Serialized) {
+ Return (CDSM (Arg0, Arg1, Arg2, Arg3, HIDA))
+ }
+ Method(_STA, 0, NotSerialized) {
+ Return (0x0)
+ }
+ Method (_PS3, 0, Serialized) {
+ ^^TPS3 ()
+ }
+ Method (_PS0, 0, Serialized) {
+ ^^TPS0 ()
+ }
+ Method (_CRS, 0, NotSerialized) {
+ Return (^^TCRS (0x4A)) // Use I2C Slave Adress 0x4A
+ }
+ } // End Device (TSC0)
+
+ //------------------------
+ // Atmel Touch Panel using ATMEL1000 over CHEMEI INNOLUX display
+ // Model name is N133HSE - EA1, resolution 1920 x 1080
+ //------------------------
+ Device(TCS1)
+ {
+ Name (_ADR, Zero)
+ Name (_HID, "ATML1000")
+ Name (_CID, "PNP0C50")
+ Name (HIDA, 0x00) // HID Descriptor Address
+ Name (_UID, One)
+ Name (_S0W, 3) // Put device to 0=D0, 3=D3 Hot, 4=D3 Cold during S0 idle
+ Name (_DEP, Package() {\_SB.GPO0})
+ Method (_DSM, 0x4, Serialized) {
+ Return (CDSM (Arg0, Arg1, Arg2, Arg3, HIDA))
+ }
+ Method(_STA, 0, NotSerialized) {
+ Return (0x0)
+ }
+ Method (_PS3, 0, Serialized) {
+ ^^TPS3 ()
+ }
+ Method (_PS0, 0, Serialized) {
+ ^^TPS0 ()
+ }
+ Method (_CRS, 0, NotSerialized) {
+ Return (^^TCRS (0x4C)) // Use I2C Slave Adress 0x4C
+ }
+ } // End Device(TSC1)
+
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/TouchPad/Synaptics.asl b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/TouchPad/Synaptics.asl new file mode 100644 index 0000000000..be3309e6bd --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/TouchPad/Synaptics.asl @@ -0,0 +1,57 @@ +/** @file
+ ACPI DSDT table
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ //------------------------
+ // Synaptics Precision touchpad for CR board
+ //------------------------
+ Device (TPDC)
+ {
+ Name (_ADR, One)
+ Name (_HID, "MSFT0002")
+ Name (_CID, "PNP0C50")
+ Name (_UID, One)
+ Name (_S0W, 3) // Required to put the device to D3 Hot during S0 idle
+ Method (_DSM, 0x4, Serialized) {
+ Return (CDSM (Arg0, Arg1, Arg2, Arg3, 0x20)) // HID Descriptor Address = 0x20 (IHV Specific)
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0)
+ }
+
+ Method (_CRS, 0, Serialized)
+ {
+ Name (SBFI, ResourceTemplate ()
+ {
+ I2cSerialBus (
+ 0x20, //SlaveAddress: bus address
+ ControllerInitiated, //SlaveMode: Default to ControllerInitiated
+ 400000, //ConnectionSpeed: in Hz
+ AddressingMode7Bit, //Addressing Mode: default to 7 bit
+ "\\_SB.PCI0.I2C5", //ResourceSource: I2C bus controller name
+ , //ResourceSourceIndex: defaults to 0
+ , //ResourceUsage: Defaults to ResourceConsumer
+ , //Descriptor Name: creates name for offset of resource descriptor
+ ) //VendorData
+
+ //Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {93} // SE77, Line1, IRQ93
+ GpioInt(Level, ActiveLow, Shared, PullDefault, 0,"\\_SB.GPO3",) {77} // SE77, TCH_PAD_INT_N to GPIO_ALERT
+ })
+ Return (SBFI)
+ }
+ } // End Device (TPDC)
+
+
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/TouchPad/Synaptics2.asl b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/TouchPad/Synaptics2.asl new file mode 100644 index 0000000000..ba79c49ea1 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/TouchPad/Synaptics2.asl @@ -0,0 +1,57 @@ +/** @file
+ ACPI DSDT table
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ //------------------------
+ // Synaptics Precision touchpad
+ //------------------------
+ Device (TPD1)
+ {
+ Name (_ADR, One)
+ Name (_HID, "MSFT0002")
+ Name (_CID, "PNP0C50")
+ Name (_UID, One)
+ Name (_S0W, 3) // Put device to 0=D0, 3=D3 Hot, 4=D3 Cold during S0 idle
+ Method (_DSM, 0x4, Serialized) {
+ Return (CDSM (Arg0, Arg1, Arg2, Arg3, 0x20)) // HID Descriptor Address = 0x20 (IHV Specific)
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0)
+ }
+
+ Method (_CRS, 0, Serialized)
+ {
+ Name (SBFI, ResourceTemplate ()
+ {
+ I2cSerialBus (
+ 0x20, // SlaveAddress: bus address
+ ControllerInitiated, // SlaveMode: Default to ControllerInitiated
+ 400000, // ConnectionSpeed: in Hz
+ AddressingMode7Bit, // Addressing Mode: default to 7 bit
+ "\\_SB.PCI0.I2C6", // ResourceSource: I2C bus controller name
+ , // ResourceSourceIndex: defaults to 0
+ , // ResourceUsage: Defaults to ResourceConsumer
+ , // Descriptor Name: creates name for offset of resource descriptor
+ ) // VendorData
+
+ //Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {94} // SE77, Line2, IRQ94
+ GpioInt(Level, ActiveLow, Exclusive, PullNone, 0,"\\_SB.GPO3",) {77} // SE77, TCH_PAD_INT_N to GPIO_ALERT
+ })
+ Return (SBFI)
+ }
+ } // End Device (TPD1)
+
+
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Wifi/Broadcom.asl b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Wifi/Broadcom.asl new file mode 100644 index 0000000000..99cda32782 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Wifi/Broadcom.asl @@ -0,0 +1,169 @@ +/** @file
+ ACPI DSDT table
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ External(\WIFD, IntObj)
+ External(\_SB.GPO1.AVBL, IntObj)
+ External(\_SB.GPO1.CWLE, IntObj)
+ External(\_SB.PCI0.SDHB.PSTS, IntObj)
+
+ Device (BRCM) // WIFI For Android
+ {
+ Name (_ADR, 0x01) // SlotNumber + Function
+ Name (_DEP, Package() {\_SB.GPO1})
+ // Added here for Android Support ++
+ Name (_HID, "BCM43241") // _HID: Hardware ID
+ Name (_CID, "BCM43241") // _CID: Compatible ID
+ // Added here for Android Support --
+ Method(_STA, 0x0, NotSerialized)
+ {
+ If (LEqual(WIFD, 1))
+ {
+ Return (0x0F)
+ }
+ Return(0x0)
+ }
+
+ Method (_RMV, 0, NotSerialized)
+ {
+ Return (0x0)
+ }
+
+ Name (_PRW, Package() {0, 0})
+ Name (_S4W, 2)
+ Name (_S0W, 2)
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, ExclusiveAndWake, , , ) {53} // N21 Line#2 to IOAPIC IRQ 53
+ GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO1") {21} // COMBO_WLAN_IRQ to GPIO N21
+ GpioIo(Exclusive, PullNone, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {5} // COMBO_WLAN _R_EN to GPIO N5
+ })
+ Return (RBUF)
+ }
+
+ Method (_PS3, 0, NotSerialized)
+ {
+ If(LEqual (\_SB.GPO1.AVBL, 1)) {
+ Store( 0x00, \_SB.GPO1.CWLE ) // COMBO_WLAN_EN = 0 put WLAN to disabled state
+ }
+ Store( 0x00, \_SB.PCI0.SDHB.PSTS) // Indicates that the device is powered off
+ }
+ Method (_PS0, 0, NotSerialized)
+ {
+ If(LEqual(\_SB.PCI0.SDHB.PSTS, 0x0))
+ {
+ If(LEqual (\_SB.GPO1.AVBL, 1)) {
+ Store( 0x01, \_SB.GPO1.CWLE ) // COMBO_WLAN_EN = 1 put WLAN to enabled state
+ }
+ Store( 0x01, \_SB.PCI0.SDHB.PSTS) // Indicates that the device is powered on
+ }
+ }
+
+ } // Device (BRCM)
+ Device (BRC1) // WIFI for Windows
+ {
+ Name (_ADR, 0x02) // SlotNumber + Function
+ Name (_DEP, Package() {\_SB.GPO1})
+ Method(_STA, 0x0, NotSerialized)
+ {
+ If (LEqual(WIFD, 0))
+ {
+ Return (0x0F)
+ }
+ Return(0)
+ }
+ Method (_RMV, 0, NotSerialized)
+ {
+ Return (0x0)
+ }
+ Name (_PRW, Package() {0, 0})
+ Name (_S4W, 2)
+ Name (_S0W, 2)
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, ExclusiveAndWake, , , ) {53} // N21 Line#2 to IOAPIC IRQ 53
+ //GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO1") {21} // COMBO_WLAN_IRQ to GPIO N21
+ //GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {5} // COMBO_WLAN _R_EN to GPIO N5
+ })
+ Return (RBUF)
+ }
+
+ Method (_PS3, 0, NotSerialized)
+ {
+ If(LEqual (\_SB.GPO1.AVBL, 1)) {
+ Store( 0x00, \_SB.GPO1.CWLE ) // COMBO_WLAN_EN = 0 put WLAN to disabled state
+ }
+ Store( 0x00, \_SB.PCI0.SDHB.PSTS) // Indicates that the device is powered off
+ }
+ Method (_PS0, 0, NotSerialized)
+ {
+ If(LEqual(\_SB.PCI0.SDHB.PSTS, 0x0))
+ {
+ If(LEqual (\_SB.GPO1.AVBL, 1)) {
+ Store( 0x01, \_SB.GPO1.CWLE ) // COMBO_WLAN_EN = 1 put WLAN to enabled state
+ }
+ Store( 0x01, \_SB.PCI0.SDHB.PSTS) // Indicates that the device is powered on
+ }
+ }
+ } // Device (BRC1)
+
+
+ //
+ // Secondary Broadcom WIFI function
+ //
+ Device(BRC2)
+ {
+ Name(_ADR, 0x2) // function 2
+ Name(_STA, 0xf)
+ //
+ // The device is not removable. This must be a method.
+ //
+ Method(_RMV, 0x0, NotSerialized)
+ {
+ Return(0x0)
+ }
+
+ //
+ // Describe a vendor-defined connection between this device and the
+ // primary wifi device
+ //
+
+ Method(_CRS) {
+ Name(NAM, Buffer() {"\\_SB.PCI0.SDHB.BRC1"})
+ Name(SPB, Buffer() {
+ 0x8E, // SPB Descriptor
+ 0x1D, 0x00, // Length including NAM above
+ 0x01, // +0x00 SPB Descriptor Revision
+ 0x00, // +0x01 Resource Source Index
+ 0xc0, // +0x02 Bus type - vendor defined
+ 0x02, // +0x03 Consumer + controller initiated
+ 0x00, 0x00, // +0x04 Type specific flags
+ 0x01, // +0x06 Type specific revision
+ 0x00, 0x00 // +0x07 type specific data length
+ // +0x09 - 0xf bytes for NULL-terminated NAM
+ // Length = 0x18
+ })
+
+ Name(END, Buffer() {0x79, 0x00})
+ Concatenate(SPB, NAM, Local0)
+ Concatenate(Local0, END, Local1)
+ Return(Local1)
+ }
+ }
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Ssdt.asl b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Ssdt.asl new file mode 100644 index 0000000000..a30fcf5bb4 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Ssdt.asl @@ -0,0 +1,122 @@ +/** @file
+ ACPI DSDT table
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+DefinitionBlock (
+ "Ssdt.aml",
+ "SSDT",
+ 0x02, // revision.
+ // A Revision field value greater than or equal to 2 signifies that integers
+ // declared within the Definition Block are to be evaluated as 64-bit values
+ "INTEL", // OEM ID (6 byte string)
+ "BSW_RH", // OEM table ID (8 byte string)
+ 0x0 // OEM version of DSDT table (4 byte Integer)
+ )
+{
+ External(\GP23, IntObj)
+ External(\_TZ.TZ01, ThermalZoneObj)
+
+ Scope(\_GPE)
+ {
+ Method(_L17)
+ {
+ // Clear the GPE23 Status Bit.
+ Store(1,GP23)
+ // Handle the external SCI Thermal Event.
+ Notify(\_TZ.TZ01,0x80)
+ }
+ }
+
+ External(\_SB.GPO1, DeviceObj)
+ External(\_SB.PCI0, DeviceObj)
+ External(\_SB.PCI0.URT1, DeviceObj)
+ External(\_SB.PCI0.URT2, DeviceObj)
+ External(\_SB.PCI0.SPI1, DeviceObj)
+ External(\_SB.PCI0.I2C1, DeviceObj)
+ External(\_SB.PCI0.I2C2, DeviceObj)
+ External(\_SB.PCI0.I2C3, DeviceObj)
+ External(\_SB.PCI0.I2C4, DeviceObj)
+ External(\_SB.PCI0.I2C5, DeviceObj)
+ External(\_SB.PCI0.I2C6, DeviceObj)
+ External(\_SB.PCI0.I2C7, DeviceObj)
+ External(\_SB.PCI0.SDHB, DeviceObj)
+ External(CDSM, MethodObj)
+
+ Scope(\_SB.PCI0.URT1)
+ {
+ include("Device/Bluetooth/Broadcom.asl")
+ }
+
+ Scope(\_SB.PCI0.URT2)
+ {
+ include("Device/Gps/Broadcom.asl")
+ }
+
+ Scope(\_SB.PCI0.SPI1)
+ {
+ include("Device/FingerPrint/AuthenTec.asl")
+ }
+
+ Scope(\_SB.PCI0)
+ {
+ include("Device/Nfc/Nxp2.asl")
+ }
+
+ Scope(\_SB.PCI0.I2C1)
+ {
+ include("Device/SensorHub/STMicroelectronics.asl")
+ }
+
+ Scope(\_SB.PCI0.I2C2)
+ {
+ include("Device/Audio/Realtek.asl")
+ include("Device/Rfid/Impinj.asl")
+ }
+
+ Scope(\_SB.PCI0.I2C3)
+ {
+ include("Device/Camera/Camera.asl")
+ }
+
+ Scope(\_SB.PCI0.I2C4)
+ {
+ include("Device/Camera/Camera2.asl")
+ }
+
+ Scope(\_SB.PCI0.I2C5)
+ {
+ include("Device/TouchPad/Synaptics.asl")
+ }
+
+ Scope(\_SB.PCI0.I2C6)
+ {
+ include("Device/TouchPad/Atmel.asl")
+ include("Device/TouchPad/Synaptics2.asl")
+ }
+
+ Scope(\_SB.PCI0.I2C7)
+ {
+ include("Device/Nfc/Nxp1.asl")
+ }
+
+ Scope(\_SB.PCI0)
+ {
+ include("Device/Audio/Audio.asl")
+ }
+
+ Scope(\_SB.PCI0.SDHB)
+ {
+ include("Device/Wifi/Broadcom.asl")
+ }
+}
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardGpios.h b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardGpios.h new file mode 100644 index 0000000000..71d26e1697 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardGpios.h @@ -0,0 +1,203 @@ +/** @file
+ GPIO setting for CherryView.
+
+ This file includes package header files, library classes.
+
+ Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _BOARDGPIOS_H_
+#define _BOARDGPIOS_H_
+
+#include <PiPei.h>
+#include "PchAccess.h"
+#include "PlatformBaseAddresses.h"
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/Timerlib.h>
+#include <Library/PchPlatformLib.h>
+#include <Library/GpioLib.h>
+#include <Guid/PlatformInfo.h>
+
+//#define EFI_DEBUG 1
+#define GPIO_DFX1_PAD0 0x4418
+#define GPIO_DFX3_PAD0 0x4408
+#define GPIO_MF_ISH_I2C1_SCL_PAD0 0x4810
+#define GPIO_MF_ISH_I2C1_SDA_PAD0 0x4858
+#define GPIO_PCIE_CLKREQ0B_PAD0 0x5C00
+#define GPIO_SEC_GPIO_SUS8_PAD0 0x4840
+#define GPIO_SEC_GPIO_SUS8_PAD1 0x4844
+#define GPIO_SEC_GPIO_SUS9_PAD0 0x4860
+#define GPIO_SEC_GPIO_SUS9_PAD1 0x4864
+#define GPIO_SEC_GPIO_SUS10_PAD0 0x4808
+#define GPIO_SEC_GPIO_SUS10_PAD1 0x480C
+#define GPIO_I2C_NFC_SCL_PAD0 0x5038
+#define GPIO_I2C_NFC_SCL_PAD1 0x503C
+#define GPIO_I2C_NFC_SDA_PAD0 0x5020
+#define GPIO_I2C_NFC_SDA_PAD1 0x5024
+#define GPIO_MF_ISH_GPIO_7_PAD0 0x4808
+
+#define USB3_CAMERA 0
+#define MIPI_CAMERA 1
+#define DISABLE 0
+#define NO_PULL_UP 0
+#define SECURE_NFC_ENABLE 1
+
+#define GPIO_SOC_RUNTIME_SCI_N 0x4850
+
+/// *****************************************************************************************************************************************
+/// *****************************************************************************************************************************************
+/// *****************************************************************************************************************************************
+/// *************************************************** CHERRYVIEW GPIO CONFIGURATION *************************************************
+/// *****************************************************************************************************************************************
+/// *****************************************************************************************************************************************
+/// *****************************************************************************************************************************************
+
+#define ENABLE 1
+#define DISABLE 0
+
+// Braswell Cherry Hill platform
+
+/// Community Configuration
+/// Family Configuration
+/*
+* GPIO Families configuration in CherryView
+*
+*/
+
+GPIO_SAI_INIT mBSW_CH_GPIO_SAI_Init_East[] =
+{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ", 0x0 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ", 0x4 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ", 0x8 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ", 0xC , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ", 0x10 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ", 0x14 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ", 0x18 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_4x2_12_0_regs ", 0x1C , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_4x2_12_1_regs ", 0x20 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ", 0x100, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ", 0x104, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ", 0x108, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ", 0x10C, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ", 0x110, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ", 0x114, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ", 0x118, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_4x2_12_0_regs ", 0x11c, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_4x2_12_1_regs ", 0x120, 0x18310, ENABLE),
+};
+
+GPIO_SAI_INIT mBSW_CH_GPIO_SAI_Init_North[] =
+{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ", 0x0 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ", 0x4 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ", 0x8 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ", 0xC , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ", 0x10 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ", 0x14 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ", 0x18 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_2x4_rcomp_10_0_regs ", 0x1C , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x4_13_0_regs ", 0x20 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_3x4_12_0_regs ", 0x24 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_2x4_12_0_regs ", 0x28 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_3x4_13_0_regs ", 0x2C , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ", 0x100, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ", 0x104, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ", 0x108, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ", 0x10C, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ", 0x110, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ", 0x114, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ", 0x118, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_2x4_rcomp_10_0_regs ", 0x11C, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x4_13_0_regs ", 0x120, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_3x4_12_0_regs ", 0x124, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_2x4_12_0_regs ", 0x128, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_3x4_13_0_regs ", 0x12C, 0x18310, ENABLE),
+};
+
+GPIO_SAI_INIT mBSW_CH_GPIO_SAI_Init_SouthEast[] =
+{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ", 0x0 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ", 0x4 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ", 0x8 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ", 0xC , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ", 0x10 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ", 0x14 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ", 0x18 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_2_regs ", 0x1C , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_3x3_rcomp_13_0_regs ", 0x20 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_hshvfamily_2x3_rcomp_7_0_regs ", 0x24 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_hshvfamily_3x3_rcomp_9_0_regs ", 0x28 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_3x3_10_0_regs ", 0x2C , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_3x3_11_0_regs ", 0x30 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ", 0x100, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ", 0x104, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ", 0x108, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ", 0x10C, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ", 0x110, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ", 0x114, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ", 0x118, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_2_regs ", 0x11C, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_3x3_rcomp_13_0_regs ", 0x120, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_hshvfamily_2x3_rcomp_7_0_regs ", 0x124, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_hshvfamily_3x3_rcomp_9_0_regs ", 0x128, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_3x3_10_0_regs ", 0x12C, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_3x3_11_0_regs ", 0x130, 0x18310, ENABLE),
+};
+
+GPIO_SAI_INIT mBSW_CH_GPIO_SAI_Init_SouthWest[] =
+{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ",0x0 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ",0x4 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ",0x8 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ",0xC , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ",0x10 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ",0x14 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ",0x18 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_2x3_8_1_regs ",0x1C , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_6_regs ",0x20 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_5_regs ",0x24 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_4_regs ",0x28 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_3_regs ",0x2C , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_1_regs ",0x30 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_0_regs ",0x34 , 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ",0x100, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ",0x104, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ",0x108, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ",0x10C, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ",0x110, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ",0x114, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ",0x118, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_2x3_8_1_regs ",0x11C, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_6_regs ",0x120, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_5_regs ",0x124, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_4_regs ",0x128, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_3_regs ",0x12C, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_1_regs ",0x130, 0x18310, ENABLE),
+ CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_0_regs ",0x134, 0x18310, ENABLE),
+};
+
+
+CHV_GPIO_PAD_INIT mBSW_CH_GpioInitData_SetupBasedConfig[] =
+// Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks
+{
+ CHV_GPIO_PAD_CONF (L"N53: GP_CAMERASB01 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5040 , NORTH ) , // FLASH_RESET_N
+//CHV_GPIO_PAD_CONF (L"N53: GP_CAMERASB01 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5040 , NORTH ) , // IMAGING_DFU : USB3 CAM
+//CHV_GPIO_PAD_CONF (L"N53: GP_CAMERASB01 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5040 , NORTH ) , // IMAGING_DFU : MIPI CAM
+};
+
+CHV_GPIO_PAD_INIT mBSW_CH_GpioInitData_N[] =
+// PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks
+{
+ CHV_GPIO_PAD_CONF (L"N25: GPIO_SUS6 ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line9 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , No_Inversion , NA , 19 , SCI , 0x4850 , NORTH ) , // XDP_HLT_BOOT
+ CHV_GPIO_PAD_CONF (L"N18: GPIO_SUS7 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , SMI , 0x4818 , NORTH ) , //
+ CHV_GPIO_PAD_CONF (L"N23: SEC_GPIO_SUS8 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4840 , NORTH ) , //
+ CHV_GPIO_PAD_CONF (L"N27: SEC_GPIO_SUS9 ", GPIO , M1 , GPI , LOW , NA , Trig_Level , Line15 , NA , NA , NA , NonMaskable , En_RX_Data , Inv_RX_Data , NA , 21 , SCI , 0x4860 , NORTH ) , // GPIO_THERM_ALERT_N
+};
+
+#endif
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInit.c b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInit.c new file mode 100644 index 0000000000..9d69107119 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInit.c @@ -0,0 +1,1277 @@ +/** @file
+ Board Init driver.
+
+ Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Guid/PlatformInfo.h>
+#include <Ppi/BoardDetection.h>
+#include <Ppi/ChvPlatformPolicyPpi.h>
+#include <Protocol/PlatformGopPolicy.h>
+#include <Library/GpioLib.h>
+#include <Library/PchPlatformLib.h>
+#include <PlatformGpioTable.h>
+//
+// TBD: Need update to CH version
+//
+extern UINT8 mBSW_CR_SpdDataMemorySolderDown[];
+
+//
+// TBD: Need update to CH version
+//
+CHV_GPIO_PAD_INIT mBswCherryHillGpioInitData[] =
+{
+ //
+ // North Community
+ // Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks
+ CHV_GPIO_PAD_CONF (L"N00: GPIO_DFX0 ", Native , M5 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 0 , NA , 0x4400 , NORTH ) , // C0_BPM0_TX
+ CHV_GPIO_PAD_CONF (L"N01: GPIO_DFX3 ", Native , M5 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 1 , NA , 0x4408 , NORTH ) , // C0_BPM3_TX
+ CHV_GPIO_PAD_CONF (L"N02: GPIO_DFX7 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 2 , NA , 0x4410 , NORTH ) , //
+ CHV_GPIO_PAD_CONF (L"N03: GPIO_DFX1 ", Native , M5 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , NORTH ) , // C0_BPM1_TX
+ CHV_GPIO_PAD_CONF (L"N04: GPIO_DFX5 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 4 , NA , 0x4420 , NORTH ) , //
+ CHV_GPIO_PAD_CONF (L"N05: GPIO_DFX4 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 5 , NA , 0x4428 , NORTH ) , //
+ CHV_GPIO_PAD_CONF (L"N06: GPIO_DFX8 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 6 , NA , 0x4430 , NORTH ) , // JACK DETECT?
+ CHV_GPIO_PAD_CONF (L"N07: GPIO_DFX2 ", Native , M5 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 7 , NA , 0x4438 , NORTH ) , // C0_BPM2_TX
+ CHV_GPIO_PAD_CONF (L"N08: GPIO_DFX6 ", Native , M8 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 8 , NA , 0x4440 , NORTH ) , //
+ CHV_GPIO_PAD_CONF (L"N15: GPIO_SUS0 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 9 , NA , 0x4800 , NORTH ) , // GPIO0_SUS0
+ CHV_GPIO_PAD_CONF (L"N16: SEC_GPIO_SUS10 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 10 , NA , 0x4808 , NORTH ) , // GPIO_SUS10
+ CHV_GPIO_PAD_CONF (L"N17: GPIO_SUS3 ", GPIO , M1 , GPI , NA , NA , Trig_Level , Line1 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , No_Inversion , NA , 11 , NA , 0x4810 , NORTH ) , // NGFF_SDIO_WAKE_N
+ CHV_GPIO_PAD_CONF (L"N18: GPIO_SUS7 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , SMI , 0x4818 , NORTH ) , // GPIO_SUS7
+ CHV_GPIO_PAD_CONF (L"N19: GPIO_SUS1 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 13 , NA , 0x4820 , NORTH ) , // GPIO_SUS1
+ CHV_GPIO_PAD_CONF (L"N20: GPIO_SUS5 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 14 , NA , 0x4828 , NORTH ) , // NGFF_KILL_WIFI_N
+ CHV_GPIO_PAD_CONF (L"N21: SEC_GPIO_SUS11 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 15 , NA , 0x4830 , NORTH ) , // GPIO_SUS11
+ CHV_GPIO_PAD_CONF (L"N22: GPIO_SUS4 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 16 , NA , 0x4838 , NORTH ) , // NGFF_KILL_BT_N
+ CHV_GPIO_PAD_CONF (L"N23: SEC_GPIO_SUS8 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4840 , NORTH ) , // GPIO_SUS8
+ CHV_GPIO_PAD_CONF (L"N24: GPIO_SUS2 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 18 , NA , 0x4848 , NORTH ) , // NGFF_PWR_EN
+ CHV_GPIO_PAD_CONF (L"N25: GPIO_SUS6 ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line9 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , No_Inversion , NA , 19 , SCI , 0x4850 , NORTH ) , // XDP_HLT_BOOT
+ CHV_GPIO_PAD_CONF (L"N26: CX_PREQ_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 20 , NA , 0x4858 , NORTH ) , // PREQ_B
+ CHV_GPIO_PAD_CONF (L"N27: GPIO_SUS9 ", GPIO , M1 , GPI , LOW , NA , Trig_Level , Line15 , NA , NA , NA , NonMaskable , En_RX_Data , Inv_RX_Data , NA , 21 , SCI , 0x4860 , NORTH ) , // GPIO_SUS9
+ CHV_GPIO_PAD_CONF (L"N30: TRST_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 22 , NA , 0x4C00 , NORTH ) , // TRST_B
+ CHV_GPIO_PAD_CONF (L"N31: TCK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 23 , NA , 0x4C08 , NORTH ) , // XDP_TCK
+ CHV_GPIO_PAD_CONF (L"N32: PROCHOT_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 24 , NA , 0x4C10 , NORTH ) , // VR_HOT_N
+ CHV_GPIO_PAD_CONF (L"N33: SVID0_DATA ", Native , M0 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 25 , NA , 0x4C18 , NORTH ) , // SVID_DATA
+ CHV_GPIO_PAD_CONF (L"N34: TMS ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 26 , NA , 0x4C20 , NORTH ) , // XDP_TMS
+ CHV_GPIO_PAD_CONF (L"N35: CX_PRDY_B2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 27 , NA , 0x4C28 , NORTH ) , // PRDY_B2
+ CHV_GPIO_PAD_CONF (L"N36: TDO_2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 28 , NA , 0x4C30 , NORTH ) , //
+ CHV_GPIO_PAD_CONF (L"N37: CX_PRDY_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 29 , NA , 0x4C38 , NORTH ) , // CX_PRDY_B
+ CHV_GPIO_PAD_CONF (L"N38: SVID0_ALERT_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_RX_Data , NA , 30 , NA , 0x4C40 , NORTH ) , // SVID0_ALERT_B
+ CHV_GPIO_PAD_CONF (L"N39: TDO ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 31 , NA , 0x4C48 , NORTH ) , // XDP_TDO
+ CHV_GPIO_PAD_CONF (L"N40: SVID0_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 32 , NA , 0x4C50 , NORTH ) , // SVD_CLK
+ CHV_GPIO_PAD_CONF (L"N41: TDI ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 33 , NA , 0x4C58 , NORTH ) , // XDP_TDI
+ CHV_GPIO_PAD_CONF (L"N45: GP_CAMERASB05 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 34 , NA , 0x5000 , NORTH ) , // FLASH_TORCH
+ CHV_GPIO_PAD_CONF (L"N46: GP_CAMERASB02 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 35 , NA , 0x5008 , NORTH ) , // GPIO_FLHD_N
+ CHV_GPIO_PAD_CONF (L"N47: GP_CAMERASB08 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 36 , NA , 0x5010 , NORTH ) , // XDP_GP_CAMERASB08
+ CHV_GPIO_PAD_CONF (L"N48: GP_CAMERASB00 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 37 , NA , 0x5018 , NORTH ) , // CAM_ACT_LED
+ CHV_GPIO_PAD_CONF (L"N49: GP_CAMERASB06 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 38 , NA , 0x5020 , NORTH ) , // CAM1_PWRDWN
+ CHV_GPIO_PAD_CONF (L"N50: GP_CAMERASB10 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 39 , NA , 0x5028 , NORTH ) , // CAM_2_RST_N
+ CHV_GPIO_PAD_CONF (L"N51: GP_CAMERASB03 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 40 , NA , 0x5030 , NORTH ) , // XDP_GP_CAMERASB03
+ CHV_GPIO_PAD_CONF (L"N52: GP_CAMERASB09 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 41 , NA , 0x5038 , NORTH ) , // CAM_1_RST_N
+ CHV_GPIO_PAD_CONF (L"N53: GP_CAMERASB01 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 42 , NA , 0x5040 , NORTH ) , // FLASH_RESET_N
+ CHV_GPIO_PAD_CONF (L"N54: GP_CAMERASB07 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 43 , NA , 0x5048 , NORTH ) , // CAM2_PWRDWN
+ CHV_GPIO_PAD_CONF (L"N55: GP_CAMERASB11 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 44 , NA , 0x5050 , NORTH ) , // CAM_3_RST_N
+ CHV_GPIO_PAD_CONF (L"N56: GP_CAMERASB04 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 45 , NA , 0x5058 , NORTH ) , // FLASH_TRIG
+ CHV_GPIO_PAD_CONF (L"N60: PANEL0_BKLTEN ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 46 , NA , 0x5400 , NORTH ) , // BRD_ID_BIT_1
+ CHV_GPIO_PAD_CONF (L"N61: HV_DDI0_HPD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 47 , NA , 0x5408 , NORTH ) , // SOC_HDMI_HPD
+ CHV_GPIO_PAD_CONF (L"N62: HV_DDI2_DDC_SDA ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 48 , NA , 0x5410 , NORTH ) , // UART0_RXD (Default) || DDI1_DDC_SCA
+ CHV_GPIO_PAD_CONF (L"N63: PANEL1_BKLTCTL ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 49 , NA , 0x5418 , NORTH ) , //
+ CHV_GPIO_PAD_CONF (L"N64: HV_DDI1_HPD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 50 , NA , 0x5420 , NORTH ) , // SOC_DP1_HPD
+ CHV_GPIO_PAD_CONF (L"N65: PANEL0_BKLTCTL ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 51 , NA , 0x5428 , NORTH ) , // BRD_ID_BIT_0
+ CHV_GPIO_PAD_CONF (L"N66: HV_DDI0_DDC_SDA ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 52 , NA , 0x5430 , NORTH ) , // HDMI_SMB_SOC_SDA
+ CHV_GPIO_PAD_CONF (L"N67: HV_DDI2_DDC_SCL ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 53 , NA , 0x5438 , NORTH ) , // UART0_TXD (Default) || DDI1_DDC_SCL
+ CHV_GPIO_PAD_CONF (L"N68: HV_DDI2_HPD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 54 , NA , 0x5440 , NORTH ) , // SOC_DP2_HPD
+ CHV_GPIO_PAD_CONF (L"N69: PANEL1_VDDEN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 55 , NA , 0x5448 , NORTH ) , //
+ CHV_GPIO_PAD_CONF (L"N70: PANEL1_BKLTEN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 56 , NA , 0x5450 , NORTH ) , //
+ CHV_GPIO_PAD_CONF (L"N71: HV_DDI0_DDC_SCL ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 57 , NA , 0x5458 , NORTH ) , // HDMI_SMB_SOC_SCL
+ CHV_GPIO_PAD_CONF (L"N72: PANEL0_VDDEN ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 58 , NA , 0x5460 , NORTH ) , // BRD_ID_BIT_2
+
+ //
+ // East Community
+ // Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks
+ //
+ CHV_GPIO_PAD_CONF (L"E00: PMU_SLP_S3_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 0 , NA , 0x4400 , EAST ) , // SLP_S3_3P3_N
+ CHV_GPIO_PAD_CONF (L"E01: PMU_BATLOW_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 1 , NA , 0x4408 , EAST ) , // PMU_BATLOW_N
+ CHV_GPIO_PAD_CONF (L"E02: SUS_STAT_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 2 , NA , 0x4410 , EAST ) , // SUS_STAT_N
+ CHV_GPIO_PAD_CONF (L"E03: PMU_SLP_S0IX_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , EAST ) , // SLP_S01X_3P3_N
+ CHV_GPIO_PAD_CONF (L"E04: PMU_AC_PRESENT ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 4 , NA , 0x4420 , EAST ) , // PMU_AC_PRESENT
+ CHV_GPIO_PAD_CONF (L"E05: PMU_PLTRST_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 5 , NA , 0x4428 , EAST ) , // PLTRST_3P3_N
+ CHV_GPIO_PAD_CONF (L"E06: PMU_SUSCLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 6 , NA , 0x4430 , EAST ) , // SUSCLK_3P3
+ CHV_GPIO_PAD_CONF (L"E07: PMU_SLP_LAN_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 7 , NA , 0x4438 , EAST ) , // Not Used, Available
+ CHV_GPIO_PAD_CONF (L"E08: PMU_PWRBTN_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 8 , NA , 0x4440 , EAST ) , // SOC_PWRBTN_N special programming below
+ CHV_GPIO_PAD_CONF (L"E09: PMU_SLP_S4_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 9 , NA , 0x4448 , EAST ) , // SLP_S4_3P3_N
+ CHV_GPIO_PAD_CONF (L"E10: PMU_WAKE_B ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , No_Inversion , NA , 10 , NA , 0x4450 , EAST ) , // PMU_3P3_WAKE_N
+ CHV_GPIO_PAD_CONF (L"E11: PMU_WAKE_LAN_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 11 , NA , 0x4458 , EAST ) , // Not Used, Available
+ CHV_GPIO_PAD_CONF (L"E15: MF_ISH_GPIO_3 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , NA , 0x4800 , EAST ) , // FAB ID bit 3
+ CHV_GPIO_PAD_CONF (L"E16: MF_ISH_GPIO_7 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 13 , NA , 0x4808 , EAST ) , // Not Used, Test points
+ CHV_GPIO_PAD_CONF (L"E17: MF_ISH_I2C1_SCL ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 14 , NA , 0x4810 , EAST ) , // Not Used, Test points
+ CHV_GPIO_PAD_CONF (L"E18: MF_ISH_GPIO_1 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 15 , NA , 0x4818 , EAST ) , // FAB ID bit 1
+ CHV_GPIO_PAD_CONF (L"E19: MF_ISH_GPIO_5 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 16 , NA , 0x4820 , EAST ) , // Not Used, Test points
+ CHV_GPIO_PAD_CONF (L"E20: MF_ISH_GPIO_9 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4828 , EAST ) , // Not Used, Test points
+ CHV_GPIO_PAD_CONF (L"E21: MF_ISH_GPIO_0 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 18 , NA , 0x4830 , EAST ) , // FAB ID bit 0
+ CHV_GPIO_PAD_CONF (L"E22: MF_ISH_GPIO_4 ", GPIO , M1 , GPI , NA , NA , NA , Line0 , NA , NA , NA , NonMaskable , NA , No_Inversion , NA , 19 , NA , 0x4838 , EAST ) , // Not Used, Test points
+ CHV_GPIO_PAD_CONF (L"E23: MF_ISH_GPIO_8 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 20 , NA , 0x4840 , EAST ) , // Not Used, Test points
+ CHV_GPIO_PAD_CONF (L"E24: MF_ISH_GPIO_2 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 21 , NA , 0x4848 , EAST ) , // FAB ID bit 2
+ CHV_GPIO_PAD_CONF (L"E25: MF_ISH_GPIO_6 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 22 , NA , 0x4850 , EAST ) , // Not Used, Test points
+ CHV_GPIO_PAD_CONF (L"E26: MF_ISH_I2C1_SDA ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 23 , NA , 0x4858 , EAST ) , // Not Used, Test points
+ //
+ // South East Community
+ // Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks
+ //
+ CHV_GPIO_PAD_CONF (L"SE00: MF_PLT_CLK0 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 0 , NA , 0x4400 , SOUTHEAST ) , // CAM_1_MCLK Camera1_clock
+ CHV_GPIO_PAD_CONF (L"SE01: PWM1 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 1 , NA , 0x4408 , SOUTHEAST ) , // WIFI_PCIE_RST_N
+ CHV_GPIO_PAD_CONF (L"SE02: MF_PLT_CLK1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 1 , NA , 0x4410 , SOUTHEAST ) , // CAM_2_MCLK Camera2_clock
+ CHV_GPIO_PAD_CONF (L"SE03: MF_PLT_CLK4 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , SOUTHEAST ) , // Not Used
+ CHV_GPIO_PAD_CONF (L"SE04: MF_PLT_CLK3 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 4 , NA , 0x4420 , SOUTHEAST ) , // I2S_MCLK
+ CHV_GPIO_PAD_CONF (L"SE05: PWM0 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 5 , NA , 0x4428 , SOUTHEAST ) , //
+ CHV_GPIO_PAD_CONF (L"SE06: MF_PLT_CLK5 ", GPIO , M3 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 6 , NA , 0x4430 , SOUTHEAST ) , // Not Used
+ CHV_GPIO_PAD_CONF (L"SE07: MF_PLT_CLK2 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 7 , NA , 0x4438 , SOUTHEAST ) , // Not Used
+ CHV_GPIO_PAD_CONF (L"SE15: SDMMC2_D3_CD_B ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 8 , NA , 0x4800 , SOUTHEAST ) , // NGFF_SDEMMC2_D3
+ CHV_GPIO_PAD_CONF (L"SE16: SDMMC1_CLK ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_L , NA , NA , NA , NA , No_Inversion , NA , 9 , NA , 0x4808 , SOUTHEAST ) , // EMMC1_CLK
+ CHV_GPIO_PAD_CONF (L"SE17: SDMMC1_D0 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 10 , NA , 0x4810 , SOUTHEAST ) , // EMMC1_D_0
+ CHV_GPIO_PAD_CONF (L"SE18: SDMMC2_D1 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 11 , NA , 0x4818 , SOUTHEAST ) , // NGFF_SDEMMC2_D1
+ CHV_GPIO_PAD_CONF (L"SE19: SDMMC2_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , NA , 0x4820 , SOUTHEAST ) , // NGFF_SDEMMC2_CLK
+ CHV_GPIO_PAD_CONF (L"SE20: SDMMC1_D2 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 13 , NA , 0x4828 , SOUTHEAST ) , // EMMC1_D_2
+ CHV_GPIO_PAD_CONF (L"SE21: SDMMC2_D2 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 14 , NA , 0x4830 , SOUTHEAST ) , // NGFF_SDEMMC2_D2
+ CHV_GPIO_PAD_CONF (L"SE22: SDMMC2_CMD ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 15 , NA , 0x4838 , SOUTHEAST ) , // NGFF_SDEMMC2_CM
+ CHV_GPIO_PAD_CONF (L"SE23: SDMMC1_CMD ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 16 , NA , 0x4840 , SOUTHEAST ) , // EMMC1_CMD
+ CHV_GPIO_PAD_CONF (L"SE24: SDMMC1_D1 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4848 , SOUTHEAST ) , // EMMC1_D_1
+ CHV_GPIO_PAD_CONF (L"SE25: SDMMC2_D0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 18 , NA , 0x4850 , SOUTHEAST ) , // NGFF_SDEMMC2_D0
+ CHV_GPIO_PAD_CONF (L"SE26: SDMMC1_D3_CD_B ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 19 , NA , 0x4858 , SOUTHEAST ) , // EMMC1_D_3
+ CHV_GPIO_PAD_CONF (L"SE30: SDMMC3_D1 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 20 , NA , 0x4C00 , SOUTHEAST ) , // SD_CARD_D1
+ CHV_GPIO_PAD_CONF (L"SE31: SDMMC3_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 21 , NA , 0x4C08 , SOUTHEAST ) , // SD_CARD_CLK
+ CHV_GPIO_PAD_CONF (L"SE32: SDMMC3_D3 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 22 , NA , 0x4C10 , SOUTHEAST ) , // SD_CARD_D3
+ CHV_GPIO_PAD_CONF (L"SE33: SDMMC3_D2 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 23 , NA , 0x4C18 , SOUTHEAST ) , // SD_CARD_D2
+ CHV_GPIO_PAD_CONF (L"SE34: SDMMC3_CMD ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 24 , NA , 0x4C20 , SOUTHEAST ) , // SD_CARD_CMD
+ CHV_GPIO_PAD_CONF (L"SE35: SDMMC3_D0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 25 , NA , 0x4C28 , SOUTHEAST ) , // SD_CARD_D0
+ CHV_GPIO_PAD_CONF (L"SE45: MF_LPC_AD2 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 26 , NA , 0x5000 , SOUTHEAST ) , // LPC_AD2
+ CHV_GPIO_PAD_CONF (L"SE46: LPC_CLKRUNB ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 27 , NA , 0x5008 , SOUTHEAST ) , // L_CLKRUN_N
+ CHV_GPIO_PAD_CONF (L"SE47: MF_LPC_AD0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 28 , NA , 0x5010 , SOUTHEAST ) , // LPC_AD0
+ CHV_GPIO_PAD_CONF (L"SE48: LPC_FRAMEB ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 29 , NA , 0x5018 , SOUTHEAST ) , // L_FRAME_N
+ CHV_GPIO_PAD_CONF (L"SE49: MF_LPC_CLKOUT1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 30 , NA , 0x5020 , SOUTHEAST ) , // L_CLKOUT1
+ CHV_GPIO_PAD_CONF (L"SE50: MF_LPC_AD3 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 31 , NA , 0x5028 , SOUTHEAST ) , // LPC_AD3
+ CHV_GPIO_PAD_CONF (L"SE51: MF_LPC_CLKOUT0 ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , No_Inversion , NA , 32 , NA , 0x5030 , SOUTHEAST ) , // L_CLKOUT0
+ CHV_GPIO_PAD_CONF (L"SE52: MF_LPC_AD1 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 33 , NA , 0x5038 , SOUTHEAST ) , // LPC_AD1
+ CHV_GPIO_PAD_CONF (L"SE60: SPI1_MISO ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 34 , NA , 0x5400 , SOUTHEAST ) , // SPI1_MISO
+ CHV_GPIO_PAD_CONF (L"SE61: SPI1_CS0_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 35 , NA , 0x5408 , SOUTHEAST ) , // SPI1_CS0_N
+ CHV_GPIO_PAD_CONF (L"SE62: SPI1_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 36 , NA , 0x5410 , SOUTHEAST ) , // SPI1_CLK
+ CHV_GPIO_PAD_CONF (L"SE63: MMC1_D6 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 37 , NA , 0x5418 , SOUTHEAST ) , // EMMC1_D6
+ CHV_GPIO_PAD_CONF (L"SE64: SPI1_MOSI ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 38 , NA , 0x5420 , SOUTHEAST ) , // SPI1_MOSI
+ CHV_GPIO_PAD_CONF (L"SE65: MMC1_D5 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 39 , NA , 0x5428 , SOUTHEAST ) , // EMMC1_D5
+ CHV_GPIO_PAD_CONF (L"SE66: SPI1_CS1_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 40 , NA , 0x5430 , SOUTHEAST ) , // SPI1_CS1_N
+ CHV_GPIO_PAD_CONF (L"SE67: MMC1_D4_SD_WE ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 41 , NA , 0x5438 , SOUTHEAST ) , // EMMC1_D4
+ CHV_GPIO_PAD_CONF (L"SE68: MMC1_D7 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 42 , NA , 0x5440 , SOUTHEAST ) , // EMMC1_D7
+ CHV_GPIO_PAD_CONF (L"SE69: MMC1_RCLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 43 , NA , 0x5448 , SOUTHEAST ) , // EMMC1_RCLK
+ CHV_GPIO_PAD_CONF (L"SE75: USB_OC1_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 44 , NA , 0x5800 , SOUTHEAST ) , // USB3_OC1_N
+ CHV_GPIO_PAD_CONF (L"SE76: PMU_RSTBUTTON_B", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 45 , NA , 0x5808 , SOUTHEAST ) , // SOC_RESETBTN_N special programming below
+ CHV_GPIO_PAD_CONF (L"SE77: GPIO_ALERT ", GPIO , M1 , GPI , NA , NA , Trig_Level , Line2 , NA , NA , NA , NonMaskable , En_RX_Data , Inv_RX_Data , NA , 46 , NA , 0x5810 , SOUTHEAST ) , // DCN : 2502579 - Programmed for TCH_PAD_INT_N
+ CHV_GPIO_PAD_CONF (L"SE78: SDMMC3_PWR_EN_B", Native , M1 , NA , NA , NA , NA , NA , P_20K_L , NA , NA , NA , NA , No_Inversion , NA , 47 , NA , 0x5818 , SOUTHEAST ) , // SD_CARD_PWRDN_N
+ CHV_GPIO_PAD_CONF (L"SE79: ILB_SERIRQ ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 48 , NA , 0x5820 , SOUTHEAST ) , // ILB_SERIRQ
+ CHV_GPIO_PAD_CONF (L"SE80: USB_OC0_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 49 , NA , 0x5828 , SOUTHEAST ) , // USB3_OC0_N
+ CHV_GPIO_PAD_CONF (L"SE81: SDMMC3_CD_B ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 50 , NA , 0x5830 , SOUTHEAST ) , // SD_CARD_DET_N
+ CHV_GPIO_PAD_CONF (L"SE82: SPKR ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 51 , NA , 0x5838 , SOUTHEAST ) , // SPKR
+ CHV_GPIO_PAD_CONF (L"SE83: SUSPWRDNACK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 52 , NA , 0x5840 , SOUTHEAST ) , // SUSPWRDNACK_3P3
+ CHV_GPIO_PAD_CONF (L"SE84: SPARE_PIN ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 53 , NA , 0x5848 , SOUTHEAST ) , // SPARE_PIN
+ CHV_GPIO_PAD_CONF (L"SE85: SDMMC3_1P8_EN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 54 , NA , 0x5850 , SOUTHEAST ) , // SD_CARD_PWR_EN
+ //
+ // South west Community
+ // Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks
+ //
+ CHV_GPIO_PAD_CONF (L"SW00: FST_SPI_D2 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 0 , NA , 0x4400 , SOUTHWEST ) , // FST_SPI_D2
+ CHV_GPIO_PAD_CONF (L"SW01: FST_SPI_D0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 1 , NA , 0x4408 , SOUTHWEST ) , // FST_SPI_D0
+ CHV_GPIO_PAD_CONF (L"SW02: FST_SPI_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 2 , NA , 0x4410 , SOUTHWEST ) , // FAST_SPI_CLK
+ CHV_GPIO_PAD_CONF (L"SW03: FST_SPI_D3 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , SOUTHWEST ) , // FST_SPI_D3
+ CHV_GPIO_PAD_CONF (L"SW04: FST_SPI_CS1_B ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 4 , NA , 0x4420 , SOUTHWEST ) , // V3P3DX_TCH_EN
+ CHV_GPIO_PAD_CONF (L"SW05: FST_SPI_D1 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 5 , NA , 0x4428 , SOUTHWEST ) , // FST_SPI_D1
+ CHV_GPIO_PAD_CONF (L"SW06: FST_SPI_CS0_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 6 , NA , 0x4430 , SOUTHWEST ) , // FST_SPI_CS_N
+ CHV_GPIO_PAD_CONF (L"SW07: FST_SPI_CS2_B ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 7 , NA , 0x4438 , SOUTHWEST ) , // FST_SPI_CS2_N (SPI TPM)
+ CHV_GPIO_PAD_CONF (L"SW15: UART1_RTS_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 8 , NA , 0x4800 , SOUTHWEST ) , // UART_BT_RTS
+ CHV_GPIO_PAD_CONF (L"SW16: UART1_RXD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 9 , NA , 0x4808 , SOUTHWEST ) , // UART_BT_RXD
+ CHV_GPIO_PAD_CONF (L"SW17: UART2_RXD ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , No_Inversion , NA , 10 , NA , 0x4810 , SOUTHWEST ) , // UART_GPS_RXD
+ CHV_GPIO_PAD_CONF (L"SW18: UART1_CTS_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 11 , NA , 0x4818 , SOUTHWEST ) , // UART_BT_CTS
+ CHV_GPIO_PAD_CONF (L"SW19: UART2_RTS_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , NA , 0x4820 , SOUTHWEST ) , // UART_GPS_RTS
+ CHV_GPIO_PAD_CONF (L"SW20: UART1_TXD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 13 , NA , 0x4828 , SOUTHWEST ) , // UART_BT_TXD
+ CHV_GPIO_PAD_CONF (L"SW21: UART2_TXD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 14 , NA , 0x4830 , SOUTHWEST ) , // UART_GPS_TXD
+ CHV_GPIO_PAD_CONF (L"SW22: UART2_CTS_B ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , No_Inversion , NA , 15 , NA , 0x4838 , SOUTHWEST ) , // UART_GPS_CTS
+ CHV_GPIO_PAD_CONF (L"SW30: MF_HDA_CLK ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 16 , NA , 0x4C00 , SOUTHWEST ) , // MF_HDA_CLK II GP_SSP_0_I2S_TXD
+ CHV_GPIO_PAD_CONF (L"SW31: MF_HDA_RSTB ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4C08 , SOUTHWEST ) , // AUD_LINK_RST_N
+ CHV_GPIO_PAD_CONF (L"SW32: MF_HDA_SDI0 ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 18 , NA , 0x4C10 , SOUTHWEST ) , // AUD_LINK_SDI0_SOC
+ CHV_GPIO_PAD_CONF (L"SW33: MF_HDA_SDO ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 19 , NA , 0x4C18 , SOUTHWEST ) , // AUD_LINK_SDO
+ CHV_GPIO_PAD_CONF (L"SW34: MF_HDA_DOCKRSTB", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 20 , NA , 0x4C20 , SOUTHWEST ) , // NGFF_I2S_1_TXD_R_BT || I2S_2_TXD_R_AICO
+ CHV_GPIO_PAD_CONF (L"SW35: MF_HDA_SYNC ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 21 , NA , 0x4C28 , SOUTHWEST ) , // AUD_LINK_SYNC
+ CHV_GPIO_PAD_CONF (L"SW36: MF_HDA_SDI1 ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 22 , NA , 0x4C30 , SOUTHWEST ) , // AUD_LINK_SDI1_SOC
+ CHV_GPIO_PAD_CONF (L"SW37: MF_HDA_DOCKENB ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 23 , NA , 0x4C38 , SOUTHWEST ) , // NGFF_I2S_1_RXD_R_BT || I2S_2_RXD_R_AICO
+ CHV_GPIO_PAD_CONF (L"SW45: I2C5_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 24 , NA , 0x5000 , SOUTHWEST ) , // I2C5_SDA_3P3
+ CHV_GPIO_PAD_CONF (L"SW46: I2C4_SDA ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 25 , NA , 0x5008 , SOUTHWEST ) , // HV_DDI2_DDC_SDA
+ CHV_GPIO_PAD_CONF (L"SW47: I2C6_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 26 , NA , 0x5010 , SOUTHWEST ) , //
+ CHV_GPIO_PAD_CONF (L"SW48: I2C5_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 27 , NA , 0x5018 , SOUTHWEST ) , // I2C5_SDA_3P3
+ CHV_GPIO_PAD_CONF (L"SW49: I2C_NFC_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 28 , NA , 0x5020 , SOUTHWEST ) , // I2C_NFC_SDA_3P3
+ CHV_GPIO_PAD_CONF (L"SW50: I2C4_SCL ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 29 , NA , 0x5028 , SOUTHWEST ) , // HV_DDI2_DDC_SCL
+ CHV_GPIO_PAD_CONF (L"SW51: I2C6_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 30 , NA , 0x5030 , SOUTHWEST ) , //
+ CHV_GPIO_PAD_CONF (L"SW52: I2C_NFC_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 31 , NA , 0x5038 , SOUTHWEST ) , // I2C_NFC_SCL_3P3
+ CHV_GPIO_PAD_CONF (L"SW60: I2C1_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 32 , NA , 0x5400 , SOUTHWEST ) , // I2C1_SCL_AUD_CONN
+ CHV_GPIO_PAD_CONF (L"SW61: I2C0_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 33 , NA , 0x5408 , SOUTHWEST ) , // I2C_3P3_NGFF_SCL
+ CHV_GPIO_PAD_CONF (L"SW62: I2C2_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 34 , NA , 0x5410 , SOUTHWEST ) , // I2C2_SCL_CAM
+ CHV_GPIO_PAD_CONF (L"SW63: I2C1_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 35 , NA , 0x5418 , SOUTHWEST ) , // I2C1_SDA_AUD_CONN
+ CHV_GPIO_PAD_CONF (L"SW64: I2C3_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 36 , NA , 0x5420 , SOUTHWEST ) , // I2C3_CAM_SCL
+ CHV_GPIO_PAD_CONF (L"SW65: I2C0_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 37 , NA , 0x5428 , SOUTHWEST ) , // I2C_3P3_NGFF_SDA
+ CHV_GPIO_PAD_CONF (L"SW66: I2C2_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 38 , NA , 0x5430 , SOUTHWEST ) , // I2C2_SDA_CAM
+ CHV_GPIO_PAD_CONF (L"SW67: I2C3_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 39 , NA , 0x5438 , SOUTHWEST ) , // I2C3_CAM_SDA
+ CHV_GPIO_PAD_CONF (L"SW75: SATA_GP0 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 40 , NA , 0x5800 , SOUTHWEST ) , // reserved for SATA (Interlock switch)
+ CHV_GPIO_PAD_CONF (L"SW76: SATA_GP1 ", GPIO , M1 , GPI , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 41 , NA , 0x5808 , SOUTHWEST ) , // GPI to select UART0 | DDI1 mode
+ CHV_GPIO_PAD_CONF (L"SW77: SATA_LEDN ", Native , M1 , NA , NA , NA , NA , NA , NA , _ENABLE , NA , NA , NA , No_Inversion , NA , 42 , NA , 0x5810 , SOUTHWEST ) , // SATA_LED_N
+ CHV_GPIO_PAD_CONF (L"SW78: SATA_GP2 ", Native , M1 , NA , NA , NA , NA , NA , NA , _ENABLE , NA , NA , NA , No_Inversion , NA , 43 , NA , 0x5818 , SOUTHWEST ) , // SATA_DEVSLP0 -need to check
+ CHV_GPIO_PAD_CONF (L"SW79: MF_SMB_ALERTB ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 44 , NA , 0x5820 , SOUTHWEST ) , // SMB_ALERTB_3P3
+ CHV_GPIO_PAD_CONF (L"SW80: SATA_GP3 ", GPIO , M2 , GPI , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 45 , NA , 0x5828 , SOUTHWEST ) , // TOUCH_RST_N -need to check
+ CHV_GPIO_PAD_CONF (L"SW81: MF_SMB_CLK ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 46 , NA , 0x5830 , SOUTHWEST ) , // SMB_3P3_CLK
+ CHV_GPIO_PAD_CONF (L"SW82: MF_SMB_DATA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 47 , NA , 0x5838 , SOUTHWEST ) , // SMB_3P3_DAT
+ CHV_GPIO_PAD_CONF (L"SW90: PCIE_CLKREQ0B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 48 , NA , 0x5C00 , SOUTHWEST ) , //
+ CHV_GPIO_PAD_CONF (L"SW91: PCIE_CLKREQ1B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 49 , NA , 0x5C08 , SOUTHWEST ) , // PCIE_CLKREQ1_N
+ CHV_GPIO_PAD_CONF (L"SW92: GP_SSP_2_CLK ", Native , M1 , NA , NA , NA , NA , NA , P_20K_L , NA , NA , NA , NA , No_Inversion , NA , 50 , NA , 0x5C10 , SOUTHWEST ) , // PCIE_CLKREQ1_N
+ CHV_GPIO_PAD_CONF (L"SW93: PCIE_CLKREQ2B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 51 , NA , 0x5C18 , SOUTHWEST ) , // PCIE_CLKREQ2_N
+ CHV_GPIO_PAD_CONF (L"SW94: GP_SSP_2_RXD ", Native , M1 , NA , NA , NA , NA , NA , P_20K_L , NA , NA , NA , NA , No_Inversion , NA , 52 , NA , 0x5C20 , SOUTHWEST ) , //
+ CHV_GPIO_PAD_CONF (L"SW95: PCIE_CLKREQ3B ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 53 , NA , 0x5C28 , SOUTHWEST ) , // SDMMC3_WP (Def)
+ CHV_GPIO_PAD_CONF (L"SW96: GP_SSP_2_FS ", Native , M1 , NA , NA , NA , NA , NA , P_20K_L , NA , NA , NA , NA , No_Inversion , NA , 54 , NA , 0x5C30 , SOUTHWEST ) , // I2S_2_FS
+ CHV_GPIO_PAD_CONF (L"SW97: GP_SSP_2_TXD ", Native , M1 , NA , NA , NA , NA , NA , P_20K_L , NA , NA , NA , NA , Inv_TX_Enable , NA , 55 , NA , 0x5C38 , SOUTHWEST ) , // I2S_2_TXD
+};
+
+CHAR16* GPIOPadNames[GPIO_TABLE_ROW_NUM] = {
+ //
+ // North Community
+ //
+ L"N00: GPIO_DFX0 ",
+ L"N01: GPIO_DFX3 ",
+ L"N02: GPIO_DFX7 ",
+ L"N03: GPIO_DFX1 ",
+ L"N04: GPIO_DFX5 ",
+ L"N05: GPIO_DFX4 ",
+ L"N06: GPIO_DFX8 ",
+ L"N07: GPIO_DFX2 ",
+ L"N08: GPIO_DFX6 ",
+ L"N15: GPIO_SUS0 ",
+ L"N16: SEC_GPIO_SUS10 ",
+ L"N17: GPIO_SUS3 ",
+ L"N18: GPIO_SUS7 ",
+ L"N19: GPIO_SUS1 ",
+ L"N20: GPIO_SUS5 ",
+ L"N21: SEC_GPIO_SUS11 ",
+ L"N22: GPIO_SUS4 ",
+ L"N23: SEC_GPIO_SUS8 ",
+ L"N24: GPIO_SUS2 ",
+ L"N25: GPIO_SUS6 ",
+ L"N26: CX_PREQ_B ",
+ L"N27: GPIO_SUS9 ",
+ L"N30: TRST_B ",
+ L"N31: TCK ",
+ L"N32: PROCHOT_B ",
+ L"N33: SVID0_DATA ",
+ L"N34: TMS ",
+ L"N35: CX_PRDY_B2 ",
+ L"N36: TDO_2 ",
+ L"N37: CX_PRDY_B ",
+ L"N38: SVID0_ALERT_B ",
+ L"N39: TDO ",
+ L"N40: SVID0_CLK ",
+ L"N41: TDI ",
+ L"N45: GP_CAMERASB05 ",
+ L"N46: GP_CAMERASB02 ",
+ L"N47: GP_CAMERASB08 ",
+ L"N48: GP_CAMERASB00 ",
+ L"N49: GP_CAMERASB06 ",
+ L"N50: GP_CAMERASB10 ",
+ L"N51: GP_CAMERASB03 ",
+ L"N52: GP_CAMERASB09 ",
+ L"N53: GP_CAMERASB01 ",
+ L"N54: GP_CAMERASB07 ",
+ L"N55: GP_CAMERASB11 ",
+ L"N56: GP_CAMERASB04 ",
+ L"N60: PANEL0_BKLTEN ",
+ L"N61: HV_DDI0_HPD ",
+ L"N62: HV_DDI2_DDC_SDA ",
+ L"N63: PANEL1_BKLTCTL ",
+ L"N64: HV_DDI1_HPD ",
+ L"N65: PANEL0_BKLTCTL ",
+ L"N66: HV_DDI0_DDC_SDA ",
+ L"N67: HV_DDI2_DDC_SCL ",
+ L"N68: HV_DDI2_HPD ",
+ L"N69: PANEL1_VDDEN ",
+ L"N70: PANEL1_BKLTEN ",
+ L"N71: HV_DDI0_DDC_SCL ",
+ L"N72: PANEL0_VDDEN ",
+ //
+ // East Community
+ //
+ L"E00: PMU_SLP_S3_B ",
+ L"E01: PMU_BATLOW_B ",
+ L"E02: SUS_STAT_B ",
+ L"E03: PMU_SLP_S0IX_B ",
+ L"E04: PMU_AC_PRESENT ",
+ L"E05: PMU_PLTRST_B ",
+ L"E06: PMU_SUSCLK ",
+ L"E07: PMU_SLP_LAN_B ",
+ L"E08: PMU_PWRBTN_B ",
+ L"E09: PMU_SLP_S4_B ",
+ L"E10: PMU_WAKE_B ",
+ L"E11: PMU_WAKE_LAN_B ",
+ L"E15: MF_ISH_GPIO_3 ",
+ L"E16: MF_ISH_GPIO_7 ",
+ L"E17: MF_ISH_I2C1_SCL ",
+ L"E18: MF_ISH_GPIO_1 ",
+ L"E19: MF_ISH_GPIO_5 ",
+ L"E20: MF_ISH_GPIO_9 ",
+ L"E21: MF_ISH_GPIO_0 ",
+ L"E22: MF_ISH_GPIO_4 ",
+ L"E23: MF_ISH_GPIO_8 ",
+ L"E24: MF_ISH_GPIO_2 ",
+ L"E25: MF_ISH_GPIO_6 ",
+ L"E26: MF_ISH_I2C1_SDA ",
+ //
+ // South East Community
+ //
+ L"SE00: MF_PLT_CLK0 ",
+ L"SE01: PWM1 ",
+ L"SE02: MF_PLT_CLK1 ",
+ L"SE03: MF_PLT_CLK4 ",
+ L"SE04: MF_PLT_CLK3 ",
+ L"SE05: PWM0 ",
+ L"SE06: MF_PLT_CLK5 ",
+ L"SE07: MF_PLT_CLK2 ",
+ L"SE15: SDMMC2_D3_CD_B ",
+ L"SE16: SDMMC1_CLK ",
+ L"SE17: SDMMC1_D0 ",
+ L"SE18: SDMMC2_D1 ",
+ L"SE19: SDMMC2_CLK ",
+ L"SE20: SDMMC1_D2 ",
+ L"SE21: SDMMC2_D2 ",
+ L"SE22: SDMMC2_CMD ",
+ L"SE23: SDMMC1_CMD ",
+ L"SE24: SDMMC1_D1 ",
+ L"SE25: SDMMC2_D0 ",
+ L"SE26: SDMMC1_D3_CD_B ",
+ L"SE30: SDMMC3_D1 ",
+ L"SE31: SDMMC3_CLK ",
+ L"SE32: SDMMC3_D3 ",
+ L"SE33: SDMMC3_D2 ",
+ L"SE34: SDMMC3_CMD ",
+ L"SE35: SDMMC3_D0 ",
+ L"SE45: MF_LPC_AD2 ",
+ L"SE46: LPC_CLKRUNB ",
+ L"SE47: MF_LPC_AD0 ",
+ L"SE48: LPC_FRAMEB ",
+ L"SE49: MF_LPC_CLKOUT1 ",
+ L"SE50: MF_LPC_AD3 ",
+ L"SE51: MF_LPC_CLKOUT0 ",
+ L"SE52: MF_LPC_AD1 ",
+ L"SE60: SPI1_MISO ",
+ L"SE61: SPI1_CS0_B ",
+ L"SE62: SPI1_CLK ",
+ L"SE63: MMC1_D6 ",
+ L"SE64: SPI1_MOSI ",
+ L"SE65: MMC1_D5 ",
+ L"SE66: SPI1_CS1_B ",
+ L"SE67: MMC1_D4_SD_WE ",
+ L"SE68: MMC1_D7 ",
+ L"SE69: MMC1_RCLK ",
+ L"SE75: USB_OC1_B ",
+ L"SE76: PMU_RSTBUTTON_B",
+ L"SE77: GPIO_ALERT ",
+ L"SE78: SDMMC3_PWR_EN_B",
+ L"SE79: ILB_SERIRQ ",
+ L"SE80: USB_OC0_B ",
+ L"SE81: SDMMC3_CD_B ",
+ L"SE82: SPKR ",
+ L"SE83: SUSPWRDNACK ",
+ L"SE84: SPARE_PIN ",
+ L"SE85: SDMMC3_1P8_EN ",
+ //
+ // South west Community
+ //
+ L"SW00: FST_SPI_D2 ",
+ L"SW01: FST_SPI_D0 ",
+ L"SW02: FST_SPI_CLK ",
+ L"SW03: FST_SPI_D3 ",
+ L"SW04: FST_SPI_CS1_B ",
+ L"SW05: FST_SPI_D1 ",
+ L"SW06: FST_SPI_CS0_B ",
+ L"SW07: FST_SPI_CS2_B ",
+ L"SW15: UART1_RTS_B ",
+ L"SW16: UART1_RXD ",
+ L"SW17: UART2_RXD ",
+ L"SW18: UART1_CTS_B ",
+ L"SW19: UART2_RTS_B ",
+ L"SW20: UART1_TXD ",
+ L"SW21: UART2_TXD ",
+ L"SW22: UART2_CTS_B ",
+ L"SW30: MF_HDA_CLK ",
+ L"SW31: MF_HDA_RSTB ",
+ L"SW32: MF_HDA_SDI0 ",
+ L"SW33: MF_HDA_SDO ",
+ L"SW34: MF_HDA_DOCKRSTB",
+ L"SW35: MF_HDA_SYNC ",
+ L"SW36: MF_HDA_SDI1 ",
+ L"SW37: MF_HDA_DOCKENB ",
+ L"SW45: I2C5_SDA ",
+ L"SW46: I2C4_SDA ",
+ L"SW47: I2C6_SDA ",
+ L"SW48: I2C5_SCL ",
+ L"SW49: I2C_NFC_SDA ",
+ L"SW50: I2C4_SCL ",
+ L"SW51: I2C6_SCL ",
+ L"SW52: I2C_NFC_SCL ",
+ L"SW60: I2C1_SDA ",
+ L"SW61: I2C0_SDA ",
+ L"SW62: I2C2_SDA ",
+ L"SW63: I2C1_SCL ",
+ L"SW64: I2C3_SDA ",
+ L"SW65: I2C0_SCL ",
+ L"SW66: I2C2_SCL ",
+ L"SW67: I2C3_SCL ",
+ L"SW75: SATA_GP0 ",
+ L"SW76: SATA_GP1 ",
+ L"SW77: SATA_LEDN ",
+ L"SW78: SATA_GP2 ",
+ L"SW79: MF_SMB_ALERTB ",
+ L"SW80: SATA_GP3 ",
+ L"SW81: MF_SMB_CLK ",
+ L"SW82: MF_SMB_DATA ",
+ L"SW90: PCIE_CLKREQ0B ",
+ L"SW91: PCIE_CLKREQ1B ",
+ L"SW92: GP_SSP_2_CLK ",
+ L"SW93: PCIE_CLKREQ2B ",
+ L"SW94: GP_SSP_2_RXD ",
+ L"SW95: PCIE_CLKREQ3B ",
+ L"SW96: GP_SSP_2_FS ",
+ L"SW97: GP_SSP_2_TXD "
+};
+
+UINT16 GPIOMmioOffset[GPIO_TABLE_ROW_NUM] = {
+ //
+ // North Community
+ //
+ 0x4400 ,
+ 0x4408 ,
+ 0x4410 ,
+ 0x4418 ,
+ 0x4420 ,
+ 0x4428 ,
+ 0x4430 ,
+ 0x4438 ,
+ 0x4440 ,
+ 0x4800 ,
+ 0x4808 ,
+ 0x4810 ,
+ 0x4818 ,
+ 0x4820 ,
+ 0x4828 ,
+ 0x4830 ,
+ 0x4838 ,
+ 0x4840 ,
+ 0x4848 ,
+ 0x4850 ,
+ 0x4858 ,
+ 0x4860 ,
+ 0x4C00 ,
+ 0x4C08 ,
+ 0x4C10 ,
+ 0x4C18 ,
+ 0x4C20 ,
+ 0x4C28 ,
+ 0x4C30 ,
+ 0x4C38 ,
+ 0x4C40 ,
+ 0x4C48 ,
+ 0x4C50 ,
+ 0x4C58 ,
+ 0x5000 ,
+ 0x5008 ,
+ 0x5010 ,
+ 0x5018 ,
+ 0x5020 ,
+ 0x5028 ,
+ 0x5030 ,
+ 0x5038 ,
+ 0x5040 ,
+ 0x5048 ,
+ 0x5050 ,
+ 0x5058 ,
+ 0x5400 ,
+ 0x5408 ,
+ 0x5410 ,
+ 0x5418 ,
+ 0x5420 ,
+ 0x5428 ,
+ 0x5430 ,
+ 0x5438 ,
+ 0x5440 ,
+ 0x5448 ,
+ 0x5450 ,
+ 0x5458 ,
+ 0x5460 ,
+ //
+ // East Community
+ //
+ 0x4400 ,
+ 0x4408 ,
+ 0x4410 ,
+ 0x4418 ,
+ 0x4420 ,
+ 0x4428 ,
+ 0x4430 ,
+ 0x4438 ,
+ 0x4440 ,
+ 0x4448 ,
+ 0x4450 ,
+ 0x4458 ,
+ 0x4800 ,
+ 0x4808 ,
+ 0x4810 ,
+ 0x4818 ,
+ 0x4820 ,
+ 0x4828 ,
+ 0x4830 ,
+ 0x4838 ,
+ 0x4840 ,
+ 0x4848 ,
+ 0x4850 ,
+ 0x4858 ,
+ //
+ // South East Community
+ //
+ 0x4400 ,
+ 0x4408 ,
+ 0x4410 ,
+ 0x4418 ,
+ 0x4420 ,
+ 0x4428 ,
+ 0x4430 ,
+ 0x4438 ,
+ 0x4800 ,
+ 0x4808 ,
+ 0x4810 ,
+ 0x4818 ,
+ 0x4820 ,
+ 0x4828 ,
+ 0x4830 ,
+ 0x4838 ,
+ 0x4840 ,
+ 0x4848 ,
+ 0x4850 ,
+ 0x4858 ,
+ 0x4C00 ,
+ 0x4C08 ,
+ 0x4C10 ,
+ 0x4C18 ,
+ 0x4C20 ,
+ 0x4C28 ,
+ 0x5000 ,
+ 0x5008 ,
+ 0x5010 ,
+ 0x5018 ,
+ 0x5020 ,
+ 0x5028 ,
+ 0x5030 ,
+ 0x5038 ,
+ 0x5400 ,
+ 0x5408 ,
+ 0x5410 ,
+ 0x5418 ,
+ 0x5420 ,
+ 0x5428 ,
+ 0x5430 ,
+ 0x5438 ,
+ 0x5440 ,
+ 0x5448 ,
+ 0x5800 ,
+ 0x5808 ,
+ 0x5810 ,
+ 0x5818 ,
+ 0x5820 ,
+ 0x5828 ,
+ 0x5830 ,
+ 0x5838 ,
+ 0x5840 ,
+ 0x5848 ,
+ 0x5850 ,
+ //
+ // South west Community
+ //
+ 0x4400 ,
+ 0x4408 ,
+ 0x4410 ,
+ 0x4418 ,
+ 0x4420 ,
+ 0x4428 ,
+ 0x4430 ,
+ 0x4438 ,
+ 0x4800 ,
+ 0x4808 ,
+ 0x4810 ,
+ 0x4818 ,
+ 0x4820 ,
+ 0x4828 ,
+ 0x4830 ,
+ 0x4838 ,
+ 0x4C00 ,
+ 0x4C08 ,
+ 0x4C10 ,
+ 0x4C18 ,
+ 0x4C20 ,
+ 0x4C28 ,
+ 0x4C30 ,
+ 0x4C38 ,
+ 0x5000 ,
+ 0x5008 ,
+ 0x5010 ,
+ 0x5018 ,
+ 0x5020 ,
+ 0x5028 ,
+ 0x5030 ,
+ 0x5038 ,
+ 0x5400 ,
+ 0x5408 ,
+ 0x5410 ,
+ 0x5418 ,
+ 0x5420 ,
+ 0x5428 ,
+ 0x5430 ,
+ 0x5438 ,
+ 0x5800 ,
+ 0x5808 ,
+ 0x5810 ,
+ 0x5818 ,
+ 0x5820 ,
+ 0x5828 ,
+ 0x5830 ,
+ 0x5838 ,
+ 0x5C00 ,
+ 0x5C08 ,
+ 0x5C10 ,
+ 0x5C18 ,
+ 0x5C20 ,
+ 0x5C28 ,
+ 0x5C30 ,
+ 0x5C38
+};
+
+UINT8 WakeMaskBit[GPIO_TABLE_ROW_NUM] = {
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 27,
+ 28,
+ 29,
+ 30,
+ 31,
+ 32,
+ 33,
+ 34,
+ 35,
+ 36,
+ 37,
+ 38,
+ 39,
+ 40,
+ 41,
+ 42,
+ 43,
+ 44,
+ 45,
+ 46,
+ 47,
+ 48,
+ 49,
+ 50,
+ 51,
+ 52,
+ 53,
+ 54,
+ 55,
+ 56,
+ 57,
+ 58,
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 0,
+ 1,
+ 1,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 27,
+ 28,
+ 29,
+ 30,
+ 31,
+ 32,
+ 33,
+ 34,
+ 35,
+ 36,
+ 37,
+ 38,
+ 39,
+ 40,
+ 41,
+ 42,
+ 43,
+ 44,
+ 45,
+ 46,
+ 47,
+ 48,
+ 49,
+ 50,
+ 51,
+ 52,
+ 53,
+ 54,
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 27,
+ 28,
+ 29,
+ 30,
+ 31,
+ 32,
+ 33,
+ 34,
+ 35,
+ 36,
+ 37,
+ 38,
+ 39,
+ 40,
+ 41,
+ 42,
+ 43,
+ 44,
+ 45,
+ 46,
+ 47,
+ 48,
+ 49,
+ 50,
+ 51,
+ 52,
+ 53,
+ 54,
+ 55
+};
+
+
+EFI_STATUS
+GetBoardFabIdsKsc (
+ OUT UINT16 *BoardFabIds
+ );
+
+EFI_STATUS
+GetBoradFabIdsGpio (
+ OUT UINT8 *BoardId,
+ OUT UINT8 *FabId
+ );
+
+EFI_STATUS
+EFIAPI
+BraswellCherryHillBoardDetectionCallback (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mBraswellCherryHillDetectionStartNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gBoardDetectionStartPpiGuid,
+ BraswellCherryHillBoardDetectionCallback
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mBraswellCherryHillDetectedPpi = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gBoardDetectedPpiGuid,
+ NULL
+};
+
+VOID
+ProgramGpiosWithPcd (
+ IN UINT32 Gpio_Mmio_Offset,
+ IN UINT32 Gpio_Pin_Num,
+ IN PLATFORM_GPIO_TABLE_ROW* GpioRowPtr
+ )
+{
+ CHV_GPIO_PAD_INIT GpioConfTable[GPIO_TABLE_ROW_NUM];
+ UINT8 RowIndex;
+ UINT8 Mode_Select = 0;
+ UINT8 Mode = 0;
+ UINT8 GPIO_Config = NA;
+ UINT8 GPIO_STATE = NA;
+ UINT8 Gpio_Light_Mode = NA;
+ UINT8 INT_Type = NA;
+ UINT8 INT_S = NA;
+ UINT8 Term_H_L = NA;
+ UINT8 Open_Drain = NA;
+ UINT8 Current_Source = NA;
+ UINT8 Int_Mask = NA;
+ UINT8 Glitch_Cfg = NA;
+ UINT8 InvertRX_TX = NA;
+ UINT8 WAKE_Mask = NA;
+ UINT8 Wake_Mask_Bit = NA;
+ UINT8 GPE = NA;
+ UINT16 MMIO_Offset = 0;
+ UINT32 Community = 0;
+
+ RowIndex = 0;
+ while (GpioRowPtr->Usage != USAGE_None) {
+#ifdef EFI_DEBUG
+ GpioConfTable[RowIndex].pad_name = GPIOPadNames[RowIndex];
+#endif
+
+ //
+ // Mode select & GPIO_Config
+ //
+ switch (GpioRowPtr->Usage) {
+ case USAGE_GPIO:
+ Mode_Select = GPIO;
+ GPIO_Config = GPIO;
+ break;
+ case USAGE_GPO:
+ Mode_Select = GPIO;
+ GPIO_Config = GPO;
+ break;
+ case USAGE_GPI:
+ Mode_Select = GPIO;
+ GPIO_Config = GPI;
+ break;
+ case USAGE_HIZ:
+ Mode_Select = GPIO;
+ GPIO_Config = HI_Z;
+ break;
+ case USAGE_Native:
+ Mode_Select = Native;
+ GPIO_Config = NA;
+ break;
+ default:
+ ASSERT(FALSE);
+ break;
+ }
+ //
+ // Function Number
+ //
+ Mode = GpioRowPtr->FuncNum;
+ //
+ // GPIO state
+ //
+ switch (GpioRowPtr->InitLevel) {
+ case GPIO_ATTRIBUTE_LOW:
+ GPIO_STATE = LOW;
+ break;
+ case GPIO_ATTRIBUTE_HIGH:
+ GPIO_STATE = HIGH;
+ break;
+ case NA:
+ GPIO_STATE = NA;
+ break;
+ default:
+ ASSERT(FALSE);
+ break;
+ }
+ //
+ // Gpio_Light_Mode
+ //
+ switch (GpioRowPtr->LightModeBar) {
+ case GPIO_ATTRIBUTE_HIGH:
+ Gpio_Light_Mode = HIGH;
+ break;
+ case GPIO_ATTRIBUTE_LOW:
+ Gpio_Light_Mode = LOW;
+ break;
+ case NA:
+ Gpio_Light_Mode = NA;
+ break;
+ default:
+ ASSERT(FALSE);
+ break;
+ }
+ //
+ // INT_Type
+ //
+ switch (GpioRowPtr->TrigType) {
+ case TRIGGER_Edge_High:
+ INT_Type = Trig_Edge_High;
+ break;
+ case TRIGGER_Edge_Low:
+ INT_Type = Trig_Edge_Low;
+ break;
+ case TRIGGER_Edge_Both:
+ INT_Type = Trig_Edge_Both;
+ break;
+ case TRIGGER_Level_High:
+ INT_Type = Trig_Level;
+ break;
+ case TRIGGER_Level_Low:
+ INT_Type = Trig_Level;
+ break;
+ case TRIGGER_None:
+ INT_Type = NA;
+ default:
+ ;
+ break;
+ }
+
+ //
+ // INT_S
+ //
+ INT_S = GpioRowPtr->IntLineNum;
+
+ //
+ // Term_H_L
+ //
+ if (GpioRowPtr->PullDirection == DIRECTION_Pull_Up) {
+ if (GpioRowPtr->PullStrength == STRENGTH_20K)
+ Term_H_L = P_20K_H;
+ else if (GpioRowPtr->PullStrength == STRENGTH_5K)
+ Term_H_L = P_5K_H;
+ else if (GpioRowPtr->PullStrength == STRENGTH_1K)
+ Term_H_L = P_1K_H;
+ else
+ Term_H_L = P_NONE;
+ } else if (GpioRowPtr->PullDirection == DIRECTION_Pull_Down) {
+ if (GpioRowPtr->PullStrength == STRENGTH_20K)
+ Term_H_L = P_20K_L;
+ else if (GpioRowPtr->PullStrength == STRENGTH_5K)
+ Term_H_L = P_5K_L;
+ else if (GpioRowPtr->PullStrength == STRENGTH_1K)
+ Term_H_L = P_1K_L;
+ else
+ Term_H_L = P_NONE;
+ } else {
+ Term_H_L = NA;
+ }
+
+ //
+ // Open_Drain
+ //
+ if (GpioRowPtr->DriveType == DRIVE_Open_Drain) {
+ Open_Drain = _ENABLE;
+ } else {
+ Open_Drain = NA;
+ }
+
+ //
+ // Int_Mask
+ //
+ if (GpioRowPtr->IntLineNum != NA) {
+ Int_Mask = NonMaskable;
+ } else {
+ Int_Mask = NA;
+ }
+
+ //
+ // Glitch_Cfg
+ //
+ switch (GpioRowPtr->GlitchFilterConfig) {
+ case GLITCH_DISABLE:
+ Glitch_Cfg = glitch_Disable;
+ break;
+ case GLITCH_EN_EdgeDetect:
+ Glitch_Cfg = En_EdgeDetect;
+ break;
+ case GLITCH_EN_RX_Data:
+ Glitch_Cfg = En_RX_Data;
+ break;
+ case GLITCH_EN_Edge_RX_Data:
+ Glitch_Cfg = En_Edge_RX_Data;
+ break;
+ default:
+ Glitch_Cfg = NA;
+ break;
+ }
+
+ //
+ // InvertRX_TX
+ //
+ switch (GpioRowPtr->InvertRxTx) {
+ case GPIO_No_Inversion:
+ InvertRX_TX = No_Inversion;
+ break;
+ case GPIO_Inv_RX_Enable:
+ InvertRX_TX = Inv_RX_Enable;
+ break;
+ case GPIO_Inv_TX_Enable:
+ InvertRX_TX = Inv_TX_Enable;
+ break;
+ case GPIO_Inv_RX_TX_Enable:
+ InvertRX_TX = Inv_RX_TX_Enable;
+ break;
+ case GPIO_Inv_RX_Data:
+ InvertRX_TX = Inv_RX_Data;
+ break;
+ case GPIO_Inv_TX_Data:
+ InvertRX_TX = Inv_TX_Data;
+ break;
+ default:
+ Glitch_Cfg = NA;
+ break;
+ }
+
+ //
+ // Community
+ //
+ if (RowIndex < GPIO_TABLE_NORTH_ROW_NUM) {
+ Community = NORTH;
+ } else if (RowIndex < ( GPIO_TABLE_NORTH_ROW_NUM + GPIO_TABLE_EAST_ROW_NUM )){
+ Community = EAST;
+ } else if (RowIndex < ( GPIO_TABLE_NORTH_ROW_NUM + GPIO_TABLE_EAST_ROW_NUM + GPIO_TABLE_SOUTHEAST_ROW_NUM)){
+ Community = SOUTHEAST;
+ } else if (RowIndex < GPIO_TABLE_ROW_NUM ){
+ Community = SOUTHWEST;
+ }
+
+ //
+ // Wake_Mask_Bit
+ //
+ Wake_Mask_Bit = WakeMaskBit[RowIndex];
+
+ //
+ // GPE
+ //
+ if ( GpioRowPtr->IntType == INT_SCI ) {
+ GPE = SCI;
+ } else if ( GpioRowPtr->IntType == INT_SMI ){
+ GPE = SMI;
+ } else {
+ GPE = NA;
+ }
+
+ //
+ // MMIO_Offset
+ //
+ MMIO_Offset = GPIOMmioOffset[RowIndex];
+
+ GpioConfTable[RowIndex].padConfg0.padCnf0 = CHV_GPIO_PAD_CONFG0(Mode_Select, Mode, GPIO_Config, GPIO_STATE, Gpio_Light_Mode, INT_S, Term_H_L, Glitch_Cfg);
+ GpioConfTable[RowIndex].padConfg0_changes.padCnf0= CHV_GPIO_PAD_CONFG0_CHANGE(GPIO_Config, GPIO_STATE, Gpio_Light_Mode, INT_S, Term_H_L, Glitch_Cfg);
+ GpioConfTable[RowIndex].padConfg1.padCnf1 = CHV_GPIO_PAD_CONFG1(INT_Type, Open_Drain, Current_Source, InvertRX_TX);
+ GpioConfTable[RowIndex].padConfg1_changes.padCnf1 = CHV_GPIO_PAD_CONFG1_CHANGE(INT_Type, Open_Drain, Current_Source, InvertRX_TX);
+ GpioConfTable[RowIndex].PAD_MISC.micsData = CHV_GPIO_PAD_MISC(Int_Mask, WAKE_Mask,Wake_Mask_Bit, GPE);
+ GpioConfTable[RowIndex].Community = Community;
+ GpioConfTable[RowIndex].MMIO_ADDRESS = CHV_GPIO_PAD_MMIO(MMIO_Offset, Community);
+
+ GpioRowPtr++;
+ RowIndex++;
+ if (RowIndex >= Gpio_Pin_Num)
+ break;
+ }
+
+ ASSERT(RowIndex == Gpio_Pin_Num);
+ InternalGpioPADConfig (Gpio_Mmio_Offset, Gpio_Pin_Num, GpioConfTable);
+}
+
+EFI_STATUS
+EFIAPI
+BraswellCherryHillBoardDetectionCallback (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_PLATFORM_INFO_HOB PlatformInfoHob;
+ UINTN DataSize;
+ UINT16 BoardFabIds;
+ UINT8 BoardId;
+ UINT8 FabId;
+ EFI_STATUS Status;
+ VOID *Instance;
+ PLATFORM_GPIO_TABLE_ROW* GpioRowPtr;
+
+ Status = PeiServicesLocatePpi (
+ &gBoardDetectedPpiGuid,
+ 0,
+ NULL,
+ &Instance
+ );
+ if (!EFI_ERROR(Status)) {
+ return EFI_SUCCESS;
+ }
+
+ DEBUG ((EFI_D_INFO, "BraswellCherryHillBoardDetectionCallback\n"));
+
+ ZeroMem (&PlatformInfoHob, sizeof (PlatformInfoHob));
+
+ Status = GetBoardFabIdsKsc (&BoardFabIds);
+ if (Status != EFI_SUCCESS) {
+ GetBoradFabIdsGpio (&BoardId, &FabId);
+ if (BoardId == 1) {
+ PlatformInfoHob.BoardId = BOARD_ID_BSW_CH;
+ PlatformInfoHob.BoardSvidConfig = BSW_SVID_CONFIG0;
+ if (SocStepping() >= SocC0) {
+ PlatformInfoHob.BoardSvidConfig = BSW_SVID_CONFIG1;
+ }
+ DEBUG ((EFI_D_INFO, "I'm Braswell Cherry Hill \n\n"));
+ DEBUG ((EFI_D_INFO, "SoC Stepping = 0x%x \n", ((UINT32)SocStepping())));
+ PlatformInfoHob.MemCfgID = 0;
+ DEBUG ((EFI_D_INFO, "PlatformInfoHob->MemCfgID= 0x%x\n", PlatformInfoHob.MemCfgID));
+ PlatformInfoHob.FABID = FabId;
+ DEBUG ((EFI_D_INFO, "PlatformInfoHob->FABID = 0x%x\n", FabId ));
+ PlatformInfoHob.PlatformFlavor = FlavorMobile;
+ DEBUG ((EFI_D_INFO, "PlatformInfoHob->PlatformFlavor = 0x%x\n", PlatformInfoHob.PlatformFlavor ));
+ DEBUG ((EFI_D_INFO, "PlatformInfoHob->BoardSvidConfig = 0x%x\n", PlatformInfoHob.BoardSvidConfig ));
+ DEBUG ((EFI_D_INFO, "PlatformInfoHob->BoardId = 0x%x\n", PlatformInfoHob.BoardId ));
+
+ PlatformInfoHob.ECSupport = FALSE;
+ PlatformInfoHob.FanSupport = FALSE;
+ PlatformInfoHob.BatterySupport = FALSE;
+
+ DataSize = sizeof (EFI_PLATFORM_INFO_HOB);
+ PcdSetPtr (PcdPlatformInfo, &DataSize, &PlatformInfoHob);
+
+ DataSize = sizeof (EFI_GUID);
+ PcdSetPtr (PcdBmpImageGuid, &DataSize, &gHdmiDpVbtGuid);
+
+ PcdSet8 (PcdNfcConnection, 0);
+
+ PcdSet8 (PcdOemMemeoryDimmType,DimmInstalled);
+
+ //
+ // Config SC/NC/SUS GPIO Pins
+ //
+ GpioRowPtr = (PLATFORM_GPIO_TABLE_ROW*)PcdGetPtr (PcdPlatformGpioTable);
+ if (GpioRowPtr->Usage == USAGE_None) {
+ // Program all the gpios from the default GPIO table
+ InternalGpioPADConfig(0, sizeof(mBswCherryHillGpioInitData)/sizeof(mBswCherryHillGpioInitData[0]), mBswCherryHillGpioInitData);
+ } else {
+ //
+ // Use the GPIO table from pcd to initialize North/East/SouthWest/SouthEast GPIO Pins
+ //
+ DEBUG ((EFI_D_INFO, "Use GPIO table from pcd to config GPIO pins\n"));
+ ProgramGpiosWithPcd (0, GPIO_TABLE_ROW_NUM, &GpioRowPtr[0]);
+ }
+
+ Status = PeiServicesInstallPpi (&mBraswellCherryHillDetectedPpi);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function performs Board initialization in Pre-Memory.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES No enough resoruces (such as out of memory).
+**/
+EFI_STATUS
+EFIAPI
+BraswellCherryHillInitConstructor (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+
+ Status = PeiServicesNotifyPpi (&mBraswellCherryHillDetectionStartNotifyList);
+
+ return Status;
+}
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInit.inf b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInit.inf new file mode 100644 index 0000000000..0d59894539 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInit.inf @@ -0,0 +1,65 @@ +## @file
+# Board detected module for Intel(R) Atom(TM) x5 Processor Series.
+#
+# It will detect the board ID.
+#
+# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BraswellCherryHillInit
+ FILE_GUID = CC235019-C750-41E4-AF71-A172C07ACE47
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ CONSTRUCTOR = BraswellCherryHillInitConstructor
+
+[Sources]
+ BoardInit.c
+
+[LibraryClasses]
+ PeiServicesLib
+ PcdLib
+ PchPlatformLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ChvRefCodePkg/ChvRefCodePkg.dec
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
+
+[Pcd]
+ ## SOMETIMES_PRODUCES
+ gEfiEdkIIPlatformTokenSpaceGuid.PcdPlatformInfo
+
+ ## SOMETIMES_PRODUCES
+ gEfiCHVTokenSpaceGuid.PcdBmpImageGuid
+
+ ## SOMETIMES_PRODUCES
+ gEfiEdkIIPlatformTokenSpaceGuid.PcdNfcConnection
+
+ ## SOMETIMES_PRODUCES
+ gEfiEdkIIPlatformTokenSpaceGuid.PcdOemMemeoryDimmType
+
+ ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdPlatformGpioTable
+
+[Guids]
+ ## SOMETIMES_CONSUMES
+ gHdmiDpVbtGuid
+
+[Ppis]
+ # NOTIFY
+ gBoardDetectionStartPpiGuid
+
+ ## SOMETIMES_PRODUCES
+ ## SOMETIMES_CONSUMES
+ gBoardDetectedPpiGuid
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInitLate.c b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInitLate.c new file mode 100644 index 0000000000..7321160b78 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInitLate.c @@ -0,0 +1,69 @@ +/** @file
+ Board Init driver.
+
+ Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Guid/PlatformInfo.h>
+#include <Ppi/BoardDetection.h>
+#include <Ppi/ChvPlatformPolicyPpi.h>
+#include <Protocol/PlatformGopPolicy.h>
+#include "BoardGpios.h"
+
+VOID
+SAI_SettingOfGpioFamilies (
+ GPIO_SAI_INIT* SAI_Conf_Data,
+ UINT32 familySize
+ );
+
+VOID
+BraswellCherryHillGpioInit (
+ VOID
+ )
+{
+ DEBUG ((EFI_D_ERROR, "Programming BSW CR Board Gpio Tables which are not done properly by FSP...\n"));
+
+ // GPIO lock if really want
+ SAI_SettingOfGpioFamilies(mBSW_CH_GPIO_SAI_Init_East, sizeof(mBSW_CH_GPIO_SAI_Init_East)/sizeof(mBSW_CH_GPIO_SAI_Init_East[0]));
+ SAI_SettingOfGpioFamilies(mBSW_CH_GPIO_SAI_Init_North, sizeof(mBSW_CH_GPIO_SAI_Init_North)/sizeof(mBSW_CH_GPIO_SAI_Init_North[0]));
+ SAI_SettingOfGpioFamilies(mBSW_CH_GPIO_SAI_Init_SouthEast, sizeof(mBSW_CH_GPIO_SAI_Init_SouthEast)/sizeof(mBSW_CH_GPIO_SAI_Init_SouthEast[0]));
+ SAI_SettingOfGpioFamilies(mBSW_CH_GPIO_SAI_Init_SouthWest, sizeof(mBSW_CH_GPIO_SAI_Init_SouthWest)/sizeof(mBSW_CH_GPIO_SAI_Init_SouthWest[0]));
+}
+
+/**
+ This function performs Board initialization in Pre-Memory.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES No enough resoruces (such as out of memory).
+**/
+EFI_STATUS
+EFIAPI
+BraswellCherryHillInitLateConstructor (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_PLATFORM_INFO_HOB *PlatformInfoHob;
+
+ PlatformInfoHob = PcdGetPtr (PcdPlatformInfo);
+ if (PlatformInfoHob->BoardId == BOARD_ID_BSW_CH) {
+ PcdSet64 (PcdGpioInitFunc, (UINT64)(UINTN)BraswellCherryHillGpioInit);
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInitLate.inf b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInitLate.inf new file mode 100644 index 0000000000..a95cc4c34c --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInitLate.inf @@ -0,0 +1,52 @@ +## @file
+# GPIO porting module for Intel(R) Atom(TM) x5 Processor Series.
+#
+# This module will do the basic PCH GPIO porting.
+#
+# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BraswellCherryHillInitLate
+ FILE_GUID = CC235019-C750-41E4-AF71-A172C07ACE47
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ CONSTRUCTOR = BraswellCherryHillInitLateConstructor
+
+[Sources]
+ BoardInitLate.c
+
+[LibraryClasses]
+ PeiServicesLib
+ PcdLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ChvRefCodePkg/ChvRefCodePkg.dec
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
+
+[Pcd]
+ ## SOMETIMES_CONSUMES
+ gEfiEdkIIPlatformTokenSpaceGuid.PcdPlatformInfo
+
+ ## SOMETIMES_PRODUCES
+ gEfiEdkIIPlatformTokenSpaceGuid.PcdGpioInitFunc
+
+[Ppis]
+ ## NOTIFY
+ gBoardDetectionStartPpiGuid
+
+ ## SOMETIMES_PRODUCES
+ ## SOMETIMES_CONSUMES
+ gBoardDetectedPpiGuid
+
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BraswellCherryHillInitExtra.uni b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BraswellCherryHillInitExtra.uni new file mode 100644 index 0000000000..245b34a604 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BraswellCherryHillInitExtra.uni @@ -0,0 +1,18 @@ +// /** @file
+// BraswellCherryHillInit Localized Strings and Content
+//
+// Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php.
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME #language en-US "Intel® Atom™ x5 Processor Series Init module"
+
+
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BraswellCherryHillInitLateExtra.uni b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BraswellCherryHillInitLateExtra.uni new file mode 100644 index 0000000000..0adafe50d0 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BraswellCherryHillInitLateExtra.uni @@ -0,0 +1,18 @@ +// /** @file
+// /BraswellCherryHillInitLate Localized Strings and Content
+//
+// Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php.
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME #language en-US "Intel® Atom™ x5 Processor Series Init Late module"
+
+
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Vbt/IntelGopVbtHdmiDp.inf b/BraswellPlatformPkg/Board/BraswellCherryHill/Vbt/IntelGopVbtHdmiDp.inf new file mode 100644 index 0000000000..20737d0518 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Vbt/IntelGopVbtHdmiDp.inf @@ -0,0 +1,27 @@ +## @file
+# Graphics Output Protocol used Video BIOS Table HDMI DP Driver
+#
+# Provides Graphics Output Protocol used Video BIOS Table HDMI DP driver binary file.
+#
+# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IntelGopVbtHdmiDp
+ FILE_GUID = CFF9CF38-AE87-440d-80A9-004701FE8D01
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Binaries]
+ BIN|Vbt_HDMIPB_DPHDMIPC_DPHDMIPD.bin
+
diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Vbt/Vbt_HDMIPB_DPHDMIPC_DPHDMIPD.bin b/BraswellPlatformPkg/Board/BraswellCherryHill/Vbt/Vbt_HDMIPB_DPHDMIPC_DPHDMIPD.bin Binary files differnew file mode 100644 index 0000000000..55ad55f406 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Vbt/Vbt_HDMIPB_DPHDMIPC_DPHDMIPD.bin |