BraswellPlatformPkg: Add MultiPlatformLib

Contributed-under: TianoCore Contribution Agreement 1.0

Signed-off-by: Guo Mang <mang.guo@intel.com>

6 files changed, 571 insertions, 0 deletions

diff --git a/BraswellPlatformPkg/Library/MultiPlatformLib/BoardIdentify.c b/BraswellPlatformPkg/Library/MultiPlatformLib/BoardIdentify.c
new file mode 100644
index 0000000000..2606810f68
--- /dev/null
+++ b/BraswellPlatformPkg/Library/MultiPlatformLib/BoardIdentify.c
@@ -0,0 +1,140 @@
+/** @file

+  Boards identification for multiplatform.

+

+  Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>

+

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php.

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+**/

+

+#include <MultiPlatformLib.h>

+#include <PeiKscLib.h>

+#include <Library/TimerLib.h>

+#include <Library/GpioLib.h>

+

+/**

+  This function Issues EC command (0x0D) to EC to get board ID and FAB ID details and returns to the

+  calling function. Procedure to get Board ID & FAB ID is common to both Mobile and Desktop platforms.

+  Bit position details

+  when EC Command 0x0D is issue to EC

+  Read value 1st byte = EC LSB [ 7:0]

+  Read value 2nd byte = EC MSB [15:8]

+

+  Bits [3:0] - Board ID (Range from 0x00 to 0x0F)

+  Bit  6     - 0 = Mobile/ULT/Embedded;

+             - 1 = Desktop

+               (Note: Not required consider this bit when Bit 7 is set)

+  Bit 7      - 0 = Mainstream

+             - 1 =  Entry Notebook & Desktop (Essential Notebook)

+  Bit 8      - Generation (Tick / Tock)

+               (Note: Not required consider this bit when Bit 7 is set)

+  Bits 11:9  - FAB ID (Range from 0x00 to 0x07)

+  Bits 15:12 - Reserved

+

+  @param[in]   BoardFabIds           Board ID & FabId ID as determined through the EC.

+

+  @retval    EFI_SUCCESS             The function completed successfully.

+                                     BoardFabIds word contains

+                                     LSB - FAB ID   (0x00 - 0x07)

+                                     MSB - Board ID (1, 2, 4, 8)

+  @retval    EFI_DEVICE_ERROR        KSC fails to respond.

+

+**/

+EFI_STATUS

+GetBoardFabIdsKsc (

+  OUT UINT16                    *BoardFabIds

+  )

+{

+  EFI_STATUS     Status = EFI_SUCCESS;

+  UINT8          EcMSB;

+  UINT8          EcLSB;

+

+  //

+  // Return Unknown Board ID & Fab ID in case of error.

+  //

+  *BoardFabIds = 0xFFFF;

+

+  //

+  // Send Board ID command to EC

+  //

+  Status = SendKscCommand (0x0D);

+  if (!EFI_ERROR(Status)) {

+    //

+    // Read 1st Byte from EC (MSB)

+    //

+    Status = ReceiveKscData (&EcLSB);

+    if (!EFI_ERROR(Status)) {

+      //

+      // Read 2nd Byte from EC (LSB)

+      //

+      Status = ReceiveKscData (&EcMSB);

+      if (!EFI_ERROR(Status)) {

+        EcMSB = EcMSB & 0x0E;

+        EcMSB = EcMSB >> 1;

+        EcLSB = EcLSB & 0x7; // Need new EC to support 4 bits for BSW CR board ID, or it would be wrong if and w/ 0xF

+        *BoardFabIds = (UINT16) ((EcLSB << 8) | EcMSB );  //  MSB[11:8] - Board ID;  LSB[3:0] - FAB ID

+        Status = EFI_SUCCESS;

+      }

+    }

+  }

+

+  return Status;

+}

+

+EFI_STATUS

+GetBoradFabIdsGpio (

+  OUT UINT8 *BoardId,

+  OUT UINT8 *FabId

+  )

+{

+  UINT32                          mmio_conf0;

+

+  //

+  // Assuming Braswell Cherry Hill/Cherry Island - Get Board ID/Fab ID from GPIO

+  // Set Pad Config to GPIO for BoardId read

+  // mmio_conf0 = (IO_BASE_ADDRESS + Community + Offset + 0x0);

+  // PANEL1_BKLTCTL - BoardId Bit 0, North Community is 0x8000

+  //

+  mmio_conf0 = (IO_BASE_ADDRESS + 0x8000 + 0x5428) + CHV_GPIO_PAD_CONF0_OFFSET;

+  MmioWrite32(mmio_conf0 ,0x00008200); //Set GPIOCfg [10:8] - GPI(0x02), GPIOEn -BIT15

+  //PANEL1_BKLTEN - BoardId Bit 1

+  mmio_conf0 = (IO_BASE_ADDRESS + 0x8000 + 0x5400) + CHV_GPIO_PAD_CONF0_OFFSET;

+  MmioWrite32(mmio_conf0 ,0x00008200); //Set GPIOCfg [10:8] - GPI(0x02), GPIOEn -BIT15

+  //PANEL1_VDDEN - BoardId Bit 2

+  mmio_conf0 = (IO_BASE_ADDRESS + 0x8000 + 0x5460) + CHV_GPIO_PAD_CONF0_OFFSET;

+  MmioWrite32(mmio_conf0 ,0x00008200); //Set GPIOCfg [10:8] - GPI(0x02), GPIOEn -BIT15

+  //Get BoardId

+  *BoardId = (UINT8)((MmioRead16(IO_BASE_ADDRESS + 0x8000 + 0x5428) & BIT0) | \

+                    ((MmioRead16(IO_BASE_ADDRESS + 0x8000 + 0x5400) & BIT0) << 1) | \

+                    ((MmioRead16(IO_BASE_ADDRESS + 0x8000 + 0x5460) & BIT0) << 2));

+

+  //

+  // Set Pad Config to GPIO for FabId read

+  // mmio_conf0 = (IO_BASE_ADDRESS + Community + Offset + 0x0);

+  // MF_ISH_GPIO_0 - FAB ID bit 0, East Community is 0x10000

+  //

+  mmio_conf0 = (IO_BASE_ADDRESS + 0x10000 + 0x4830) + CHV_GPIO_PAD_CONF0_OFFSET;

+  MmioWrite32(mmio_conf0 ,0x00008200); //Set GPIOCfg [10:8] - GPI(0x02), GPIOEn -BIT15

+  // MF_ISH_GPIO_1 - FAB ID bit 1

+  mmio_conf0 = (IO_BASE_ADDRESS + 0x10000 + 0x4818) + CHV_GPIO_PAD_CONF0_OFFSET;

+  MmioWrite32(mmio_conf0 ,0x00008200); //Set GPIOCfg [10:8] - GPI(0x02), GPIOEn -BIT15

+  // MF_ISH_GPIO_2 - FAB ID bit 2

+  mmio_conf0 = (IO_BASE_ADDRESS + 0x10000 + 0x4848) + CHV_GPIO_PAD_CONF0_OFFSET;

+  MmioWrite32(mmio_conf0 ,0x00008200); //Set GPIOCfg [10:8] - GPI(0x02), GPIOEn -BIT15

+  // MF_ISH_GPIO_3 - FAB ID bit 3

+  mmio_conf0 = (IO_BASE_ADDRESS + 0x10000 + 0x4800) + CHV_GPIO_PAD_CONF0_OFFSET;

+  MmioWrite32(mmio_conf0 ,0x00008200); //Set GPIOCfg [10:8] - GPI(0x02), GPIOEn -BIT15

+  //Get FabId

+  *FabId = (UINT8)((MmioRead16(IO_BASE_ADDRESS + 0x10000 + 0x4830) & BIT0) | \

+                  ((MmioRead16(IO_BASE_ADDRESS + 0x10000 + 0x4818) & BIT0) << 1) | \

+                  ((MmioRead16(IO_BASE_ADDRESS + 0x10000 + 0x4848) & BIT0) << 2) | \

+                  ((MmioRead16(IO_BASE_ADDRESS + 0x10000 + 0x4800) & BIT0) << 3));

+

+  return EFI_SUCCESS;

+}

diff --git a/BraswellPlatformPkg/Library/MultiPlatformLib/BswBoardGpios/BoardGpios.c b/BraswellPlatformPkg/Library/MultiPlatformLib/BswBoardGpios/BoardGpios.c
new file mode 100644
index 0000000000..8d7544e508
--- /dev/null
+++ b/BraswellPlatformPkg/Library/MultiPlatformLib/BswBoardGpios/BoardGpios.c
@@ -0,0 +1,105 @@
+/** @file

+  Gpio setting programming for platform.

+

+  Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>

+

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php.

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+**/

+

+#include <BoardGpios.h>

+

+typedef

+VOID

+(EFIAPI *GPIO_INIT) (

+  VOID

+  );

+

+

+/**

+  Set GPIO PAD SAI registers for N/E/SW/SE GPIO communities

+

+  @param  SAI_Conf_Data         GPIO_SAI_INIT data array for each GPIO communities.

+

+**/

+VOID

+SAI_SettingOfGpioFamilies (

+  GPIO_SAI_INIT*    SAI_Conf_Data,

+  UINT32 familySize

+  )

+{

+

+  UINT32 count=0;

+  DEBUG ((EFI_D_ERROR, "++SAI Setting of GPIO families%x\n ",familySize));

+

+  //

+  // community SAI programming

+  //

+  for (count=0;count < familySize;count++) {

+    MmioWrite32 (SAI_Conf_Data[count].Offset, SAI_Conf_Data[count].val_.secSAI);

+  }

+

+   DEBUG ((EFI_D_ERROR, "--SAI Setting of GPIO families %x\n ",familySize));

+}

+

+/**

+  Returns the Correct GPIO table for Mobile/Desktop respectively.

+  Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get correctly.

+

+  @param[in] PeiServices            General purpose services available to every PEIM.

+  @param[in] PlatformInfoHob        PlatformInfoHob pointer with PlatformFlavor specified.

+

+  @retval  EFI_SUCCESS               The function completed successfully.

+  @retval  EFI_DEVICE_ERROR          KSC fails to respond.

+

+**/

+EFI_STATUS

+MultiPlatformGpioProgram (

+  IN CONST EFI_PEI_SERVICES     **PeiServices,

+  IN EFI_PLATFORM_INFO_HOB      *PlatformInfoHob

+  )

+{

+  CHV_CONF_PAD0                     lpadvar;

+  GPIO_INIT                         GpioInit;

+

+  DEBUG ((EFI_D_ERROR, "MultiPlatformGpioProgram()...\n"));

+

+  //

+  // Clearing Interrupt unmask registers

+  //

+  MmioWrite32 (IO_BASE_ADDRESS + GPIO_MMIO_OFFSET_N + GPIO_INTERRUPT_MASK, 0);

+  MmioWrite32 (IO_BASE_ADDRESS + GPIO_MMIO_OFFSET_E + GPIO_INTERRUPT_MASK, 0);

+  MmioWrite32 (IO_BASE_ADDRESS + GPIO_MMIO_OFFSET_SW + GPIO_INTERRUPT_MASK, 0);

+  MmioWrite32 (IO_BASE_ADDRESS + GPIO_MMIO_OFFSET_SE + GPIO_INTERRUPT_MASK, 0);

+  MmioWrite32 (IO_BASE_ADDRESS + GPIO_MMIO_OFFSET_VIRT + GPIO_INTERRUPT_MASK, 0);

+

+  GpioInit = (GPIO_INIT)(UINTN)PcdGet64 (PcdGpioInitFunc);

+  if (GpioInit != NULL) {

+    GpioInit ();

+  }

+

+  //

+  // TODO: W/A [HSD # 4963135] HPD GPIOs drive 0 in mode 1.

+  //

+  lpadvar.padCnf0 = 0;

+  lpadvar.r.Pmode = 0x1;

+  lpadvar.r.RXTXEnCfg = 0x3;

+

+  MmioOr32 (IO_BASE_ADDRESS+0x8000 + 0x5408,lpadvar.padCnf0 );  // HV_DDI0_HPD

+  MmioOr32 (IO_BASE_ADDRESS+0x8000 + 0x5420,lpadvar.padCnf0 );  // HV_DDI1_HPD

+  MmioOr32 (IO_BASE_ADDRESS+0x8000 + 0x5440,lpadvar.padCnf0 );  // HV_DDI2_HPD

+

+  //

+  // Set SDCard RCOMP Trigger Delay to 5ms

+  //

+  MmioWrite32 (IO_BASE_ADDRESS + R_PCH_CFIO_SOUTHEAST + 0x1080, 0x1E848);

+

+  return EFI_SUCCESS;

+}

+

diff --git a/BraswellPlatformPkg/Library/MultiPlatformLib/BswBoardGpios/BoardGpios.h b/BraswellPlatformPkg/Library/MultiPlatformLib/BswBoardGpios/BoardGpios.h
new file mode 100644
index 0000000000..eb2431dad8
--- /dev/null
+++ b/BraswellPlatformPkg/Library/MultiPlatformLib/BswBoardGpios/BoardGpios.h
@@ -0,0 +1,68 @@
+/** @file

+  GPIO setting for Platform.

+  This file includes package header files, library classes.

+

+  Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>

+

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php.

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+**/

+

+#ifndef _BOARDGPIOS_H_

+#define _BOARDGPIOS_H_

+

+#include <PiPei.h>

+#include "PchAccess.h"

+#include "PlatformBaseAddresses.h"

+#include <../MultiPlatformLib.h>

+#include <Library/IoLib.h>

+#include <Library/HobLib.h>

+#include <Library/Timerlib.h>

+#include <Library/PchPlatformLib.h>

+#include <Library/GpioLib.h>

+#include <Guid/PlatformInfo.h>

+#include <Ppi/Smbus2.h>

+

+#define GPIO_DFX1_PAD0            0x4418

+#define GPIO_DFX3_PAD0            0x4408

+#define GPIO_MF_ISH_I2C1_SCL_PAD0 0x4810

+#define GPIO_MF_ISH_I2C1_SDA_PAD0 0x4858

+#define GPIO_PCIE_CLKREQ0B_PAD0   0x5C00

+#define GPIO_SEC_GPIO_SUS8_PAD0   0x4840

+#define GPIO_SEC_GPIO_SUS8_PAD1   0x4844

+#define GPIO_SEC_GPIO_SUS9_PAD0   0x4860

+#define GPIO_SEC_GPIO_SUS9_PAD1   0x4864

+#define GPIO_SEC_GPIO_SUS10_PAD0  0x4808

+#define GPIO_SEC_GPIO_SUS10_PAD1  0x480C

+#define GPIO_I2C_NFC_SCL_PAD0     0x5038

+#define GPIO_I2C_NFC_SCL_PAD1     0x503C

+#define GPIO_I2C_NFC_SDA_PAD0     0x5020

+#define GPIO_I2C_NFC_SDA_PAD1     0x5024

+#define GPIO_MF_ISH_GPIO_7_PAD0   0x4808

+

+#define USB3_CAMERA                0

+#define MIPI_CAMERA                1

+#define DISABLE                    0

+#define NO_PULL_UP                 0

+#define SECURE_NFC_ENABLE          1

+

+#define GPIO_SOC_RUNTIME_SCI_N  0x4850

+

+/// *****************************************************************************************************************************************

+/// *****************************************************************************************************************************************

+/// *****************************************************************************************************************************************

+/// ***************************************************     CHERRYVIEW GPIO CONFIGURATION   *************************************************

+/// *****************************************************************************************************************************************

+/// *****************************************************************************************************************************************

+/// *****************************************************************************************************************************************

+

+#define ENABLE  1

+#define DISABLE 0

+

+#endif

diff --git a/BraswellPlatformPkg/Library/MultiPlatformLib/MultiPlatformLib.c b/BraswellPlatformPkg/Library/MultiPlatformLib/MultiPlatformLib.c
new file mode 100644
index 0000000000..d548a968fe
--- /dev/null
+++ b/BraswellPlatformPkg/Library/MultiPlatformLib/MultiPlatformLib.c
@@ -0,0 +1,115 @@
+/** @file

+  Multiplatform initialization.

+

+  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>

+

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php.

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+**/

+

+#include <MultiPlatformLib.h>

+

+

+/**

+  MultiPlatform initialization

+

+  @param[in]  PeiServices      General purpose services available to every PEIM.

+  @param[in]  PlatformInfoHob  The Hob of platform information

+

+  @retval  EFI_SUCCESS         Platform initialization completed successfully.

+  @retval  Others              All other error conditions encountered result in an ASSERT.

+

+**/

+EFI_STATUS

+MultiPlatformInfoInit (

+  IN CONST EFI_PEI_SERVICES             **PeiServices,

+  IN OUT EFI_PLATFORM_INFO_HOB          *PlatformInfoHob

+  )

+{

+  UINT32          PcieLength;

+  EFI_STATUS      Status;

+

+  //

+  // Calculate PCIe length based on user defined range

+  //

+  switch (PLATFORM_PCIE_BASE_SIZE) {

+    case 64:

+      //64MB

+      PcieLength = 0x04000000;

+      break;

+    case 128:

+      //128MB

+      PcieLength = 0x08000000;

+      break;

+    default:

+      // 256MB

+      PcieLength = 0x10000000;

+      break;

+  }

+

+  //

+  // Don't support BASE above 4GB currently

+  //

+  PlatformInfoHob->PciData.PciExpressSize     = PcieLength;

+  PlatformInfoHob->PciData.PciExpressBase     = PLATFORM_PCIE_BASE;

+

+  PlatformInfoHob->PciData.PciResourceMem32Base  = (UINT32) (PlatformInfoHob->PciData.PciExpressBase - RES_MEM32_MIN_LEN);

+  PlatformInfoHob->PciData.PciResourceMem32Limit = (UINT32) (PlatformInfoHob->PciData.PciExpressBase -1);

+

+  PlatformInfoHob->PciData.PciResourceMem64Base   = RES_MEM64_36_BASE;

+  PlatformInfoHob->PciData.PciResourceMem64Limit  = RES_MEM64_36_LIMIT;

+  PlatformInfoHob->CpuData.CpuAddressWidth        = 36;

+

+  PlatformInfoHob->MemData.MemMir0 = PlatformInfoHob->PciData.PciResourceMem64Base;

+  PlatformInfoHob->MemData.MemMir1 = PlatformInfoHob->PciData.PciResourceMem64Limit + 1;

+

+  PlatformInfoHob->PciData.PciResourceMinSecBus  = 1;  //can be changed by SystemConfiguration->PciMinSecondaryBus;

+

+  //

+  // Set MemMaxTolm to the lowest address between PCIe Base and PCI32 Base

+  //

+  if (PlatformInfoHob->PciData.PciExpressBase > PlatformInfoHob->PciData.PciResourceMem32Base ) {

+    PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciResourceMem32Base;

+  } else {

+    PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciExpressBase;

+  }

+  PlatformInfoHob->MemData.MemTolm = PlatformInfoHob->MemData.MemMaxTolm;

+

+  //

+  // Platform PCI MMIO Size in unit of 1MB

+  //

+  PlatformInfoHob->MemData.MmioSize = 0x1000 - (UINT16)(PlatformInfoHob->MemData.MemMaxTolm >> 20);

+

+  //

+  // Update Memory Config HOB size which will be used by SaveMemoryConfig

+  //

+  // bugbug PlatformInfoHob->MemData.MemConfigSize = sizeof(MRC_PARAMS_SAVE_RESTORE);

+

+  //

+  // Enable ICH IOAPIC

+  //

+  PlatformInfoHob->SysData.SysIoApicEnable  = ICH_IOAPIC;

+

+  DEBUG ((EFI_D_ERROR, "PlatformFlavor: %x (%x=tablet,%x=mobile,%x=desktop)\n", PlatformInfoHob->PlatformFlavor,FlavorTablet,FlavorMobile,FlavorDesktop));

+

+  //

+  // Get Platform Info and fill the Hob

+  //

+  PlatformInfoHob->RevisonId = PLATFORM_INFO_HOB_REVISION;

+

+  //

+  // Get GPIO table

+  //

+  //

+  // Program GPIO

+  //

+  Status = MultiPlatformGpioProgram (PeiServices, PlatformInfoHob);

+

+  return EFI_SUCCESS;

+}

diff --git a/BraswellPlatformPkg/Library/MultiPlatformLib/MultiPlatformLib.h b/BraswellPlatformPkg/Library/MultiPlatformLib/MultiPlatformLib.h
new file mode 100644
index 0000000000..abf07049e6
--- /dev/null
+++ b/BraswellPlatformPkg/Library/MultiPlatformLib/MultiPlatformLib.h
@@ -0,0 +1,81 @@
+/** @file

+  Multiplatform initialization header file.

+  This file includes package header files, library classes.

+

+  Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>

+

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php.

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+**/

+

+#ifndef _MULTIPLATFORM_LIB_H_

+#define _MULTIPLATFORM_LIB_H_

+

+//////////////////////////////////////////////////////////////////////

+#define LEN_64M       0x4000000

+//

+// Default PCI32 resource size

+//

+#define RES_MEM32_MIN_LEN   0x38000000

+

+#define RES_IO_BASE   0x0D00

+#define RES_IO_LIMIT  0xFFFF

+#define MRC_DATA_REQUIRED_FROM_OUTSIDE

+//////////////////////////////////////////////////////////////////////

+#include <PiDxe.h>

+#include <Library/BaseLib.h>

+#include <FrameworkPei.h>

+

+#include "PlatformBaseAddresses.h"

+#include "PchAccess.h"

+#include "CpuRegs.h"

+#include "Platform.h"

+

+#include <Ppi/Stall.h>

+#include <Guid/SetupVariable.h>

+#include <Ppi/AtaController.h>

+#include <Ppi/FindFv.h>

+#include <Ppi/BootInRecoveryMode.h>

+#include <Ppi/ReadOnlyVariable2.h>

+#include <Ppi/Capsule.h>

+#include <Library/DebugLib.h>

+#include <Library/BaseMemoryLib.h>

+#include <Library/PcdLib.h>

+#include <Library/IoLib.h>

+#include <Library/HobLib.h>

+#include <Library/BaseLib.h>

+#include <IndustryStandard/Pci22.h>

+#include <Guid/FirmwareFileSystem.h>

+#include <Guid/MemoryTypeInformation.h>

+#include <Ppi/Cache.h>

+#include <Ppi/Reset.h>

+#include <Ppi/EndOfPeiPhase.h>

+#include <Ppi/MemoryDiscovered.h>

+#include <Guid/GlobalVariable.h>

+#include <Ppi/RecoveryModule.h>

+#include <Ppi/DeviceRecoveryModulePei.h>

+#include <Guid/Capsule.h>

+#include <Guid/RecoveryDevice.h>

+#include <Ppi/MasterBootMode.h>

+#include <Guid/PlatformInfo.h>

+#include <Library/I2CLib.h>

+

+EFI_STATUS

+MultiPlatformGpioTableInit (

+  IN CONST EFI_PEI_SERVICES     **PeiServices,

+  IN EFI_PLATFORM_INFO_HOB      *PlatformInfoHob

+  );

+

+EFI_STATUS

+MultiPlatformGpioProgram (

+  IN CONST EFI_PEI_SERVICES     **PeiServices,

+  IN EFI_PLATFORM_INFO_HOB      *PlatformInfoHob

+  );

+

+#endif

diff --git a/BraswellPlatformPkg/Library/MultiPlatformLib/MultiPlatformLib.inf b/BraswellPlatformPkg/Library/MultiPlatformLib/MultiPlatformLib.inf
new file mode 100644
index 0000000000..dffa148d9d
--- /dev/null
+++ b/BraswellPlatformPkg/Library/MultiPlatformLib/MultiPlatformLib.inf
@@ -0,0 +1,62 @@
+## @file

+#  Platform configuration detail infomation.

+#

+#  Getting/setting platform info, such as GPIO, Clkgen, Jumper, OEMID, SSID/SVID.

+#

+#  Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>

+#

+#  This program and the accompanying materials

+#  are licensed and made available under the terms and conditions of the BSD License

+#  which accompanies this distribution.  The full text of the license may be found at

+#  http://opensource.org/licenses/bsd-license.php.

+#

+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+#

+##

+

+[Defines]

+  INF_VERSION                    = 0x00010005

+  BASE_NAME                      = MultiPlatformLib

+  FILE_GUID                      = AB83A52B-B44A-462c-B099-444CC0ED274D

+  MODULE_TYPE                    = PEIM

+  VERSION_STRING                 = 1.0

+  LIBRARY_CLASS                  = MultiPlatformLib

+  PI_SPECIFICATION_VERSION       = 0x0001000A

+

+[Sources]

+  MultiPlatformLib.c

+  MultiPlatformLib.h

+  BoardIdentify.c

+

+#GPIO

+  BswBoardGpios/BoardGpios.c

+  BswBoardGpios/BoardGpios.h

+

+[Guids]

+

+[Packages]

+  MdePkg/MdePkg.dec

+  MdeModulePkg/MdeModulePkg.dec

+  BraswellPlatformPkg/BraswellPlatformPkg.dec

+  IntelFrameworkPkg/IntelFrameworkPkg.dec

+  ChvRefCodePkg/ChvRefCodePkg.dec

+

+

+[LibraryClasses]

+  DebugLib

+  HobLib

+  IoLib

+  PeiKscLib

+  I2CLibPei

+  GpioLib

+

+[Ppis]

+  gEfiPeiReadOnlyVariable2PpiGuid      ## CONSUMES

+  gEfiPeiSmbus2PpiGuid                 ## NOTIFY

+

+[Pcd.common]

+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress     ## CONSUMES

+

+  gEfiEdkIIPlatformTokenSpaceGuid.PcdPlatformInfo

+  gEfiEdkIIPlatformTokenSpaceGuid.PcdGpioInitFunc