diff options
| author | Guo Mang <mang.guo@intel.com> | 2016-06-02 13:50:39 +0800 |
|---|---|---|
| committer | Hao Wu <hao.a.wu@intel.com> | 2016-06-07 09:55:34 +0800 |
| commit | 48f455b9a53e42468ba5069a8e6ca876b1349900 (patch) | |
| tree | 15f7c7eb87c02d59366b245aa5875e6d243dfc8f /ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library | |
| parent | e468aeccbf0401410445639ed516f3b72f8209bb (diff) | |
| download | edk2-platforms-48f455b9a53e42468ba5069a8e6ca876b1349900.tar.xz | |
ChvRefCodePkg: Add SouthCluster include files.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Diffstat (limited to 'ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library')
15 files changed, 4498 insertions, 0 deletions
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/DriverLib.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/DriverLib.h new file mode 100644 index 0000000000..7f68a3b5af --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/DriverLib.h @@ -0,0 +1,302 @@ +/** @file
+ Definitions for the Driver Library
+
+ Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _DRIVER_LIB_H
+#define _DRIVER_LIB_H
+
+//------------------------------------------------------------------------------
+// Specify the header files
+//------------------------------------------------------------------------------
+
+#include <Uefi.h>
+
+#include <IndustryStandard/Pci.h>
+
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiLib.h>
+
+#include <Protocol/DevicePath.h>
+#include <Protocol/LoadedImage.h>
+#include <Protocol/PciIo.h>
+
+//------------------------------------------------------------------------------
+// Data Types
+//------------------------------------------------------------------------------
+
+/**
+ PCI device information
+**/
+#pragma pack(1)
+typedef struct
+{
+ UINT16 VendorID; ///< PCI-SIG <a href="http://www.pcisig.com/membership/vid_search/">vendor identification</a>
+ UINT16 DeviceID; ///< Vendor specific device identification
+ UINT8 Revision; ///< Hardware revision
+ UINT8 ProgIf; ///< Programming interface
+ UINT8 SubClass; ///< Device subclass
+ UINT8 Class; ///< Class of device defined by <a href="http://www.pcisig.com/specifications/conventional/conventional_pci">PCI 2.2 Specification</a>
+} DL_PCI_INFO;
+#pragma pack()
+
+/**
+ Driver library control structure definition
+**/
+typedef struct
+{
+ //
+ // Component Name(2) Protocol support
+ //
+ CONST EFI_COMPONENT_NAME_PROTOCOL * pComponentNameProtocol; ///< Address of component name protocol
+ CONST EFI_COMPONENT_NAME2_PROTOCOL * pComponentName2Protocol; ///< Address of component name 2 protocol
+ CONST EFI_UNICODE_STRING_TABLE * pControllerNameStringTable; ///< String table for ::DlGetControllerName
+ CONST EFI_UNICODE_STRING_TABLE * pDriverNameStringTable; ///< String table for ::DlGetDriverName
+
+ //
+ // Driver Binding Protocol support
+ //
+ EFI_DRIVER_BINDING_PROTOCOL * pDriverBindingProtocol; ///< Address of driver binding protocol
+
+ //
+ // Loaded Image Protocol support
+ //
+ EFI_IMAGE_UNLOAD pfnUnload; ///< Driver unload routine
+} DL_DRIVER_LIB;
+
+//------------------------------------------------------------------------------
+// Globals
+//------------------------------------------------------------------------------
+
+extern CONST DL_DRIVER_LIB mDriverLib; ///< Driver library control structure
+extern EFI_GUID * mpDriverProtocol; ///< Driver protocol GUID attached to the controller handle
+
+//------------------------------------------------------------------------------
+// Component Name(2) Protocol API
+//------------------------------------------------------------------------------
+
+/**
+ Locate a matching ACPI device path node
+
+ This routine walks the device path attached to the ControllerHandle
+ and determines if the last (non-end) device path node is an
+ ACPI_HID_DEVICE_PATH node and if the CID or _CIDSTR values
+ match the specified values.
+
+ @param[in] CompatibleIdentification The value to match against the CID
+ value in the ACPI_HID_DEVICE_PATH
+ node. This value must be zero when
+ the CompatibleIdentification
+ value is not NULL.
+ @param[in] CompatibleIdentificationString This value is specified as NULL
+ when the CompatibleIdentification
+ value is non-zero. When the
+ CompatibleIdentification value is
+ zero (0), this value should point
+ to a zero terminated charater
+ string value.
+
+ @return When the ACPI device path node is found, this routine
+ returns the pointer to the ACPI_HID_DEVICE_PATH node.
+ Otherwise when the device path is not found this routine
+ returns NULL.
+
+**/
+CONST ACPI_HID_DEVICE_PATH *
+EFIAPI
+DlAcpiFindDeviceWithMatchingCid (
+ EFI_HANDLE ControllerHandle,
+ UINTN CompatibleIdentification,
+ CONST CHAR8 * CompatibleIdentificationString OPTIONAL
+ );
+
+/**
+ Retrieves a Unicode string that is the user readable name of the controller
+ that is being managed by a driver.
+
+ This function retrieves the user readable name of the controller specified by
+ ControllerHandle and ChildHandle in the form of a Unicode string. If the
+ driver specified by This has a user readable name in the language specified by
+ Language, then a pointer to the controller name is returned in ControllerName,
+ and EFI_SUCCESS is returned. If the driver specified by This is not currently
+ managing the controller specified by ControllerHandle and ChildHandle,
+ then EFI_UNSUPPORTED is returned. If the driver specified by This does not
+ support the language specified by Language, then EFI_UNSUPPORTED is returned.
+
+ @param[in] pThis A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+ EFI_COMPONENT_NAME_PROTOCOL instance.
+ @param[in] ControllerHandle The handle of a controller that the driver
+ specified by This is managing. This handle
+ specifies the controller whose name is to be
+ returned.
+ @param[in] ChildHandle The handle of the child controller to retrieve
+ the name of. This is an optional parameter that
+ may be NULL. It will be NULL for device
+ drivers. It will also be NULL for a bus drivers
+ that wish to retrieve the name of the bus
+ controller. It will not be NULL for a bus
+ driver that wishes to retrieve the name of a
+ child controller.
+ @param[in] pLanguage A pointer to a Null-terminated ASCII string
+ array indicating the language. This is the
+ language of the driver name that the caller is
+ requesting, and it must match one of the
+ languages specified in SupportedLanguages. The
+ number of languages supported by a driver is up
+ to the driver writer. Language is specified in
+ RFC 3066 or ISO 639-2 language code format.
+ @param[out] ppControllerName A pointer to the Unicode string to return.
+ This Unicode string is the name of the
+ controller specified by ControllerHandle and
+ ChildHandle in the language specified by
+ Language from the point of view of the driver
+ specified by This.
+
+ @retval EFI_SUCCESS The Unicode string for the user readable name in
+ the language specified by Language for the
+ driver specified by This was returned in
+ DriverName.
+ @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
+ EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+ @retval EFI_INVALID_PARAMETER ControllerName is NULL.
+ @retval EFI_UNSUPPORTED The driver specified by This is not currently
+ managing the controller specified by
+ ControllerHandle and ChildHandle.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support
+ the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+DlGetControllerName (
+ IN EFI_COMPONENT_NAME_PROTOCOL * pThis,
+ IN EFI_HANDLE ControllerHandle,
+ IN OPTIONAL EFI_HANDLE ChildHandle,
+ IN CHAR8 * pLanguage,
+ OUT CHAR16 ** ppControllerName
+ );
+
+/**
+ Retrieves a Unicode string that is the user readable name of the driver.
+
+ This function retrieves the user readable name of a driver in the form of a
+ Unicode string. If the driver specified by This has a user readable name in
+ the language specified by Language, then a pointer to the driver name is
+ returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
+ by This does not support the language specified by Language,
+ then EFI_UNSUPPORTED is returned.
+
+ @param[in] pThis A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+ EFI_COMPONENT_NAME_PROTOCOL instance.
+ @param[in] pLanguage A pointer to a Null-terminated ASCII string
+ array indicating the language. This is the
+ language of the driver name that the caller is
+ requesting, and it must match one of the
+ languages specified in SupportedLanguages. The
+ number of languages supported by a driver is up
+ to the driver writer. Language is specified
+ in RFC 3066 or ISO 639-2 language code format.
+ @param[out] ppDriverName A pointer to the Unicode string to return.
+ This Unicode string is the name of the
+ driver specified by This in the language
+ specified by Language.
+
+ @retval EFI_SUCCESS The Unicode string for the Driver specified by
+ This and the language specified by Language was
+ returned in DriverName.
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+ @retval EFI_INVALID_PARAMETER DriverName is NULL.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support
+ the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+DlGetDriverName (
+ IN EFI_COMPONENT_NAME_PROTOCOL * pThis,
+ IN CHAR8 * pLanguage,
+ OUT CHAR16 ** ppDriverName
+ );
+
+//------------------------------------------------------------------------------
+// Loaded Image Protocol Support
+//------------------------------------------------------------------------------
+
+/**
+Common driver entry point
+
+ @param[in] ImageHandle Handle for the image
+ @param[in] pSystemTable Address of the system table.
+
+ @retval EFI_SUCCESS Image successfully loaded.
+
+**/
+EFI_STATUS
+EFIAPI
+DlEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE * pSystemTable
+ );
+
+/**
+ Driver unload routine
+
+ @param[in] ImageHandle Handle for the image.
+
+ @retval EFI_SUCCESS Image may be unloaded
+
+**/
+EFI_STATUS
+EFIAPI
+DlDriverUnload (
+ IN EFI_HANDLE ImageHandle
+ );
+
+//------------------------------------------------------------------------------
+// PCI Support
+//------------------------------------------------------------------------------
+
+/**
+ Read PCI device information
+
+ This routine fills in the ::DL_PCI_INFO structure with the data
+ from configuration space.
+
+ @param[in] Controller Handle for the controller.
+ @param[in] DriverBindingHandle Handle for binding protocols.
+ @param[in] Attributes Attributes for OpenProtocol
+ @param[in] pPciInfo Address of a ::DL_PCI_INFO structure.
+ @param[out] ppPciIo Optional address to receive the EFI_PCI_IO_PROTCOL,
+ The caller must close the PCI I/O protocol if this
+ address is not NULL.
+
+ @retval EFI_SUCCESS The structure was initialized.
+
+**/
+EFI_STATUS
+DlPciInfo (
+ IN EFI_HANDLE Controller,
+ IN EFI_HANDLE DriverBindingHandle,
+ IN UINT32 Attributes,
+ IN DL_PCI_INFO * pPciInfo,
+ OUT EFI_PCI_IO_PROTOCOL ** ppPciIo
+ );
+
+//------------------------------------------------------------------------------
+
+#endif // _DRIVER_LIB_H
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/DxeRuntimePciLibPciExpress.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/DxeRuntimePciLibPciExpress.h new file mode 100644 index 0000000000..0adefa37b9 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/DxeRuntimePciLibPciExpress.h @@ -0,0 +1,52 @@ +/** @file
+ Header file for the Dxe Runtime PCI Express library.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _DXE_RUNTIME_PCI_LIB_PCIEXPRESS_H_
+#define _DXE_RUNTIME_PCI_LIB_PCIEXPRESS_H_
+
+//
+// Function prototypes
+//
+
+/**
+ Constructor for Pci library. Register VirtualAddressNotifyEvent() notify function
+ It will ASSERT() if that operation fails
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+EFIAPI
+PciLibConstructor (
+ VOID
+ );
+
+/**
+ Register memory space
+ If StartAddress > 0x0FFFFFFF, then ASSERT().
+ If SmPciLibAddressMapIndex) > PCI_LIB_ADDRESS_MAP_MAX_ITEM, then ASSERT().
+
+ @param[in] Address Starting address of the memory space
+ @param[in] Length Length of the memory space
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+EFIAPI
+PciLibRegisterMemory (
+ IN UINTN Address,
+ IN UINTN Length
+ );
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/GpioLib.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/GpioLib.h new file mode 100644 index 0000000000..2e1b60ed95 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/GpioLib.h @@ -0,0 +1,1092 @@ +/** @file
+ Library for GPIO Pin Programming.
+
+ Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _GPIO_LIB_H_
+#define _GPIO_LIB_H_
+
+#include <PiPei.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBaseAddresses.h>
+#include "PchAccess.h"
+#include <Library/TimerLib.h>
+#include <Library/PchPlatformLib.h>
+
+#define SD_MMIO_TIMEOUT 5
+#define HOST_CONTROL_1_REGISTER 0x28
+#define SD_POWER_CONTROL_REGISTER 0x29
+
+#define INVALID_COMMUNITY 0x01
+#define CFIO_COMMUNITY_NORTH 0x01
+#define CFIO_COMMUNITY_EAST 0x02
+#define CFIO_COMMUNITY_SOUTH_EAST 0x03
+#define CFIO_COMMUNITY_SOUTH_WEST 0x04
+
+// PAD registers offsets
+#define GPIO_MMIO_OFFSET_SW 0x0000
+#define GPIO_MMIO_OFFSET_N 0x8000
+#define GPIO_MMIO_OFFSET_E 0x10000
+#define GPIO_MMIO_OFFSET_SE 0x18000
+#define GPIO_MMIO_OFFSET_VIRT 0x20000
+
+#define CHV_GPIO_PAD_CONF0_OFFSET 0x0
+#define CHV_GPIO_PAD_CONF1_OFFSET 0x4
+#define CHV_GPIO_WAKE_REG0_BITS 0x20
+
+#define LOW 0
+#define HIGH 1
+#define MASK_WAKE 0
+#define UNMASK_WAKE 1
+
+// Families registers offsets
+#define GPIO_FAMILY_CONF_REGS_OFF 0x4400
+#define GPIO_FAMILY_CONF_REGS_SIZE 0x400
+#define GPIO_REGS_SIZE 8
+
+#define RCOMP_CONTROl_REG 0x0
+#define RCOMP_OFFSET_REG 0x4
+#define RCOMP_OVERRIDE_REG 0x8
+#define RCOMP_VALUE_REG 0xC
+#define FAMILY_RCOMP_CONFIG_REG 0x10
+#define FAMILY_CONFIG_REG 0x14
+
+// GPIO Security registers offset
+#define GPIO_READ_ACCESS_POLICY_REG 0x0000
+#define GPIO_WRITE_ACCESS_POLICY_REG 0x0100
+#define GPIO_WAKE_STATUS_REG 0x0200
+#define GPIO_WAKE_MASK_REG0 0x0280
+#define GPIO_WAKE_MASK_REG1 0x0284
+#define GPIO_INTERRUPT_STATUS 0x0300
+#define GPIO_INTERRUPT_MASK 0x0380
+#define GPE0A_STS_REG 0x20
+#define GPE0A_EN_REG 0x28
+#define ALT_GPIO_SMI_REG 0x38
+#define GPIO_ROUT_REG 0x58
+// Broad cast registers
+#define GPIO_FAMILY_BW_MASK_31_0 0x1000
+#define GPIO_FAMILY_BW_DATA_31_0 0x1004
+#define GPIO_FAMILY_BROADCAST_REG_MASK 0x1008
+#define GPIO_PAD_BW_DATA_31_0 0x4004
+#define GPIO_PAD_BROADCAST_REG_MASK_0 0x4008
+
+#define MAX_FAMILY_PAD_GPIO_NO 15
+#define FAMILY0_PAD_REGS_OFF 0x4400
+#define FAMILY_PAD_REGS_SIZE 0x400
+
+#define GPIO_PAD_MODE_MASK 0xFFF0FFFF
+#define GPIO_EN_MASK 0xFFFF7FFF
+#define PULLUP_OR_PULLDOWN_MASK 0xFF8FFFFF
+#define PULL_VALUE_MASK 0xFF8FFFFF
+#define GPIO_INV_RXTX_MASK 0xFFFFFF0F
+#define GPIO_INT_MASK 0x0FFFFFFF
+#define GPIO_INT_TYPE 0xFFFFFFF8
+
+#define GPIO_PAD_LOCK 0x80000000
+#define PULL_UP_EN 0x00800000
+#define GPIO_DIRECTION_EN 0x00008000
+#define GPIO_DIRECTION 0x00000700
+#define GPIO_TX_STATE 0x00000002
+
+#define GPIO_RETURN_FAIL 1
+#define GPIO_RETURN_PASS 0
+
+//PAD numbers
+#define PAD0 0x00
+#define PAD1 0x01
+
+//PAD Read or Write
+#define PAD_READ 0x00
+#define PAD_WRITE 0x01
+
+//PAD Lock Status
+#define LOCKED 0x01
+#define UNLOCKED 0x00
+
+//Pull Values
+#define PULL_1K 0x00100000
+#define PULL_5K 0x00200000
+#define PULL_20K 0x00400000
+
+#define NA 0xFF
+
+#pragma pack(1)
+typedef enum
+{
+ Native =0xff,
+ GPIO = 0, // Native, no need to set PAD_VALUE
+ GPO = 1, // GPI, input only in PAD_VALUE
+ GPI = 2, // GPO, output only in PAD_VALUE
+ HI_Z = 3,
+} GPIO_En;
+
+typedef enum
+{
+ LO = 0,
+ HI = 1,
+} GPO_D4;
+
+typedef enum
+{
+ F0 = 0,
+ F1 = 1,
+ F2 = 2,
+ F3 = 3
+} GPIO_FUNC_NUM;
+
+// Mapping to CONF0 bit 27:24
+// Note: Assume "Direct Irq En" is not set, unless specially notified
+typedef enum
+{
+ TRIG_ = 0,
+ TRIG_Edge_High = /*BIT3 |*/ BIT1, // Positive Edge (Rasing)
+ TRIG_Edge_Low = /*BIT3 |*/ BIT2, // Negative Edge (Falling)
+ TRIG_Edge_Both = /*BIT3 |*/ BIT2 | BIT1, // Both Edge
+ TRIG_Level_High= /*BIT3 |*/ BIT2 | BIT0, // Level High
+ TRIG_Level_Low = /*BIT3 |*/ BIT1 | BIT0, // Level Low
+} INT_TYPE;
+
+typedef enum
+{
+ P_NONE = 0, // Pull None
+ P_20K_L = 1, // Pull Down 20K
+ P_5K_L = 2, // Pull Down 5K
+ P_1K_L = 4, // Pull Down 1K
+ P_20K_H = 9, // Pull Up 20K
+ P_5K_H = 10, // Pull Up 5K
+ P_1K_H = 12 // Pull Up 1K
+} PULL_TYPE;
+
+typedef enum
+{
+ _DISABLE = 0, // Disable
+ _ENABLE = 1, // Enable
+} PARKMODEENB;
+
+typedef enum
+{
+ VOLT_3_3 = 0, // Working on 3.3 Volts
+ VOLT_1_8 = 1, // Working on 1.8 Volts
+} VP18MODE;
+
+typedef enum
+{
+ DISABLE_HS = 0, // Disable high speed mode
+ ENABLE_HS = 1, // Enable high speed mode
+} HSMODE;
+
+typedef enum
+{
+ PULL_UP = 0, // On Die Termination Up
+ PULL_DOWN = 1, // On Die Termination Down
+} ODTUPDN;
+
+typedef enum
+{
+ DISABLE_OD =0, // On Die Termination Disable
+ ENABLE_OD =1, // On Die Termination Enable
+} ODTEN;
+
+typedef enum
+{
+ ONE_BIT = 1,
+ TWO_BIT = 3,
+ THREE_BIT = 7,
+ FOUR_BIT = 15,
+ FIVE_BIT = 31,
+ SIX_BIT = 63,
+ SEVEN_BIT = 127,
+ EIGHT_BIT = 255
+}BITS;
+
+typedef union {
+ UINT32 famCnf;
+ struct {
+ UINT32 CurrSrcStr : 3;
+ UINT32 reserve : 14;
+ UINT32 odpullEn : 1;
+ UINT32 odpulldir : 1;
+ UINT32 hsMode : 1;
+ UINT32 Reseve3 : 1;
+ UINT32 vpMode : 1;
+ UINT32 Reseve2 : 2;
+ UINT32 HYSCTL : 2;
+ UINT32 parkMode : 1;
+ UINT32 reseve1 : 5;
+ }r;
+} CONF_FAMILY;
+
+typedef enum
+{
+ M0 =0,
+ M1,
+ M2,
+ M3,
+ M4,
+ M5,
+ M6,
+ M7,
+ M8,
+ M9,
+ M10,
+ M11,
+ M12,
+ M13,
+ M14,
+ M15,
+} ModeList;
+
+typedef enum
+{
+ Line0 =0,
+ Line1 =1,
+ Line2 =2,
+ Line3 =3,
+ Line4 =4,
+ Line5 =5,
+ Line6 =6,
+ Line7 =7,
+ Line8 =8,
+ Line9 =9,
+ Line10 =10,
+ Line11 =11,
+ Line12 =12,
+ Line13 =13,
+ Line14 =14,
+ Line15 =15,
+} Int_Select;
+
+typedef enum
+{
+ INT_DIS =0,
+ Trig_Edge_Low =1,
+ Trig_Edge_High =2,
+ Trig_Edge_Both =3,
+ Trig_Level =4,
+} INT_Type;
+
+typedef enum
+{
+ glitch_Disable = 0,
+ En_EdgeDetect,
+ En_RX_Data,
+ En_Edge_RX_Data,
+} Glitch_Cfg;
+
+typedef enum
+{
+ Maskable,
+ NonMaskable,
+}mask;
+
+typedef enum
+{
+ NORTH = GPIO_MMIO_OFFSET_N,
+ EAST = GPIO_MMIO_OFFSET_E,
+ SOUTHWEST = GPIO_MMIO_OFFSET_SW,
+ SOUTHEAST = GPIO_MMIO_OFFSET_SE,
+ VIRTUAL = GPIO_MMIO_OFFSET_VIRT,
+} coms;
+
+typedef enum
+{
+ SMI = 1,
+ SCI = 2,
+} GPE_config;
+
+//
+// InvertRxTx 7:4
+// 0 - No Inversion
+// 1 - Inversion
+// [0] RX Enable
+// [1] TX Enable
+// [2] RX Data
+// [3] TX Data
+//
+typedef enum
+{
+ No_Inversion = 0,
+ Inv_RX_Enable = 0x1,
+ Inv_TX_Enable = 0x2,
+ Inv_RX_TX_Enable = 0x3,
+ Inv_RX_Data = 0x4,
+ Inv_RX_Data_TX_Enable = 0x6,
+ Inv_TX_Data = 0x8,
+} InvertRX_TX;
+
+typedef union {
+ UINT32 padCnf0;
+ struct {
+ UINT32 GPIORXState : 1; // 0 GPIO RX State (GPIORXState).
+ UINT32 GPIOTXState : 1; // 1 GPIO TX State (GPIOTXState).
+ UINT32 Reserved1 : 5; // 2-6 Reserved
+ UINT32 Gpio_Light_Mode : 1; // 7 GPIO Light Mode
+ UINT32 GPIOCfg : 3; // 8-10 GPIO Config (GPIOCfg).
+ UINT32 Reserved2 : 4; // 11-14 Reserved
+ UINT32 GPIOEn : 1; // 15 GPIO Enable (GPIOEn)
+ UINT32 Pmode : 4; // 16-19 Pad Mode (Pmode)
+ UINT32 Term : 4; // 20-23 Termination (Term)
+ UINT32 RXTXEnCfg : 2; // 24-25 RX/TX Enable Config (RXTXEnCfg)
+ UINT32 GFCfg : 2; // 26-27 Glitch Filter Config (GFCfg)
+ UINT32 IntSel : 4; // 28-31 Interrupt Select (IntSel)
+ }r;
+} CHV_CONF_PAD0;
+
+typedef union {
+ UINT32 padCnf1;
+ struct {
+ UINT32 IntWakeCfg : 3; // 0-2 Interrupt and Wake Configuration (IntWakeCfg).
+ UINT32 ODEn : 1; // 3 Open Drain Enable (ODEn).
+ UINT32 InvRXTX : 4; // 4-7 Invert RX TX (InvRXTX)
+ UINT32 Reserved : 2; // 8-9 Reserved.
+ UINT32 IOSTerm : 2; // 10-11 I/O Standby Termination (IOSTerm)
+ UINT32 IOSState : 4; // 12-15 I/O Standby State (IOSState)
+ UINT32 analogmuxen : 1; // 16 Analog Mux Enable (analogmuxen)
+ UINT32 ODTEN : 1; // 17 Reserved for On Die Termination Enable (ODTEN)
+ UINT32 ODTUPDN : 1; // 18 Reserved for On Die Termination Up/Down (ODTUPDN)
+ UINT32 HSMODE : 1; // 19 Reserved for High Speed mode (HSMODE)
+ UINT32 VP18Mode : 1; // 20 Reserved for 1.8 V Mode (VP18Mode)
+ UINT32 VP15MODE : 1; // 21 Reserved for 1.5V Mode (VP15MODE)
+ UINT32 CLKNENB : 1; // 22 Reserved for CLKNENB
+ UINT32 AZAMODE : 1; // 23 Reserved for AZAMODE
+ UINT32 HYSCTL : 2; // 24-25 Reserved for Hysteresis Control (HYSCTL)
+ UINT32 PARKMODEENB : 1; // 26 Reserved for Parkmode Enable Bar (PARKMODEENB)
+ UINT32 csen : 1; // 27 Current Source Enable (csen)
+ UINT32 svid_od_en : 1; // 28 SVID 1V Open Drain Mode (svid_1v_od_en)
+ UINT32 Reserved1 : 1; // 29 Reserved for Pad Configuration.
+ UINT32 PadRstCfg : 1; // 30 Pad Reset Config (PadRstCfg)
+ UINT32 CfgLock : 1; // 31 Configuration Lock (CfgLock).
+ }r;
+} CHV_CONF_PAD1;
+
+ #ifdef EFI_DEBUG
+ #define CHV_GPIO_PAD_CONF(pad_name, Mode_Select, Mode, GPIO_Config, GPIO_STATE, Gpio_Light_Mode, INT_Type, INT_S, Term_H_L, Open_Drain, Current_Source, Int_Mask, Glitch_Cfg, InvertRX_TX, WAKE_Mask,Wake_Mask_Bit, GPE, MMIO_Offset, Community ) { \
+ ((((INT_S) != NA) ? ((UINT32) INT_S << 28) : 0) | (((Glitch_Cfg) != NA) ? (Glitch_Cfg << 26) : 0) | (((Term_H_L) != NA) ? (Term_H_L << 20) : 0) | (((Mode_Select) == GPIO) ? ((Mode << 16 ) | (1 << 15) ) : ( (Mode << 16 ))) | (((GPIO_Config) != NA) ? (GPIO_Config << 8 ) : 0) | (((Gpio_Light_Mode) != NA) ? (Gpio_Light_Mode << 7) : 0) | (((GPIO_STATE) == HIGH ) ? 2 : 0)), \
+ ((((INT_S) != NA) ? ((UINT32) FOUR_BIT << 28) : 0) | (((Glitch_Cfg) != NA) ? (TWO_BIT << 26) : 0) | (((Term_H_L) != NA) ? (FOUR_BIT << 20) : 0) | (FIVE_BIT << 15) | (((GPIO_Config) != NA) ? (THREE_BIT << 8) : 0) | (((Gpio_Light_Mode) != NA) ? (ONE_BIT << 7) : 0) | (((GPIO_STATE) != NA ) ? ONE_BIT << 1 : 0)), \
+ ((((Current_Source) != NA) ? (Current_Source << 27) : 0) | (((InvertRX_TX) != NA) ? InvertRX_TX << 4 : 0) | (((Open_Drain) != NA) ? Open_Drain << 3 : 0 ) | (((INT_Type) != NA) ? INT_Type : 0)), \
+ ((((Current_Source) != NA) ? (ONE_BIT << 27) : 0) | (((InvertRX_TX) != NA) ? FOUR_BIT << 4 : 0) | (((Open_Drain) != NA) ? ONE_BIT << 3 : 0) | (((INT_Type) != NA) ? THREE_BIT : 0)), Community, (MMIO_Offset != NA) ? (IO_BASE_ADDRESS+Community +MMIO_Offset) : 0, pad_name, ((((GPE) != NA) ? (GPE << 0) : 0) | (((WAKE_Mask) != NA) ? (WAKE_Mask << 2) : 0) | (((Int_Mask) != NA) ? (Int_Mask << 3) : 0))| (((Wake_Mask_Bit) != NA) ? (Wake_Mask_Bit << 4) : (NA << 4))}
+ #else
+ #define CHV_GPIO_PAD_CONF(pad_name, Mode_Select, Mode, GPIO_Config, GPIO_STATE, Gpio_Light_Mode, INT_Type, INT_S, Term_H_L, Open_Drain, Current_Source, Int_Mask, Glitch_Cfg, InvertRX_TX, WAKE_Mask,Wake_Mask_Bit, GPE, MMIO_Offset, Community ) { \
+ ((((INT_S) != NA) ? ((UINT32) INT_S << 28) : 0) | (((Glitch_Cfg) != NA) ? (Glitch_Cfg << 26) : 0) | (((Term_H_L) != NA) ? (Term_H_L << 20) : 0) | (((Mode_Select) == GPIO) ? ((Mode << 16 ) | (1 << 15) ) : ( (Mode << 16 ))) | (((GPIO_Config) != NA) ? (GPIO_Config << 8 ) : 0) |(((Gpio_Light_Mode) != NA) ? (Gpio_Light_Mode << 7) : 0) | (((GPIO_STATE) == HIGH ) ? 2 : 0)), \
+ ((((INT_S) != NA) ? ((UINT32) FOUR_BIT << 28) : 0) | (((Glitch_Cfg) != NA) ? (TWO_BIT << 26) : 0) | (((Term_H_L) != NA) ? (FOUR_BIT << 20) : 0) | (FIVE_BIT << 15) | (((GPIO_Config) != NA) ? (THREE_BIT << 8) : 0) | (((Gpio_Light_Mode) != NA) ? (ONE_BIT << 7) : 0) | (((GPIO_STATE) != NA ) ? ONE_BIT << 1 : 0)), \
+ ((((Current_Source) != NA) ? (Current_Source << 27) : 0) | (((InvertRX_TX) != NA) ? InvertRX_TX << 4 : 0) | (((Open_Drain) != NA) ? Open_Drain << 3 : 0 ) | (((INT_Type) != NA) ? INT_Type : 0)), \
+ ((((Current_Source) != NA) ? (ONE_BIT << 27) : 0) | (((InvertRX_TX) != NA) ? FOUR_BIT << 4 : 0) | (((Open_Drain) != NA) ? ONE_BIT << 3 : 0) | (((INT_Type) != NA) ? THREE_BIT : 0)), Community, (MMIO_Offset != NA) ? (IO_BASE_ADDRESS+Community +MMIO_Offset) : 0,((((GPE) != NA) ? (GPE << 0) : 0) | (((WAKE_Mask) != NA) ? (WAKE_Mask << 2) : 0) | (((Int_Mask) != NA) ? (Int_Mask << 3) : 0)) | (((Wake_Mask_Bit) != NA) ? (Wake_Mask_Bit << 4) : (NA << 4))}
+ #endif
+
+#define CHV_GPIO_PAD_CONFG0(Mode_Select, Mode, GPIO_Config, GPIO_STATE, Gpio_Light_Mode, INT_S, Term_H_L, Glitch_Cfg) \
+ ((((INT_S) != NA) ? ((UINT32) INT_S << 28) : 0) | (((Glitch_Cfg) != NA) ? (Glitch_Cfg << 26) : 0) | (((Term_H_L) != NA) ? (Term_H_L << 20) : 0) | (((Mode_Select) == GPIO) ? ((Mode << 16 ) | (1 << 15) ) : ( (Mode << 16 ))) | (((GPIO_Config) != NA) ? (GPIO_Config << 8 ) : 0) |(((Gpio_Light_Mode) != NA) ? (Gpio_Light_Mode << 7) : 0) | (((GPIO_STATE) == HIGH ) ? 2 : 0))
+
+#define CHV_GPIO_PAD_CONFG0_CHANGE(GPIO_Config, GPIO_STATE, Gpio_Light_Mode, INT_S, Term_H_L, Glitch_Cfg) \
+ ((((INT_S) != NA) ? ((UINT32) FOUR_BIT << 28) : 0) | (((Glitch_Cfg) != NA) ? (TWO_BIT << 26) : 0) | (((Term_H_L) != NA) ? (FOUR_BIT << 20) : 0) | (FIVE_BIT << 15) | (((GPIO_Config) != NA) ? (THREE_BIT << 8) : 0) | (((Gpio_Light_Mode) != NA) ? (ONE_BIT << 7) : 0) | (((GPIO_STATE) != NA ) ? ONE_BIT << 1 : 0))
+
+#define CHV_GPIO_PAD_CONFG1(INT_Type, Open_Drain, Current_Source, InvertRX_TX) \
+ ((((Current_Source) != NA) ? (Current_Source << 27) : 0) | (((InvertRX_TX) != NA) ? InvertRX_TX << 4 : 0) | (((Open_Drain) != NA) ? Open_Drain << 3 : 0 ) | (((INT_Type) != NA) ? INT_Type : 0))
+#define CHV_GPIO_PAD_CONFG1_CHANGE(INT_Type, Open_Drain, Current_Source, InvertRX_TX) \
+ ((((Current_Source) != NA) ? (ONE_BIT << 27) : 0) | (((InvertRX_TX) != NA) ? FOUR_BIT << 4 : 0) | (((Open_Drain) != NA) ? ONE_BIT << 3 : 0) | (((INT_Type) != NA) ? THREE_BIT : 0))
+#define CHV_GPIO_PAD_MMIO(MMIO_Offset, Community) (MMIO_Offset != NA) ? (IO_BASE_ADDRESS+Community +MMIO_Offset) : 0
+#define CHV_GPIO_PAD_MISC(Int_Mask, WAKE_Mask,Wake_Mask_Bit, GPE) ((((GPE) != NA) ? (GPE << 0) : 0) | (((WAKE_Mask) != NA) ? (WAKE_Mask << 2) : 0) | (((Int_Mask) != NA) ? (Int_Mask << 3) : 0)) | (((Wake_Mask_Bit) != NA) ? (Wake_Mask_Bit << 4) : (NA << 4))
+
+typedef union {
+ UINT32 micsData;
+ struct {
+ UINT32 GPE_ENABLE : 2; // 0 set if GPIO GPE is enable.
+ UINT32 wake_able : 1; // 2 set if GPIO Wake capable
+ UINT32 intr_mask : 1; // 3 set if GPIO interrupt masked
+ UINT32 Wake_Mask_Position : 8; // 4 set the GPIO wake mask bit position
+ }r;
+} CHV_PAD_MISC;
+
+typedef struct {
+ CHV_CONF_PAD0 padConfg0;
+ CHV_CONF_PAD0 padConfg0_changes;
+ CHV_CONF_PAD1 padConfg1;
+ CHV_CONF_PAD1 padConfg1_changes;
+ UINT32 Community;
+ UINT32 MMIO_ADDRESS;
+#ifdef EFI_DEBUG
+ CHAR16 *pad_name; // GPIO Pin Name for debug purpose
+#endif
+ CHV_PAD_MISC PAD_MISC;
+} CHV_GPIO_PAD_INIT;
+
+typedef union {
+ UINT32 mics1;
+ struct {
+ UINT32 RCOMP_ENABLE : 1; // 0 set if rcomp is enable.
+ }r;
+} CHV_FAMILY_MISC;
+
+typedef struct {
+ CONF_FAMILY confg;
+ CONF_FAMILY confg_change;
+ CHV_FAMILY_MISC family_misc;
+ UINT32 mmioAddr;
+#ifdef EFI_DEBUG
+ CHAR16 *family_name; // GPIO Family Name for debug purpose
+#endif
+} GPIO_CONF_FAMILY_INIT;
+
+typedef union {
+ UINT32 wake_;
+ struct {
+ UINT32 GPIO_ : 32; // 1 set if GPIO 1 wake enable.
+ }r;
+} GPIO_WAKE;
+
+typedef union {
+ UINT32 intr_;
+ struct {
+ UINT32 GPIO_ : 32; // 1 set if GPIO 1 wake enable.
+ }r;
+} GPIO_INTERRUPT;
+
+typedef union {
+ UINT32 rout_;
+ struct {
+ UINT32 GPIO_ROUT : 32;
+ }r;
+} GPIO_ROUT;
+
+typedef union {
+ UINT32 gpe0a_;
+ struct {
+ UINT32 GPIO_EN : 32; //Expand the structure if required.
+ }r;
+} GPE0a_EN;
+
+typedef union {
+ UINT32 smi_;
+ struct {
+ UINT32 GPIO_SMI : 32; //Expand the structure if required.
+ }r;
+} ALT_GPIO_SMI;
+
+//PAD_CONF0_MMIO_ADDR = IOBASE + COMMUNITY_BASE + 0x4400+0x400*Family# + 0x8*Pad#
+ #ifdef EFI_DEBUG
+ #define CHV_GPIO_FAMILY_INIT(family_name, PARKMODEENB, HYSCTL, VP18MODE, HSMODE, ODTUPDN, ODTEN, CurrSrcStr, rComp, familyNo, Community) { ((((PARKMODEENB) != NA) ? (UINT32)PARKMODEENB << 26 : 0) | (((HYSCTL) != NA) ? HYSCTL << 24 : 0) | (((VP18MODE) != NA) ? VP18MODE << 21 : 0) | (((HSMODE) != NA) ? HSMODE << 19 : 0) | (((ODTUPDN) != NA) ? ODTUPDN << 18 : 0) | (((ODTEN) != NA) ? ODTEN << 17 : 0) | (CurrSrcStr)), \
+ ((((PARKMODEENB) != NA) ? (UINT32)ONE_BIT << 26 : 0) | (((HYSCTL) != NA) ? TWO_BIT << 24 : 0) | (((VP18MODE) != NA) ? ONE_BIT << 21 : 0) | (((HSMODE) != NA) ? ONE_BIT << 19 : 0) | (((ODTUPDN) != NA) ? ONE_BIT << 18 : 0) | (((ODTEN) != NA) ? ONE_BIT << 17 : 0) | (THREE_BIT)), \
+ ((rComp == ENABLE) ? 1 : 0), (familyNo != NA) ? (IO_BASE_ADDRESS+Community +(0x80*familyNo)+0x1080) : 0, family_name }
+ #else
+ #define CHV_GPIO_FAMILY_INIT(family_name, PARKMODEENB, HYSCTL, VP18MODE, HSMODE, ODTUPDN, ODTEN, CurrSrcStr, rComp, familyNo, Community) { ((((PARKMODEENB) != NA) ? (UINT32)PARKMODEENB << 26 : 0) | (((HYSCTL) != NA) ? HYSCTL << 24 : 0) | (((VP18MODE) != NA) ? VP18MODE << 21 : 0) | (((HSMODE) != NA) ? HSMODE << 19 : 0) | (((ODTUPDN) != NA) ? ODTUPDN << 18 : 0) | (((ODTEN) != NA) ? ODTEN << 17 : 0) | (CurrSrcStr)), \
+ ((((PARKMODEENB) != NA) ? (UINT32)ONE_BIT << 26 : 0) | (((HYSCTL) != NA) ? TWO_BIT << 24 : 0) | (((VP18MODE) != NA) ? ONE_BIT << 21 : 0) | (((HSMODE) != NA) ? ONE_BIT << 19 : 0) | (((ODTUPDN) != NA) ? ONE_BIT << 18 : 0) | (((ODTEN) != NA) ? ONE_BIT << 17 : 0) | (THREE_BIT)), \
+ ((rComp == ENABLE) ? 1 : 0), (familyNo != NA) ? (IO_BASE_ADDRESS+Community +(0x80*familyNo)+0x1080) : 0 }
+ #endif
+
+//family_rcomp = IOBASE + COMMUNITY_BASE + 0x1080 + 0x20*family + rcompOffset
+
+/*
+ * RCOMP REGISTERS
+ */
+
+typedef union {
+ UINT32 rcomCtrl;
+ struct {
+ UINT32 InitCalValN : 8; // 0-7 Initial Pull Down Value (InitCalValN)
+ UINT32 InitCalValP : 8; // 8-15 Initial Pull Up Value (InitCalValP)
+ UINT32 RFSMStopCyc : 4; // 16-19 RCOMP FSM Stop Cycles (RFSMStopCyc)
+ UINT32 RFSMStop : 2; // 20-21 RCOMP FSM Stop Condition (RFSMStop)
+ UINT32 ircintclkperiod : 2; // 22-23 IRC Internal Clock Period (ircintclkperiod)
+ UINT32 ircfreq_select : 2; // 24-25 IRCCLK Frequency Select (ircfreq_select)
+ UINT32 reserved : 3; // 26-28 reserved (reserved)
+ UINT32 chicken_bit : 1; // 29 RCOMP FSM Binary Chicken Bit (chicken_bit)
+ UINT32 RcalStart : 1; // 30 RCOMP Calibration Start (RcalStart)
+ UINT32 RFSMEn : 1; // 31 RCOMP FSM Enable (RFSMEn)
+ }r;
+} CHV_RCOMP_CTRL;
+
+typedef union {
+ UINT32 rcompOffset;
+ struct {
+ UINT32 OffNStrVal : 5; // 0-4 Pull Down Offset Strength Value (OffNStrVal).
+ UINT32 OffNStrSign : 1; // 5 Pull Down Offset Strength Sign (OffNStrSign).
+ UINT32 Reserved : 2; // 6-7 Reserved
+ UINT32 OffPStrVal : 5; // 8-12 Pull Up Offset Strength Value (OffPStrVal).
+ UINT32 OffPStrSign : 1; // 13 Pull Up Offset Strength Sign (OffPStrSign)
+ UINT32 Reserved1 : 2; // 14-15 Reserved
+ UINT32 OffNSlewVal : 4; // 16-19 Pull Down Slew Offset (OffNSlewVal)
+ UINT32 OffNSlewSign : 1; // 20 Pull Down Offset Slew Sign (OffNSlewSign)
+ UINT32 Reserved3 : 3; // 21-23 Reserved
+ UINT32 OffPSlewVal : 4; // 24-27 Pull Up Slew Offset (OffPSlewVal)
+ UINT32 OffPSlewSign : 1; // 28 Pull Up Offset Slew Sign (OffPSlewSign)
+ UINT32 Reserved4 : 3; // 29-31 Reserved
+ }r;
+} CHV_RCOMP_OFFSET;
+
+typedef union {
+ UINT32 rcomOver;
+ struct {
+ UINT32 OvrNStrVal : 8; // 0-7 Override Pull Down Strength Value (OvrNStrVal).
+ UINT32 OvrPStrVal : 8; // 8-15 Override Pull Up Strength Value (OvrPStrVal).
+ UINT32 OvrNSlewVal : 4; // 16-19 Override N Slew Value (OvrNSlewVal).
+ UINT32 OvrPSlewVal : 2; // 20-23 Override P Slew Value (OvrPSlewVal).
+ UINT32 Reserved : 6; // 24-29 Reserved.
+ UINT32 OvrLoad : 1; // 30 Override Load (OvrLoad)
+ UINT32 OvrREn : 1; // 31 Override RCOMP Enable (OvrREn)
+ }r;
+} CHV_RCOMP_OVERRIDE;
+
+typedef union {
+ UINT32 rcompValue;
+ struct {
+ UINT32 NStrVal : 8; // 0-7 Pull Down Strength Value (NStrVal).
+ UINT32 PStrVal : 8; // 8-15 Pull Up Strength Value (PStrVal).
+ UINT32 NSlewVal : 4; // 16-19 N Slew Value (NSlewVal)
+ UINT32 PSlewVal : 4; // 20-23 P Slew Value (PSlewVal)
+ UINT32 Reserved : 8; // 24-31 Reserved
+ }r;
+} CHV_RCOMP_VALUE;
+
+typedef union {
+ UINT32 secSAI;
+ struct {
+ UINT32 IA_Untrusted : 1;
+ UINT32 IA_Ucode : 1;
+ UINT32 IA_Smm : 1;
+ UINT32 ucode_NPP : 1;
+ UINT32 IA_Boot : 1;
+ UINT32 IA_Untrusted_5 : 1;
+ UINT32 IA_Untrusted_6 : 1;
+ UINT32 IA_XUcode : 1;
+ UINT32 Punit_Trusted : 1;
+ UINT32 SEC_Trusted : 1;
+ UINT32 Drm : 1;
+ UINT32 FuseStrap_Puller : 1;
+ UINT32 Fuse_Provider : 1;
+ UINT32 Strap_Provider : 1;
+ UINT32 DFX_Untrusted : 1;
+ UINT32 DFX_Trusted : 1;
+ UINT32 PMC_Trusted : 1;
+ UINT32 DRNG : 1;
+ UINT32 ISH_t : 1;
+ UINT32 Device_Untrusted_19 : 1;
+ UINT32 Device_Untrusted_20 : 1;
+ UINT32 Device_Untrusted_21 : 1;
+ UINT32 Device_Untrusted_22 : 1;
+ UINT32 Device_Untrusted_23 : 1;
+ UINT32 Device_Untrusted_24 : 1;
+ UINT32 Device_Untrusted_25 : 1;
+ UINT32 Device_Untrusted_26 : 1;
+ UINT32 Device_Untrusted_27 : 1;
+ UINT32 Device_Untrusted_28 : 1;
+ UINT32 Device_Untrusted_29 : 1;
+ UINT32 Device_Untrusted_30 : 1;
+ UINT32 Device_Untrusted : 1;
+ }r;
+} policy_access_reg;
+
+typedef union {
+ UINT32 familyRcompCnfg;
+ struct {
+ UINT32 NSlewVal : 4; // 0-3 N Slew Value (NSlewVal).
+ UINT32 PSlewVal : 4; // 4-7 P Slew Value (PSlewVal).
+ UINT32 NStaticLegEn : 1; // 8 N Static Leg Enable (NStaticLegEn)
+ UINT32 PStaticLegEn : 1; // 9 P Static Leg Enable (PStaticLegEn)
+ UINT32 reserved : 6; // 10-15 reserved (reserved)
+ UINT32 NStrVal : 8; // 16-23 Pull Down Strength Value (NStrVal)
+ UINT32 PStrVal : 8; // 24-31 Pull Up Strength Value (PStrVal)
+ }r;
+} CHV_FAMILY_RCOMP_CNFG;
+
+typedef struct {
+ UINT32 Offset;
+ policy_access_reg val_;
+ UINT32 Community;
+#ifdef EFI_DEBUG
+ CHAR16 *family_name; // GPIO Family Name for debug purpose
+#endif
+} GPIO_SAI_INIT;
+
+#ifdef EFI_DEBUG
+ #define CHV_GPIO_SAI_INIT(family_name, Offset, value, Community) { Offset, value, Community, family_name}
+#else
+ #define CHV_GPIO_SAI_INIT(family_name, Offset, value, Community) { Offset, value, Community}
+#endif
+
+typedef struct {
+
+#ifdef EFI_DEBUG
+ CHAR16 *pad_name; // GPIO Pin Name for debug purpose
+#endif
+
+ GPIO_En usage; // GPIO pin used as Native mode or GPI/GPO/GPIO mode
+ GPO_D4 gpod4; // GPO default value
+ GPIO_FUNC_NUM func; // Function Number (F0~F7)
+ INT_TYPE int_type; // Edge or Level trigger, low or high active
+ PULL_TYPE pull; // Pull Up or Down
+ UINT8 offset; // Equal with (PCONF0 register offset >> 4 bits)
+} GPIO_CONF_PAD_INIT;
+
+#ifdef EFI_DEBUG
+ #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) {pad_name, usage, gpod4, func, /*int_cap,*/ TRIG_ ## int_type, P_ ## pull, offset}
+#else
+ #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) { usage, gpod4, func, /*int_cap,*/ TRIG_ ## int_type, P_ ## pull, offset}
+#endif
+
+typedef union {
+ UINT32 dw;
+ struct {
+ UINT32 Func_Pin_Mux : 3; // 0:2 Function of CFIO selection
+ UINT32 ipslew : 2; // 3:4 Pad (P) Slew Rate Controls PAD slew rate check Width
+ UINT32 inslew : 2; // 5:6 Pad (N) Slew Rate Controls PAD slew rate
+ UINT32 Pull_assign : 2; // 7:8 Pull assignment
+ UINT32 Pull_strength : 2; // 9:10 Pull strength
+ UINT32 Bypass_flop : 1; // 11 Bypass flop
+ UINT32 Filter_en : 1; // 12 Filter Enable
+ UINT32 Hist_ctrl : 2; // 13:14 hysteresis control
+ UINT32 Hist_enb : 1; // 15 Hysteresis enable, active low
+ UINT32 Delay_line : 6; // 16:21 Delay line values - Delay values for input or output
+ UINT32 Reserved : 3; // 22:24 Reserved
+ UINT32 TPE : 1; // 25 Trigger Positive Edge Enable
+ UINT32 TNE : 1; // 26 Trigger Negative Edge Enable
+ UINT32 Reserved2 : 3; // 27:29 Reserved
+ UINT32 i1p5sel : 1; // 30
+ UINT32 IODEN : 1; // 31 : Open Drain enable. Active high
+ } r;
+} PAD_CONF0;
+
+typedef union {
+ UINT32 dw;
+ struct {
+ UINT32 pad_val : 1; // 0 These registers are implemented as dual read/write with dedicated storage each.
+ UINT32 ioutenb : 1; // 1 output enable
+ UINT32 iinenb : 1; // 2 input enable
+ UINT32 Reserved : 29; // 3:31 Reserved
+ }r;
+} PAD_VAL;
+
+#pragma pack()
+
+#define CONF_MMIO_ADDRESS(CommunityOffset, GpioNumber, PadXOffset) (IO_BASE_ADDRESS + CommunityOffset + FAMILY0_PAD_REGS_OFF + \
+ (FAMILY_PAD_REGS_SIZE * (GpioNumber / MAX_FAMILY_PAD_GPIO_NO)) + \
+ (GPIO_REGS_SIZE * (GpioNumber % MAX_FAMILY_PAD_GPIO_NO)) + PadXOffset)
+
+/**
+ Set GPIO PAD control 0 and 1 registers for N/E/SW/SE GPIO communities
+
+ @param[in] GPIOTable_Index Begin Pin Number to start configuring in GPIO_Conf_Data table
+ @param[in] GPIOTable_NumberofPins Number of Pins to configure in GPIO_Conf_Data table
+ @param[in] Gpio_Conf_Data GPIO_CONF_PAD_INIT data array
+
+**/
+VOID
+InternalGpioPADConfig (
+ IN UINT32 Gpio_Pin_Begin_Num,
+ IN UINT32 Gpio_Pin_Size,
+ CHV_GPIO_PAD_INIT *Gpio_Conf_Data
+ );
+
+/**
+ Set GPIO families register configuration for N/E/SW/SE GPIO communities
+
+ @param[in] Gpio_Families_Mmio_Offset GPIO_MMIO_OFFSET_SW / GPIO_MMIO_OFFSET_N / GPIO_MMIO_OFFSET_E / GPIO_MMIO_OFFSET_SE.
+ @param[in] Gpio_Communities_Num Families numbers to config for GPIO communities.
+ @param[in] Gpio_Families_Data GPIO_CONF_FAMILY_INIT data array for each GPIO family.
+
+**/
+VOID
+InternalGpioFamiliesConfig (
+ IN UINT32 Gpio_Families_Mmio_Offset,
+ IN UINT32 Gpio_Communities_Num,
+ GPIO_CONF_FAMILY_INIT *Gpio_Families_Data
+ );
+
+/**
+ Set GPIO PAD SAI registers for N/E/SW/SE GPIO communities
+
+ @param[in] SAI_Conf_Data GPIO_SAI_INIT data array for each GPIO communities.
+ @param[in] UINT32 Size of the table
+**/
+VOID
+SaiSettingOfGpioFamilies (
+ GPIO_SAI_INIT *SAI_Conf_Data,
+ UINT32 familySize
+ );
+
+/**
+ Function to get the Pin Pad0 MMIO offset
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number.
+
+ @retval UINT32 Pin Mmio Offset
+**/
+UINT32
+EFIAPI
+GetPinMmioOffset (
+ IN UINT32 Community,
+ IN UINT32 PinNum
+ );
+
+/**
+ Function to Read/Write Pad0 or Pad1 control register of given Pin from commnity
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+ @param[in] Padx This can be either Pad0 or Pad1, 0 - PAD0
+ @param[in] ReadOrWrite 0 - Read and 1 - Write of Padx
+ @param[in] PadxValue Pinter to hold the Read/Write value.
+
+**/
+VOID
+ReadWritePadXConf (
+ IN UINT32 Community,
+ IN UINT32 PinNum,
+ IN BOOLEAN Padx,
+ IN BOOLEAN ReadOrWrite,
+ IN OUT UINT32 *PadxValue
+ );
+
+/**
+ Function to configure pin to any one of GPIO fucntionalities for specified pin in the community
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+ @param[in] Direction Gpio direction
+ GPIO - 0
+ GPO - 1
+ GPI - 2
+ HI-Z - 3
+ @param[in] Value Configure HIGH or LOW for GPO (Tx)
+ 1-HIGH,0-Low
+**/
+VOID
+SetGPIOMode (
+ IN UINT32 Community,
+ IN UINT32 PinNum,
+ IN UINT8 Direction,
+ IN BOOLEAN Value
+ );
+
+/**
+ Function to get the GPIO direction configuration for specified pin in the community
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+
+ @retval UINT8 The value for GPIO directin
+ GPIO-0
+ GPO-1
+ GPI-2
+ HI-Z-3
+**/
+UINT8
+EFIAPI
+GetGPIOMode (
+ IN UINT32 Community,
+ IN UINT32 PinNum
+ );
+
+/**
+ Function to configure the specified pin to any one of native mode
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+ @param[in] Mode Native Mode - M0, M1, .., M15
+
+ @retval Boolean 0 - successful native mode configuration,1 - unsuccessful, Pad Could be locked
+**/
+BOOLEAN
+EFIAPI
+SetNativeMode (
+ IN UINT32 Community,
+ IN UINT32 PinOffset,
+ IN UINT8 Mode
+ );
+
+/**
+ Function to get the native mode number
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+
+ @retval Mode Native Mode M0-0, M1-11, .., M15-15
+ Failure - Value 0xFF.
+**/
+UINT8
+EFIAPI
+GetNativeMode (
+ IN UINT32 Community,
+ IN UINT32 PinOffset
+ );
+
+/**
+ Function to configure GPO Tx State for specified pin in the community.
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+ @param[in] Value 1-HIGH, 0-LOW
+
+**/
+VOID
+GPIOSetTXValue (
+ IN UINT32 Community,
+ IN UINT32 PinNum,
+ IN BOOLEAN Value
+ );
+
+/**
+ Function to get the GPO Tx state of specified pin in the community.
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+
+ @retval Boolean 1-HIGH,0-LOW
+**/
+BOOLEAN
+EFIAPI
+GPIOGetTXValue (
+ IN UINT32 Community,
+ IN UINT32 PinNum
+ );
+
+/**
+ Function to configure pin to any one of GPIO fucntionalities for specified pin in the community
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+ @param[in] Pullup Enable pullup or pulldown
+ 1-Pull Up
+ 0-Pull Down
+ @param[in] Value Pull value
+ 1-1K
+ 2-5K
+ 4-20K
+ @retval Boolean 0-Successful termination configured, 1-Unsuccessful could be due to unsupported value.
+**/
+BOOLEAN
+EFIAPI
+GPIOSetPadTerm (
+ IN UINT32 Community,
+ IN UINT32 PinNum,
+ IN BOOLEAN PullUp,
+ IN UINT8 Value
+ );
+
+/**
+ Function to current pin termantaion value of specified pin in the community
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+ @param[out] *PullValue Pull value
+ 1 - 1K
+ 2 - 5K
+ 4 - 20K
+
+ @retval Boolean 1-Pull Up,0-Pull Down
+**/
+BOOLEAN
+GPIOGetPadTerm (
+ IN UINT32 Community,
+ IN UINT32 PinNum,
+ IN OUT UINT8 *PullValue
+ );
+
+/**
+ Function to Configure the Invert Rx/Tx Data and Rx/Tx Enable of specified pin in the community
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+ @param[out] InvRxTxValue 0=No Inversion, 1=Inversion Enabled
+ [0] RX Enable
+ [1] TX Enable
+ [2] RX Data
+ [3] TX Data
+
+**/
+VOID
+GPIOSetInvRxTx (
+ IN UINT32 Community,
+ IN UINT32 PinNum,
+ IN UINT8 InvRxTxValue
+ );
+
+/**
+ Function to get current the Invert Rx/Tx Data and Rx/Tx Enable configuration of specified pin in the community
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+
+ @retval InvRxTxValue 0-No Inversion, 1-Inversion Enabled
+ [0] RX Enable
+ [1] TX Enable
+ [2] RX Data
+ [3] TX Data
+**/
+UINT8
+EFIAPI
+GPIOGetInvRxTx (
+ IN UINT32 Community,
+ IN UINT32 PinNum
+ );
+
+/**
+ Function to configure the interrupt line and type for specified pin in the community
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+ @param[in] LineNum 0 - Interrupt Line 0
+ 1 - Interrupt Line 1
+
+ 15 = Interrupt Line 15
+ @param[in] Type Type of interrrupt
+ 0 = Interrupt/Wake Disable (Disabled and no Pad State toggles trigger the Wake/Interrupt logic)
+ 1 = Falling Edge Detect Interrupt/Wake
+ 2 = Rising Edge Detect Interrupt/Wake
+ 3 = Falling or Rising Edge Detect Interrupt/Wake
+ 4 = Level Interrupt/Wake (Bypass edge detect logic and Pad state is directly toggling the Wake/Interrupt logic)
+**/
+VOID
+ConfigureGpioInt (
+ IN UINT32 Community,
+ IN UINT32 PinNum,
+ IN UINT32 LineNum,
+ IN UINT8 Type
+ );
+
+/**
+ Function to lock the pad of specified Pin
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+ @param[in] Enable 1-Lock,0-UnLock
+
+**/
+VOID
+LockUnlockGPIOPin (
+ IN UINT32 Community,
+ IN UINT32 PinNum,
+ IN BOOLEAN Enable
+ );
+
+/**
+ Function to Read the Pad Write Lock status
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+
+ @retval Boolean 1-Locked,0-Unlocked
+**/
+BOOLEAN
+EFIAPI
+GetPinPadLockStatus (
+ IN UINT32 Community,
+ IN UINT32 PinNum
+ );
+
+/**
+ Function to Get the current interrupt configure for specified pin in the community
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] PinNum Pin number
+ @param[out] LineNum Interrupt line number refer Int_Select from PlatfromInfo.h
+ 0 = Interrupt Line 0
+ 1 = Interrupt Line 1
+
+ 15 = Interrupt Line 15
+ @param[out] Type Type of interrrupt
+ 0 = Interrupt/Wake Disable (Disabled and no Pad State toggles trigger the Wake/Interrupt logic)
+ 1 = Falling Edge Detect Interrupt/Wake
+ 2 = Rising Edge Detect Interrupt/Wake
+ 3 = Falling or Rising Edge Detect Interrupt/Wake
+ 4 = Level Interrupt/Wake (Bypass edge detect logic and Pad state is directly toggling the Wake/Interrupt logic)
+ 4> Unsupported value
+**/
+VOID
+GetGpioIntConfig (
+ IN UINT32 Community,
+ IN UINT32 PinNum,
+ IN OUT UINT8 *LineNum,
+ IN OUT UINT8 *IntType
+ );
+
+/**
+ Set particular GPIO pin as SMI / SCI
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] IntSel Selected interrupt number to rout
+ @param[in] Type Configure SMI / SCI ?
+
+**/
+VOID
+GpioGPEConfig (
+ IN UINT32 Community,
+ IN UINT32 IntSel,
+ IN UINT8 Type
+ );
+
+/**
+ Set particular GPIO Wake Cable
+
+ @param[in] Community NORTH-0x01
+ EAST-0x02
+ SOUTH_EAST-0x03
+ SOUTH_WEST-0x04
+ @param[in] CHV_PAD_MISC Wake capable mask details
+**/
+VOID
+ConfigureGPIOWake (
+ IN UINT32 community,
+ IN CHV_PAD_MISC Pad_misc
+ );
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PchPciExpressHelpersLib.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PchPciExpressHelpersLib.h new file mode 100644 index 0000000000..c0937c8cf1 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PchPciExpressHelpersLib.h @@ -0,0 +1,272 @@ +/** @file
+ Header file for PCH PCI Express helpers library
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_PCI_EXPRESS_HELPERS_LIB_H_
+#define _PCH_PCI_EXPRESS_HELPERS_LIB_H_
+
+//
+// Function prototypes
+//
+/**
+ Find the Offset to a given Capabilities ID
+ CAPID list:
+ 0x01 = PCI Power Management Interface
+ 0x04 = Slot Identification
+ 0x05 = MSI Capability
+ 0x10 = PCI Express Capability
+
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] Function Pci Function Number
+ @param[in] CapId CAPID to search for
+
+ @retval 0 CAPID not found
+ @retval Other CAPID found, Offset of desired CAPID
+**/
+UINT8
+PcieFindCapId (
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT8 CapId
+ );
+
+/**
+ Search and return the offset of desired Pci Express Capability ID
+ CAPID list:
+ 0x0001 = Advanced Error Rreporting Capability
+ 0x0002 = Virtual Channel Capability
+ 0x0003 = Device Serial Number Capability
+ 0x0004 = Power Budgeting Capability
+
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] Function Pci Function Number
+ @param[in] CapId Extended CAPID to search for
+
+ @retval 0 CAPID not found
+ @retval Other CAPID found, Offset of desired CAPID
+**/
+UINT16
+PcieFindExtendedCapId (
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT16 CapId
+ );
+
+/**
+ Map a TC to VC0 for port and endpoint
+
+ @param[in] Bus1 The bus number of the port
+ @param[in] Device1 The device number of the port
+ @param[in] Function1 The function number of the port
+ @param[in] Bus2 The bus number of the endpoint
+ @param[in] Device2 The device number of the endpoint
+ @param[in] TCx The TC number
+
+ @exception EFI_UNSUPPORTED Unsupported operation.
+ @retval EFI_SUCCESS Successfully completed.
+**/
+EFI_STATUS
+PcieMapTcxVc0 (
+ IN UINT8 Bus1,
+ IN UINT8 Device1,
+ IN UINT8 Function1,
+ IN UINT8 Bus2,
+ IN UINT8 Device2,
+ IN UINT8 TCx
+ );
+
+/**
+ Set Common clock to Root port and Endpoint PCI device
+
+ @param[in] Bus1 Root port Pci Bus Number
+ @param[in] Device1 Root port Pci Device Number
+ @param[in] Function1 Root port Pci Function Number
+ @param[in] Bus2 Endpoint Pci Bus Number
+ @param[in] Device2 Endpoint Pci Device Number
+
+ @exception EFI_UNSUPPORTED Unsupported operation.
+ @retval EFI_SUCCESS VC mapping correctly initialized
+**/
+EFI_STATUS
+PcieSetCommonClock (
+ IN UINT8 Bus1,
+ IN UINT8 Device1,
+ IN UINT8 Function1,
+ IN UINT8 Bus2,
+ IN UINT8 Device2
+ );
+
+/**
+ This function enables the CLKREQ# PM on all the end point functions
+
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] RootFunction Rootport Function Number
+
+**/
+VOID
+PcieSetClkreq (
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 RootFunction
+ );
+
+/**
+ This function get or set the Max Payload Size on all the end point functions
+
+ @param[in] EndPointBus The Bus Number of the Endpoint
+ @param[in] EndPointDevice The Device Number of the Endpoint
+ @param[in] MaxPayload The Max Payolad Size of the root port
+ @param[in] Operation True: Set the Max Payload Size on all the end point functions
+ False: Get the Max Payload Size on all the end point functions
+
+ @retval EFI_SUCCESS Successfully completed.
+**/
+EFI_STATUS
+PcieMaxPayloadSize (
+ IN UINT8 EndPointBus,
+ IN UINT8 EndPointDevice,
+ IN OUT UINT16 *MaxPayload,
+ IN BOOLEAN Operation
+ );
+
+/**
+ This function disable the forwarding of EOI messages unless it discovers
+ an IOAPIC behind this root port.
+
+ @param[in] RootBus The Bus Number of the root port
+ @param[in] RootDevice The Device Number of the root port
+ @param[in] RootFunction The Function Number of the root port
+ @param[in] EndPointBus The Bus Number of the Endpoint
+ @param[in] EndPointDevice The Device Number of the Endpoint
+
+ @exception EFI_UNSUPPORTED Unsupported operation.
+ @retval EFI_SUCCESS Successfully completed.
+**/
+EFI_STATUS
+PcieSetEoiFwdDisable (
+ IN UINT8 RootBus,
+ IN UINT8 RootDevice,
+ IN UINT8 RootFunction,
+ IN UINT8 EndPointBus,
+ IN UINT8 EndPointDevice
+ );
+
+/**
+ This function performs the Power Management settings for root port and downstream device
+
+ @param[in] RootBus Pci Bus Number of the root port
+ @param[in] RootDevice Pci Device Number of the root port
+ @param[in] RootFunction Pci Function Number of the root port
+ @param[in] RootPortAspm Root port Aspm configuration
+ @param[in] NumOfDevAspmOverride Number of Device specific ASPM policy override items
+ @param[in] DevAspmOverride Pointer to array of Device specific ASPM policy override items
+ @param[in] TempBusNumberMin Minimal temp bus number that can be assigned to the root port (as secondary
+ bus number) and its down stream switches
+ @param[in] TempBusNumberMax Maximal temp bus number that can be assigned to the root port (as subordinate
+ bus number) and its down stream switches
+ @param[in] NumOfDevltrOverride Number of Device specific LTR override items
+ @param[in] DevLtrOverride Pointer to array of Device specific LTR policy override items
+ @param[in] PchPwrOptPcie Pcie Power Optimizer Configuration
+ @param[in,out] L1SubstatesSupported L1 substates supported on the root port
+ @param[in] L1SubstatesConfig L1 substates configurations on the root port
+**/
+EFI_STATUS
+PcieSetPm (
+ IN UINT8 RootBus,
+ IN UINT8 RootDevice,
+ IN UINT8 RootFunction,
+ IN PCH_PCI_EXPRESS_ASPM_CONTROL RootPortAspm,
+ IN UINT8 NumOfDevAspmOverride,
+ IN PCH_PCIE_DEVICE_ASPM_OVERRIDE *DevAspmOverride,
+ IN UINT8 TempBusNumberMin,
+ IN UINT8 TempBusNumberMax,
+ IN UINT8 NumOfDevltrOverride,
+ IN PCH_PCIE_DEVICE_LTR_OVERRIDE *DevLtrOverride,
+ IN PCH_PCIE_PWR_OPT *PchPwrOptPcie,
+ IN OUT BOOLEAN *L1SubstatesSupported,
+ IN PCH_PCIE_EXPRESS_L1SUBSTATES_CONTROL L1SubstatesConfig
+ );
+
+/**
+ This function checks if the root port and downstream device support Clkreq per port, ASPM L1 and L1 substates
+
+ @param[in] RootBus Pci Bus Number of the root port
+ @param[in] RootDevice Pci Device Number of the root port
+ @param[in] RootFunction Pci Function Number of the root port
+ @param[in] RootPortAspm Root port Aspm configuration
+ @param[in] NumOfDevAspmOverride Number of Device specific ASPM policy override items
+ @param[in] DevAspmOverride Pointer to array of Device specific ASPM policy override items
+ @param[in] TempBusNumberMin Minimal temp bus number that can be assigned to the root port (as secondary
+ bus number) and its down stream switches
+ @param[in] TempBusNumberMax Maximal temp bus number that can be assigned to the root port (as subordinate
+ bus number) and its down stream switches
+ @param[in] NumOfDevLtrOverride Number of Device specific LTR override items
+ @param[in] DevLtrOverride Pointer to array of Device specific LTR policy override items
+ @param[in] PchPwrOptPcie Pcie Power Optimizer Configuration
+ @param[in,out] L1SubstatesSupported Flag to indicate if L1 Substates are supported
+ @param[in] L1SubstatesConfig L1 Substates configuration
+ @param[in] PolicyRevision Revision of the policy
+ @param[in,out] AspmVal Aspm value for both rootport and end point devices
+ @param[in,out] ClkreqPerPortSupported Clkreq support for both rootport and endpoint devices
+ @retval EFI_SUCCESS The function completed successfully
+ @exception EFI_UNSUPPORTED The pointer to the Port PCI Express Capability Structure is not found
+**/
+EFI_STATUS
+PcieCheckPmConfig (
+ IN UINT8 RootBus,
+ IN UINT8 RootDevice,
+ IN UINT8 RootFunction,
+ IN PCH_PCI_EXPRESS_ASPM_CONTROL RootPortAspm,
+ IN UINT8 NumOfDevAspmOverride,
+ IN PCH_PCIE_DEVICE_ASPM_OVERRIDE *DevAspmOverride,
+ IN UINT8 TempBusNumberMin,
+ IN UINT8 TempBusNumberMax,
+ IN UINT8 NumOfDevLtrOverride,
+ IN PCH_PCIE_DEVICE_LTR_OVERRIDE *DevLtrOverride,
+ IN PCH_PCIE_PWR_OPT *PchPwrOptPcie,
+ IN OUT BOOLEAN *L1SubstatesSupported,
+ IN PCH_PCIE_EXPRESS_L1SUBSTATES_CONTROL L1SubstatesConfig,
+ IN OUT UINT16 *AspmVal,
+ IN OUT BOOLEAN *ClkreqPerPortSupported
+ );
+
+/**
+ Initializes the root port and its down stream devices
+
+ @param[in] RootPortBus Pci Bus Number of the root port
+ @param[in] RootPortDevice Pci Device Number of the root port
+ @param[in] RootPortFunc Pci Function Number of the root port
+ @param[in] TempBusNumberMin Minimal temp bus number that can be assigned to the root port (as secondary
+ bus number) and its down stream switches
+ @param[in] TempBusNumberMax Maximal temp bus number that can be assigned to the root port (as subordinate
+ bus number) and its down stream switches
+
+ @retval EFI_SUCCESS Successfully completed
+ @retval EFI_NOT_FOUND Can not find device.
+**/
+EFI_STATUS
+PchPcieInitRootPortDownstreamDevices (
+ IN UINT8 RootPortBus,
+ IN UINT8 RootPortDevice,
+ IN UINT8 RootPortFunc,
+ IN UINT8 TempBusNumberMin,
+ IN UINT8 TempBusNumberMax
+ );
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PchPlatformLib.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PchPlatformLib.h new file mode 100644 index 0000000000..229cdcfd84 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PchPlatformLib.h @@ -0,0 +1,251 @@ +/** @file
+ Header file for PchPlatform Lib.
+
+ Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_PLATFORM_LIB_H_
+#define _PCH_PLATFORM_LIB_H_
+
+//
+// Timeout value used when Sending / Receiving messages.
+// NOTE: this must cover the longest possible wait time
+// between message being sent and response being available.
+// e.g. Virtual function readiness might take some time.
+//
+
+/**
+ Delay for at least the request number of microseconds.
+ This function would be called by runtime driver, please do not use any MMIO marco here.
+
+ @param[in] Microseconds Number of microseconds to delay.
+
+**/
+VOID
+EFIAPI
+PchPmTimerStall (
+ IN UINTN Microseconds
+ );
+
+/**
+ Check whether SPI is in descriptor mode
+
+ @param[in] SpiBase The PCH Spi Base Address
+
+ @retval TRUE SPI is in descriptor mode
+ @retval FALSE SPI is not in descriptor mode
+**/
+BOOLEAN
+EFIAPI
+PchIsSpiDescriptorMode (
+ IN UINTN SpiBase
+ );
+
+/**
+ Return SoC stepping type
+
+ @retval SOC_STEPPING SoC stepping type
+**/
+SOC_STEPPING
+EFIAPI
+SocStepping (
+ VOID
+ );
+
+/**
+Return SoC package type
+
+@retval SOC_PACKAGE SoC package type
+**/
+SOC_PACKAGE
+EFIAPI
+GetSocPackageType (
+ VOID
+ );
+
+/**
+ Determine if PCH is supported
+
+ @retval TRUE PCH is supported
+ @retval FALSE PCH is not supported
+**/
+BOOLEAN
+IsPchSupported (
+ VOID
+ );
+
+/**
+ This function can be called to enable/disable Alternate Access Mode
+
+ @param[in] IlbBase The PCH ILB Base Address
+ @param[in] AmeCtrl If TRUE, enable Alternate Access Mode.
+ If FALSE, disable Alternate Access Mode.
+
+**/
+VOID
+EFIAPI
+PchAlternateAccessMode (
+ IN UINTN IlbBase,
+ IN BOOLEAN AmeCtrl
+ );
+
+/**
+ Write DWord data to extended IOSF-SB register block
+
+ @param[in] PortId Port ID of the target IOSF-SB block
+ @param[in] Register Register of the target IOSF-SB block
+ @param[in] Value Value to be written
+ @param[in] WriteOpCode Write Op Code
+ @param[in] Bar BAR
+ @param[in] Device Device Number
+ @param[in] Function Function Number
+
+**/
+VOID
+PchMsgBusWriteEx32 (
+ IN UINT8 PortId,
+ IN UINT32 Register,
+ IN UINT32 Value,
+ IN UINT8 WriteOpCode,
+ IN UINT8 Bar, OPTIONAL
+ IN UINT8 Device, OPTIONAL
+ IN UINT8 Function OPTIONAL
+ );
+
+/**
+ Write DWord data to IOSF-SB register block
+
+ @param[in] PortId Port ID of the target IOSF-SB block
+ @param[in] Register Register of the target IOSF-SB block
+ @param[in] Value Value to be written
+ @param[in] WriteOpCode Write Op Code
+
+**/
+VOID
+PchMsgBusWrite32 (
+ IN UINT8 PortId,
+ IN UINT32 Register,
+ IN UINT32 Value,
+ IN UINT8 WriteOpCode
+ );
+
+/**
+ Read DWord data from extended IOSF-SB register block
+
+ @param[in] PortId Port ID of the target IOSF-SB block
+ @param[in] Register Register of the target IOSF-SB block
+ @param[in] ReadOpCode Read Op Code
+ @param[in] Bar BAR
+ @param[in] Device Device Number
+ @param[in] Function Function Number
+
+ @retval Data32 Value to be read.
+**/
+UINT32
+PchMsgBusReadEx32 (
+ IN UINT8 PortId,
+ IN UINT32 Register,
+ IN UINT8 ReadOpCode,
+ IN UINT8 Bar, OPTIONAL
+ IN UINT8 Device, OPTIONAL
+ IN UINT8 Function OPTIONAL
+ );
+
+/**
+ Read DWord data from IOSF-SB register block
+
+ @param[in] PortId Port ID of the target IOSF-SB block
+ @param[in] Register Register of the target IOSF-SB block
+ @param[in] ReadOpCode Read Op Code
+
+ @retval Data32 Value to be read.
+**/
+UINT32
+PchMsgBusRead32 (
+ IN UINT8 PortId,
+ IN UINT32 Register,
+ IN UINT8 ReadOpCode
+ );
+
+/**
+ Read-modify-write DWord data from extended IOSF-SB register block
+
+ @param[in] PortId Port ID of the target IOSF-SB block
+ @param[in] Register Register of the target IOSF-SB block
+ @param[in] AndData Value to be ANDed
+ @param[in] OrData Value to be ORed
+ @param[in] ReadOpCode Read Op Code
+ @param[in] WriteOpCode Write Op Code
+ @param[in] Bar BAR
+ @param[in] Device Device Number
+ @param[in] Function Function Number
+
+ @retval EFI_SUCCESS Successfully completed.
+**/
+EFI_STATUS
+EFIAPI
+PchMsgBusAndThenOrEx32 (
+ IN UINT8 PortId,
+ IN UINT32 Register,
+ IN UINT32 AndData,
+ IN UINT32 OrData,
+ IN UINT8 ReadOpCode,
+ IN UINT8 WriteOpCode,
+ IN UINT8 Bar, OPTIONAL
+ IN UINT8 Device, OPTIONAL
+ IN UINT8 Function OPTIONAL
+ );
+
+/**
+ Read-modify-write DWord data from IOSF-SB register block
+
+ @param[in] PortId Port ID of the target IOSF-SB block
+ @param[in] Register Register of the target IOSF-SB block
+ @param[in] AndData Value to be ANDed
+ @param[in] OrData Value to be ORed
+ @param[in] ReadOpCode Read Op Code
+ @param[in] WriteOpCode Write Op Code
+
+ @retval EFI_SUCCESS Successfully completed.
+**/
+EFI_STATUS
+EFIAPI
+PchMsgBusAndThenOr32 (
+ IN UINT8 PortId,
+ IN UINT32 Register,
+ IN UINT32 AndData,
+ IN UINT32 OrData,
+ IN UINT8 ReadOpCode,
+ IN UINT8 WriteOpCode
+ );
+
+/**
+ This function can be called to poll for certain value within a time given.
+
+ @param[in] MmioAddress The Mmio Address.
+ @param[in] BitMask Bits to be masked.
+ @param[in] BitValue Value to be polled.
+ #param[in] DelayTime Delay time in terms of 100 micro seconds.
+
+ @retval EFI_SUCCESS Successfully polled the value.
+ @retval EFI_TIMEOUT Timeout while polling the value.
+**/
+EFI_STATUS
+EFIAPI
+PchMmioPoll32 (
+ IN UINTN MmioAddress,
+ IN UINT32 BitMask,
+ IN UINT32 BitValue,
+ IN UINT16 DelayTime
+ );
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PchSmbusLibrary.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PchSmbusLibrary.h new file mode 100644 index 0000000000..c4db4fe0fb --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PchSmbusLibrary.h @@ -0,0 +1,41 @@ +/** @file
+ Header file for Pch Smbus Lib.
+
+ Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_SMBUS_LIBRARY_H_
+#define _PCH_SMBUS_LIBRARY_H_
+
+/**
+ This function provides a standard way to execute Smbus sequential
+ I2C Read. This function allows the PCH to perform block reads to
+ certain I2C devices, such as serial E2PROMs. Typically these data
+ bytes correspond to an offset (address) within the serial memory
+ chips.
+
+ @param[in] SmBusAddress Address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param[out] Buffer Pointer to the buffer to store the bytes read
+ from the SMBUS
+ @param[out] Status eturn status for the executed command.
+
+ @retval UINTN The number of bytes read
+**/
+UINTN
+EFIAPI
+SmBusSeqI2CRead (
+ IN UINTN SmBusAddress,
+ OUT VOID *Buffer,
+ OUT RETURN_STATUS * Status OPTIONAL
+ );
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicMountVillePlus.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicMountVillePlus.h new file mode 100644 index 0000000000..4631f5d4d2 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicMountVillePlus.h @@ -0,0 +1,178 @@ +/** @file
+
+ Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PMIC_REG_WC_H_
+#define _PMIC_REG_WC_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/PmicLib.h>
+#include <Library/PcdLib.h>
+
+#include "PmicReg.h"
+#include "ChvAccess.h"
+#include <Guid/PlatformInfo.h>
+
+UINT8
+EFIAPI
+MtvPlusPmicRead8 (
+ IN UINT8 Register
+ );
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicWrite8 (
+ IN UINT8 Register,
+ IN UINT8 Value
+ );
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicThermInit (void);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicGpioInit (void);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicIntrInit (void);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicBcuInit (void);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicMiscInit (void);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicPage0Init (void *Profile);
+
+UINT8
+EFIAPI
+MtvPlusPmicRead8_page0 (
+ IN UINT8 Register
+ );
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicWrite8_page0 (
+ IN UINT8 Register,
+ IN UINT8 Value
+ );
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicVbusControl (BOOLEAN bTurnOn);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicVhostControl (BOOLEAN bTurnOn);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicGetDevID (UINT8 *DevId, UINT8 *RevId);
+
+UINT16
+EFIAPI
+MtvPlusPmicGetBATID (void);
+
+UINT8
+EFIAPI
+MtvPlusPmicGetBoardID(void);
+
+UINT8
+EFIAPI
+MtvPlusPmicGetMemCfgID(void);
+
+UINT8
+EFIAPI
+MtvPlusPmicGetFABID(void);
+
+UINT16
+EFIAPI
+MtvPlusPmicGetVBAT (void);
+
+BOOLEAN
+EFIAPI
+MtvPlusPmicIsACOn (void);
+
+BOOLEAN
+EFIAPI
+MtvPlusPmicIsPwrBtnPressed(void);
+
+BOOLEAN
+EFIAPI
+MtvPlusPmicIsUIBtnPressed(void);
+
+UINT16
+EFIAPI
+MtvPlusPmicGetResetCause (void);
+
+VOID
+EFIAPI
+MtvPlusPmicClearResetCause (void);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicGetWakeCause (IN OUT UINT8 *WakeCause);
+
+VOID
+EFIAPI
+MtvPlusPmicClearWakeCause (void);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicDebugRegDump (void);
+
+BOOLEAN
+EFIAPI
+MtvPlusPmicIsUsbConnected (void);
+
+BOOLEAN
+EFIAPI
+MtvPlusPmicIsBatOn (void);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicSetVDDQ (void);
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicGpioToggleForLpcConfig(void);
+
+VOID
+MtvPlusPmicForceOffModem (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicBatchRegisterInit (
+ IN RegInit_st *RegInit,
+ IN UINT32 length
+ );
+
+EFI_STATUS
+EFIAPI
+MtvPlusPmicSetVIDDecayWA (void);
+
+VOID
+MtvPlusPmicProgramPunitPwrConfigRegisters (
+ VOID
+ );
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicNVMProvision.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicNVMProvision.h new file mode 100644 index 0000000000..5737a89ecb --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicNVMProvision.h @@ -0,0 +1,193 @@ +/** @file
+
+ Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PMICNVMPROVISION_H_
+#define PMICNVMPROVISION_H_
+
+#define PMIC_PROVISIONING_ASK_USER 0
+#define PMIC_PROVISIONING_PUTS_DEBUG 1
+#define PMIC_PROVISIONING_NEUTERED_FOR_DEBUG 0
+#define PMIC_PROVISIONING_ASK_USER_TIMEOUT 60
+
+// setting below to '1' will print the current nvm content and exit.
+#define NVM_READBACK_ONLY 0
+
+#define NVM_OTP_MAX 2048
+#define NVM_WR_ERR 1
+#define MAGIC_NVM 0xDEADBEEF
+
+// Flags
+#define OTP_WR_ONGOING 0x1 //NVMSTAT0_REG[0]
+#define OTP_PD_ACT 0x2 //NVMSTAT0_REG[1]
+#define OTP_WR_MODE_EN 0x1 //NVMCTRL1_REG[0]
+#define OTP_WR_TRIGGER 0x2 //NVMCTRL1_REG[1]
+#define WRITE_FINISHED_INFO 0x1
+#define WRITE_ONE_CLEAR 0x1
+#define IA_IRQ_ASSERTED 1
+#define NVM_CONTROLLER 0x1
+
+// Register definitions
+#define PMIC_NVMDBUF0 0x1C6
+#define PMIC_NVMDBUF1 0x1C7
+#define PMIC_NVMDBUF2 0x1C8
+#define PMIC_NVMDBUF3 0x1C9
+#define PMIC_NVMDBUF4 0x1CA
+#define PMIC_NVMDBUF5 0x1CB
+#define PMIC_NVMDBUF6 0x1CC
+#define PMIC_NVMDBUF7 0x1CD
+#define PMIC_NVMDBUF8 0x1CE
+#define PMIC_NVMDBUF9 0x1CF
+#define PMIC_NVMDBUF10 0x1D0
+#define PMIC_NVMDBUF11 0x1D1
+#define PMIC_NVMDBUF12 0x1D2
+#define PMIC_NVMDBUF13 0x1D3
+#define PMIC_NVMDBUF14 0x1D4
+#define PMIC_NVMDBUF15 0x1D5
+#define PMIC_NVMDBUF16 0x1D6
+#define PMIC_NVMDBUF17 0x1D7
+#define PMIC_NVMDBUF18 0x1D8
+#define PMIC_NVMDBUF19 0x1D9
+#define PMIC_NVMDBUF20 0x1DA
+#define PMIC_NVMDBUF21 0x1DB
+#define PMIC_NVMDBUF22 0x1DC
+#define PMIC_NVMDBUF23 0x1DD
+#define PMIC_NVMDBUF24 0x1DE
+#define PMIC_NVMDBUF25 0x1DF
+#define PMIC_NVMDBUF26 0x1E0
+#define PMIC_NVMDBUF27 0x1E1
+#define PMIC_NVMDBUF28 0x1E2
+#define PMIC_NVMDBUF29 0x1E3
+#define PMIC_NVMDBUF30 0x1E4
+#define PMIC_NVMDBUF31 0x1E5
+#define PMIC_NVMDBUF32 0x1E6
+#define PMIC_NVMDBUF33 0x1E7
+#define PMIC_NVMCTL0 0x1E8
+#define PMIC_NVMCTL1 0x1E9
+#define PMIC_OTPMRB1 0x1EA
+#define PMIC_OTPMRB0_RD1 0x1ED
+#define PMIC_OTPMRB0_RD2 0x1EE
+#define PMIC_NVMSTAT0 0x1F0
+#define PMIC_NVMUSAGESTATH 0x1F3
+#define PMIC_NVMUSAGESTATL 0x1F4
+
+#define PMIC_ID_REG 0x000 // PMIC_ID_REG: 5E offset 0x00
+#define PMICSPARE00_REG 0x108 // OTP_VERSION: 6E offset 0x08
+#define PMICSPARE01_REG 0x109
+
+#define PMIC_VENDIRQLVL1 0x200
+#define PMIC_NVMVIRQ_REG 0x202 //4E
+
+#define PMIC_NVM_MB_ADDRH_REG 0x1C3 // for read-back
+#define PMIC_NVM_MB_ADDRL_REG 0x1C4 // for read-back
+#define PMIC_NVM_MB_DATA_REG 0x1C5 // for read-back
+
+#define MAX_SECTION_SIZE 34
+#define SECTION_HEADER_SIZE 2
+#define PMIC_PROVISIONING_PUTS_DEBUG 1
+#define PMIC_NVM_FILE_NAME L"PMIC_NVM_payload.bin"
+
+typedef struct
+{
+ UINT16 rstid_msb:2;
+ UINT16 owner:5;
+ UINT16 valid:1;
+ UINT16 sectionLength:5;
+ UINT16 type:1;
+ UINT16 rstid_lsb:2;
+} NVM_SectionHeader_t;
+
+typedef struct
+{
+ UINT32 Magic;
+ UINT16 xlsVersion;
+ UINT16 glueVersion;
+ UINT16 lengthOfPayloadStructure;
+ UINT8 checksum;
+ char nvmDate;
+} NVM_PayLoadHeader_t;
+
+#define MAX_OWNER_TYPE 20
+#define NUM_VALID_RESET_IDS 7
+#define RAW_DATA (1 << 2)
+#define ADDRESS_AUTO_INCREMENT (1 << 1)
+#define ARBITRARY_ADDRESS (1 << 0)
+
+
+// WHC:
+typedef enum
+{
+ Production = 1,
+ TLP1 = 0x2,
+ TLP2 = 0x3,
+ CSSM_Transl_Table = 0x4,
+ SoC_Device_ID2 = 0x6,
+ SoC_Device_ID3 = 0x7,
+ Soc_Device_ID4 = 0x8,
+ SCRATCH = 0x9, //also called "SoC_Device_ID_6"
+ VNN_SVID = 0xA,
+ VNN_DCDC = 0xF,
+ //NVM.sectionOwner.
+ VCC_PHS1_DCDC = 0x18,
+ //NVM.sectionOwner.
+ VCC_PHS2_DCDC = 0x19,
+ //NVM.sectionOwner.
+ VCC_PHS3_DCDC = 0x1A,
+ //NVM.sectionOwner.
+ VCC_PHS4_DCDC = 0x1B,
+ //NVM.sectionOwner.
+ VCC_PHS5_DCDC = 0x1C,
+ //NVM.sectionOwner.
+ VMEM_PHS1_DCDC = 0x1D,
+ //NVM.sectionOwner.
+ VDD2_PHS1_DCDC = 0x1E,
+ //-----
+ SoC_Device_ID_5 = 0x5,
+ VCC0_SVID = 0xB,
+ VCC1_SVID = 0xC,
+ VGG_SVID = 0xD,
+ V_PLT_SVID = 0xE,
+ VCC0_DCDC = 0x10,
+ VCC1_DCDC = 0x11,
+ VGG_DCDC = 0x12,
+ V1P8A_DCDC = 0xB,
+ V1P05A_DCDC = 0x14,
+ V1P15_DCDC = 0x15,
+ VDDQ_DCDC = 0x16,
+ V3P3A_DCDC = 0x17,
+} owner_type_e;
+
+typedef enum
+{
+ Production_ResetID = 0,
+ PMIC_OFF = 0x1,
+ PMIC_OFF_or_COLD_RESET = 0x3,
+ PMIC_OFF_or_COLD_WARM_RESET = 0x7,
+ VRTC_RESET = 0x8,
+ PMIC_OFF_or_TLP1_RESET = 0xC,
+ PMIC_OFF_or_TLP2_RESET = 0xA,
+} rstid_e;
+
+extern UINT32 sendToHostRT(char *, UINT32);
+
+UINT8 Calculate8BitChecksum_16(UINT8 *, UINT16);
+int validatePayload(UINT8, UINT16);
+void disable_OTP_WR_MODE_EN(void);
+UINT8 NVMRead(UINT8, UINT8, UINT16, UINT8 *);
+UINT8 Write_Section(NVM_SectionHeader_t *, UINT8 *);
+UINT32 NVM_ReadBack_and_exit(UINT16);
+UINT32 PmicNVMProvision(UINT8* , UINTN);
+void write_OTP_trigger_flag(void);
+
+#endif /* PMICNVMPROVISION_H_ */
+
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicReg_DollarCove_TI.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicReg_DollarCove_TI.h new file mode 100644 index 0000000000..ba8c6da76c --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicReg_DollarCove_TI.h @@ -0,0 +1,138 @@ +/** @file
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PMIC_REG_TIDC_H_
+#define _PMIC_REG_TIDC_H_
+
+#define BIT00 0x01
+#define BIT01 0x02
+#define BIT02 0x04
+#define BIT03 0x08
+#define BIT04 0x10
+#define BIT05 0x20
+#define BIT06 0x40
+#define BIT07 0x80
+
+#define TIDC_ID 0x00
+#define TIDC_MASK_VENDID (BIT07|BIT06)
+#define TIDC_MASK_MAJREV (BIT05|BIT04|BIT03)
+#define TIDC_MASK_MINREV (BIT02|BIT01|BIT00)
+
+#define TIDC_IRQ_R 0x01
+#define TIDC_MASK_CCEOCAL BIT07 //CC calibration completes IRQ asserted
+#define TIDC_MASK_CCEOCONV BIT06 //CC conversion completes IRQ asserted
+#define TIDC_MASK_VBUSDET BIT05 //VBUS crosses detection threshold (rising or falling) IRQ asserted
+#define TIDC_MASK_VBATLOW BIT04 //VBAT crosses low voltage detection threshold (rising or falling); VBATLOW IRQ asserted
+#define TIDC_MASK_ADCCOMPL BIT02 //ADC conversion complete; ADCCOMPL IRQ asserted
+#define TIDC_MASK_DIETMPWARN BIT01 //Die temp comparator threshold crossed (rising and falling); DIETMPWARN IRQ asserted
+#define TIDC_MASK_PWRBTN BIT00 //Power Button assertion debounce time met (press and release); PWRBTN IRQ asserted
+
+#define TIDC_MIRQ 0x02
+#define TIDC_MASK_MCCEOCAL BIT07 //CC calibration completes IRQ asserted
+#define TIDC_MASK_MCCEOCONV BIT06 //CC conversion completes IRQ asserted
+#define TIDC_MASK_MVBUSDET BIT05 //VBUS crosses detection threshold (rising or falling) IRQ asserted
+#define TIDC_MASK_MVBATLOW BIT04 //VBAT crosses low voltage detection threshold (rising or falling); VBATLOW IRQ asserted
+#define TIDC_MASK_MADCCOMPL BIT02 //ADC conversion complete; ADCCOMPL IRQ asserted
+#define TIDC_MASK_MDIETMPWARN BIT01 //Die temp comparator threshold crossed (rising and falling); DIETMPWARN IRQ asserted
+#define TIDC_MASK_MPWRBTN BIT00 //Power Button assertion debounce time met (press and release); PWRBTN IRQ asserted
+
+#define TIDC_SIRQ 0x03
+#define TIDC_MASK_SCCEOCAL BIT07 //One clock cycle pulse end of Calibration
+#define TIDC_MASK_SCCEOCONV BIT06 //One clock cycle pulse end of Conversion
+#define TIDC_MASK_SVBUSDET BIT05 //VBUS > VBUS_DET
+#define TIDC_MASK_SVBATLOW BIT04 //VBAT < VBAT_LOW
+#define TIDC_MASK_SADCCOMPL BIT02 //ADC is completing a conversion
+#define TIDC_MASK_SDIETMPWARN BIT01 //PMIC die temp monitoring threshold is triggered
+#define TIDC_MASK_SPWRBTN BIT00 //power button release value after 30 ms debounce (non-pressed)
+
+#define TIDC_PBUTTON 0x10
+#define TIDC_MASK_PBDWNTMR (BIT03|BIT02)
+#define TIDC_MASK_PBUPTMR (BIT01|BIT00)
+
+#define TIDC_CHIPCTRL 0x11
+#define TIDC_RSTSRC_R 0x12
+#define TIDC_MASK_PBOFF BIT07 //Power Button override was the shutdown reason
+#define TIDC_MASK_CLDOFF BIT06 //SoC initiated cold off was the shutdown reason
+#define TIDC_MASK_UVLO BIT05 //PMIC UVLO threshold was the shutdown reason
+#define TIDC_MASK_CLDRST BIT04 //Cold reset was the start up reason
+#define TIDC_MASK_GLBRST BIT03 //SoC initiated Global Reset was the start up reason
+#define TIDC_MASK_BATTIN BIT02 //Battery insertion was the start up reason
+#define TIDC_MASK_CHGIN BIT01 //Charger insertion was the start up reason
+#define TIDC_MASK_PBTN BIT00 //Power button was the start up reason
+
+#define TIDC_LOWBATTDET_W 0x17
+#define TIDC_VBATTHR 0x18
+#define TIDC_TMPSNSCFG 0x19
+
+#define TIDC_BUCK1CTRL 0x20
+#define TIDC_BUCK2CTRL 0x21
+#define TIDC_BUCK2SLPEXIT 0x22
+#define TIDC_BUCK2SLEEP 0x23
+#define TIDC_BUCK3CTRL 0x24
+#define TIDC_BUCK3SLPEXIT 0x25
+#define TIDC_BUCK3SLEEP 0x26
+#define TIDC_BUCK4CTRL 0x27
+#define TIDC_BUCK5CTRL 0x28
+#define TIDC_BUCK5VSEL 0x29
+#define TIDC_BUCK5SLPEXIT 0x2A
+#define TIDC_BUCK5SLEEP 0x2B
+#define TIDC_BUCK6CTRL 0x2C
+
+#define TIDC_LDO1CTRL 0x41
+#define TIDC_LDO2CTRL 0x42
+#define TIDC_LDO3CTRL 0x43
+#define TIDC_LDO5CTRL 0x45
+#define TIDC_LDO6CTRL 0x46
+#define TIDC_LDO7CTRL 0x47
+#define TIDC_LDO8CTRL 0x48
+#define TIDC_LDO9CTRL 0x49
+#define TIDC_LDO10CTRL 0x4A
+#define TIDC_LDO11CTRL 0x4B
+#define TIDC_LDO12CTRL 0x4C
+#define TIDC_LDO13CTRL 0x4D
+#define TIDC_LDO14CTRL 0x4E
+
+#define TIDC_ADCCTRL_W 0x50
+#define TIDC_ADCDIETEMPZSE 0x51
+#define TIDC_ADCGPINTHERMGE 0x52
+#define TIDC_ADCVBATZSEGE 0x53
+#define TIDC_VBATHI 0x54
+#define TIDC_VBATLO 0x55
+#define TIDC_MASK_DIETEMPH (BIT01|BIT00)
+
+#define TIDC_DIETEMPHI 0x56
+#define TIDC_DIETEMPLO 0x57
+#define TIDC_BPTHERMHI 0x58
+#define TIDC_MASK_BPTHERMH (BIT01|BIT00)
+#define TIDC_BPTHERMLO 0x59
+
+#define TIDC_GPADCHI 0x5A
+#define TIDC_GPADCLO 0x5B
+
+#define TIDC_CC_CTRL 0x60
+#define TIDC_CC_OFFSETHI 0x61
+#define TIDC_CC_OFFSETLO 0x62
+#define TIDC_CC_ACC_BYTE3 0x63
+#define TIDC_CC_ACC_BYTE2 0x64
+#define TIDC_CC_ACC_BYTE1 0x65
+#define TIDC_CC_ACC_BYTE0 0x66
+#define TIDC_CC_SMPL_BYTE2 0x67
+#define TIDC_CC_SMPL_BYTE1 0x68
+#define TIDC_CC_SMPL_BYTE0 0x69
+#define TIDC_CC_INTG_BYTE1 0x6A
+#define TIDC_CC_INTG_BYTE0 0x6B
+#define TIDC_CC_SWOFFSETH 0x6C
+
+#endif
+
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicReg_DollarCove_XPOWERS.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicReg_DollarCove_XPOWERS.h new file mode 100644 index 0000000000..f23a842235 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicReg_DollarCove_XPOWERS.h @@ -0,0 +1,398 @@ +/** @file
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _DC_X_PMIC_REG_CC_H_
+#define _DC_X_PMIC_REG_CC_H_
+
+#define BIT00 0x01
+#define BIT01 0x02
+#define BIT02 0x04
+#define BIT03 0x08
+#define BIT04 0x10
+#define BIT05 0x20
+#define BIT06 0x40
+#define BIT07 0x80
+
+#define DC_X_PMIC_REG_PWR_SRC_STS 0x00
+#define DC_X_MAST_BAT_CURR_DIR BIT2 //Indication Battery current direction
+#define DC_X_MAST_VBUS_PRESENCE BIT5 //VBUS presence indication
+
+#define DC_X_PMIC_REG_CHARGER_STS 0x01
+#define DC_X_MAST_BAT_PRESENCE BIT5 //Battery presence indication
+
+#define DC_X_PMIC_REG_PUPD_REASON 0x02
+#define DC_X_MAST_PWRBTN_START BIT0 //Power on key was the start up reason
+#define DC_X_MAST_CHR_INERT_START BIT1 //Charger insertion was the start up reason
+#define DC_X_MAST_BAT_INERT_START BIT2 //Battery insertion was the start up reason
+#define DC_X_MAST_SOC_GLOBRST BIT3 //SOC initiated Global Reset was the start up reason
+#define DC_X_MAST_COLDRST BIT4 //Cold reset was the start up reaso
+#define DC_X_MAST_UVLO_SHDN BIT5 //PMIC UVLO threshold was the shutdown reason
+#define DC_X_MAST_SOC_SHDW BIT6 //SOC initiated cold off was the shutdown reason
+#define DC_X_MAST_PWRBTN_SHDW BIT7 //Power on key override was the shutdown reason
+
+#define DC_X_PMIC_REG_IC_TYPC 0x03
+#define PMIC_DEV_MASK_VERSION (BIT05|BIT04)
+#define PMIC_DEV_MASK_VENDER (BIT07|BIT06|BIT03|BIT02|BIT01|BIT00)
+
+#define DC_X_PMIC_REG_DATA_BUFFER_04 0x04
+#define DC_X_PMIC_REG_DATA_BUFFER_05 0x05
+#define DC_X_PMIC_REG_DATA_BUFFER_06 0x06
+#define DC_X_PMIC_REG_DATA_BUFFER_07 0x07
+#define DC_X_PMIC_REG_DATA_BUFFER_08 0x08
+#define DC_X_PMIC_REG_DATA_BUFFER_09 0x09
+#define DC_X_PMIC_REG_DATA_BUFFER_0A 0x0A
+#define DC_X_PMIC_REG_DATA_BUFFER_0B 0x0B
+#define DC_X_PMIC_REG_DATA_BUFFER_0C 0x0C
+#define DC_X_PMIC_REG_DATA_BUFFER_0D 0x0D
+#define DC_X_PMIC_REG_DATA_BUFFER_0E 0x0E
+#define DC_X_PMIC_REG_DATA_BUFFER_0F 0x0F
+#define DC_X_PMIC_REG_DATA_BUFFER_F2 0xF2
+#define DC_X_PMIC_REG_DATA_BUFFER_F4 0xF4
+#define DC_X_PMIC_REG_DATA_BUFFER_FF 0xFF
+
+#define DC_X_PMIC_REG_VR_CTRL_1 0x10
+#define DC_X_PMIC_REG_VR_CTRL_2 0x12
+#define DC_X_MASK_DLDO4_CTRL BIT06 //DLDO4 on©\off control 0©\off; 1©\on
+#define DC_X_MASK_DLDO3_CTRL BIT05 //DLDO3 on©\off control
+#define DC_X_MASK_DLDO2_CTRL BIT04 //DLDO2 on©\off control
+#define DC_X_MASK_DLDO1_CTRL BIT03 //DLDO1 on©\off control
+#define DC_X_MASK_ELDO3_CTRL BIT02 //ELDO3 on©\off control
+#define DC_X_MASK_ELDO2_CTRL BIT01 //ELDO2 on©\off control
+#define DC_X_MASK_ELDO1_CTRL BIT00 //ELDO1 on©\off control
+
+#define DC_X_PMIC_REG_VR_CTRL_3 0x13
+#define DC_X_MASK_ALDO3_CTRL BIT07 //ALDO3 on©\off control 0©\off; 1©\on
+#define DC_X_MASK_ALDO2_CTRL BIT06 //ALDO2 on©\off control
+#define DC_X_MASK_ALDO1_CTRL BIT05 //ALDO1 on©\off control
+#define DC_X_MASK_FLDO3_CTRL BIT04 //FLDO2 on©\off control
+#define DC_X_MASK_FLDO2_CTRL BIT03 //FLDO1 on©\off control
+#define DC_X_MASK_FLDO1_CTRL BIT02 //FLDO3 on©\off control
+
+#define DC_X_PMIC_REG_VR_CTRL_SYNC 0x14
+#define DC_X_MASK_BUCK5_POLY_PHASE BIT06 //BUCK5 poly©\phase control
+#define DC_X_MASK_BUCK3_$_POLY_PHASE BIT05 //BUCK 3 & 4 change to poly©\phase Buck
+#define DC_X_MASK_BUCK235_VRUN_VSLP BIT04 //Select the BUCK2/ 3 /5 Vrun register or Vsleep register
+#define DC_X_MASK_COLD_RESET_CONDITION BIT03 //If SLP_S0IX_B go high and PLTRST_B status is low for 512ms, PMIC will do a cold reset or not (Reset: power on reset)
+#define DC_X_MASK_COLD_RESET_ENABLE BIT02 //Cold reset Enable . All power rails power down and then power up,64ms delay
+#define DC_X_MASK_POWER_CONTROL_SEL BIT01 //1©\select buffer register, output value of control register to buffer
+#define DC_X_MASK_OUTPUT_BUFFER BIT00 //1©\outport to control register from buffer Bit[1:0], self clear to 0 after output
+
+#define DC_X_PMIC_REG_VR_CTRL_DLDO1 0x15
+#define DC_X_PMIC_REG_VR_CTRL_DLDO2 0x16
+#define DC_X_PMIC_REG_VR_CTRL_DLDO3 0x17
+#define DC_X_PMIC_REG_VR_CTRL_DLDO4 0x18
+#define DC_X_PMIC_REG_VR_CTRL_ELDO1 0x19
+#define DC_X_PMIC_REG_VR_CTRL_ELDO2 0x1A
+#define DC_X_PMIC_REG_VR_CTRL_ELDO3 0x1B
+#define DC_X_MASK_ELDO_VOL_18 (BIT04|BIT02|BIT01)
+
+#define DC_X_PMIC_REG_VR_CTRL_FLDO1 0x1C
+#define DC_X_PMIC_REG_VR_CTRL_FLDO2_3 0x1D
+
+#define DC_X_PMIC_REG_VR_CTRL_BUCK6 0x20
+#define DC_X_PMIC_REG_VR_CTRL_BUCK5 0x21
+#define DC_X_PMIC_REG_VR_CTRL_BUCK1 0x23
+#define DC_X_PMIC_REG_VR_CTRL_BUCK4 0x24
+#define DC_X_MASK_DVM_STATUS BIT07 //DVM finished or not status bit 1: finished
+#define DC_X_MASK_VOL_8BIT_6_0 (BIT00|BIT01|BIT02|BIT03|BIT04|BIT05|BIT06) //voltage setting Bit 6©\0 0.80©\1.12V£º10mV/step 1.14©\1.84V£º20mV/step
+
+#define DC_X_PMIC_REG_VR_CTRL_BUCK3 0x25
+#define DC_X_PMIC_REG_VR_CTRL_BUCK2 0x26
+#define DC_X_PMIC_REG_VR_BUCK_RAMP_CTRL 0x27
+#define DC_X_MASK_BUCK2_DVM_CTRL BIT07 //BUCK2 DVM on©\off control
+#define DC_X_MASK_BUCK3_DVM_CTRL BIT06 //BUCK3 DVM on©\off control
+#define DC_X_MASK_BUCK4_DVM_CTRL BIT05 //BUCK4 DVM on©\off control
+#define DC_X_MASK_BUCK1_DVM_CTRL BIT04 //BUCK1 DVM on©\off control
+#define DC_X_MASK_BUCK5_DVM_CTRL BIT02 //BUCK5 DVM on©\off control
+#define DC_X_MASK_RSMRST_B_LOW BIT01 //RSMRST_B drive low when ALDO3 less than 85% or not control
+#define DC_X_MASK_DRAMPWROK BIT00 //DRAMPWROK drive low when FLDO3 less than 85% or not control
+
+#define DC_X_PMIC_REG_ALDO1_VOL_CTRL 0x28
+#define DC_X_MASK_ALDO_VOL_30 (BIT04|BIT02|BIT01|BIT00)
+#define DC_X_MASK_ALDO_VOL_29 (BIT04|BIT02|BIT01)
+#define DC_X_MASK_ALDO_VOL_28 (BIT04|BIT02|BIT00)
+
+#define DC_X_PMIC_REG_ALDO2_VOL_CTRL 0x29
+#define DC_X_PMIC_REG_ALDO3_VOL_CTRL 0x2A
+#define DC_X_PMIC_REG_BC_GBL_DETECT 0x2C
+#define DC_X_PMIC_REG_BC_VBUS_CTRL_STS 0x2D
+#define DC_X_PMIC_REG_BC_USB_STATUS 0x2E
+#define DC_X_PMIC_REG_BC_DETECT_STS 0x2F
+
+#define DC_X_PMIC_REG_VBUS_PATH_CTRL 0x30
+#define DC_X_PMIC_REG_WAKE_UP_CTRL 0x31
+#define DC_X_PMIC_REG_PD_BAT_CHGLED 0x32
+#define DC_X_MASK_BAT_DETECT BIT06 //Battery detection function control: 0©\disable; 1©\enable
+#define DC_X_MASK_CHGLED_PIN (BIT05|BIT04) //CHGLED pin control
+#define DC_X_MASK_CHGLED_PIN_HIZ 0x0 //00: Hi-Z
+#define DC_X_MASK_CHGLED_PIN_05HZ 0x10 //01: 25% 0.5Hz toggle
+#define DC_X_MASK_CHGLED_PIN_2HZ 0x20 //10: 25% 2Hz toggle
+#define DC_X_MASK_CHGLED_PIN_LOW 0x30 //11: drive low
+#define DC_X_MASK_CHGLED_PIN_CTRL BIT03 //0: controlled by REG 32H[5:4]
+#define DC_X_MASK_DELAY_TIME (BIT01|BIT00) //control bit for Delay time between PWROK signal and power good time
+#define DC_X_MASK_DELAY_TIME_8MS 0x0
+#define DC_X_MASK_DELAY_TIME_16MS 0x1
+#define DC_X_MASK_DELAY_TIME_32MS 0x2
+#define DC_X_MASK_DELAY_TIME_64MS 0x3
+
+#define DC_X_PMIC_REG_CHARGER_CTRL_1 0x33
+#define DC_X_PMIC_REG_CHARGER_CTRL_2 0x34
+#define DC_X_MASK_PRE_CHARGE_TIME (BIT07|BIT06) //Pre©\charge Timer length setting 1:0
+#define DC_X_MASK_PRE_CHARGE_TIME_40MIN 0x0 //40 minutes
+#define DC_X_MASK_PRE_CHARGE_TIME_50MIN BIT06 //50 minutes
+#define DC_X_MASK_PRE_CHARGE_TIME_60MIN BIT07 //60 minutes
+#define DC_X_MASK_PRE_CHARGE_TIME_70MIN (BIT07|BIT06) //70 minutes
+#define DC_X_MASK_CRG_ON_OFF BIT05 //Charger output turn off or not when charging is end & the PMIC is on state 1: do not turn off
+#define DC_X_MASK_CHGLED_SEL BIT04 //CHGLED Type select when REG 32_[3] is 0 1: Type B
+#define DC_X_MASK_FAST_CHARGE_TIME (BIT01|BIT00) //Fast charge maximum time setting1:0
+#define DC_X_MASK_FAST_CHARGE_TIME_6HRS 0x0 //6 hours
+#define DC_X_MASK_FAST_CHARGE_TIME_8HRS 0x1 //8 hours
+#define DC_X_MASK_FAST_CHARGE_TIME_10HRS 0x2 //10 hours
+#define DC_X_MASK_FAST_CHARGE_TIME_12HRS 0x3 //12 hours
+
+#define DC_X_PMIC_REG_CHARGER_CTRL_3 0x35
+#define DC_X_PMIC_REG_POK_SETTING 0x36
+#define DC_X_MASK_ONLEVEL (BIT06|BIT07) //ONLEVEL setting
+#define DC_X_MASK_ONLEVEL_128MS 0 // 128ms
+#define DC_X_MASK_ONLEVEL_1S BIT06 // 1s
+#define DC_X_MASK_ONLEVEL_2S BIT07 // 2s
+#define DC_X_MASK_ONLEVEL_3S (BIT06|BIT07) // 3s
+#define DC_X_MASK_IRQLEVEL (BIT04|BIT05) //IRQLEVEL setting
+#define DC_X_MASK_IRQLEVEL_1S 0 //1s
+#define DC_X_MASK_IRQLEVEL_1_5S BIT04 //1.5s
+#define DC_X_MASK_IRQLEVEL_2S BIT05 //2s
+#define DC_X_MASK_IRQLEVEL_2_5S (BIT04|BIT05) //2.5s
+#define DC_X_MASK_OFFEVEL (BIT00|BIT01) //OFFLEVEL setting
+#define DC_X_MASK_OFFEVEL_4S 0
+#define DC_X_MASK_OFFEVEL_6S 1
+#define DC_X_MASK_OFFEVEL_8S 2
+#define DC_X_MASK_OFFEVEL_10S 3
+#define DC_X_MASK_AUTO_ON_OFFEVEL BIT02
+#define DC_X_MASK_SHDW_OFFEVEL BIT03 //Enable bit of the function which will shut down the PMIC when POK is larger than OFFLEVEL
+
+#define DC_X_PMIC_REG_POK_POFF_SETTING 0x37
+#define DC_X_MASK_POK_POFF (BIT00|BIT01|BIT02) //Power off activity time setting
+#define DC_X_MASK_POK_POFF_0S 0
+#define DC_X_MASK_POK_POFF_10S 1
+#define DC_X_PMIC_REG_VLTF_CHARGE_SETTING 0x38
+#define DC_X_PMIC_REG_VHTF_CHARGE_SETTING 0x39
+#define DC_X_PMIC_REG_BUCK_FREQ_SETTING 0x3B
+#define DC_X_PMIC_REG_VLTF_WORK_SETTING 0x3C
+#define DC_X_PMIC_REG_VHTF_WORK_SETTING 0x3D
+
+#define DC_X_PMIC_REG_IRQ_CTRL_1 0x40
+#define DC_X_MASK_VBUS_HI_TO_LOW_EN BIT02 //VBUS from high go low IRQ enable
+#define DC_X_MASK_VBUS_LOW_TO_HI_EN BIT03 //VBUS from low go high IRQ enable
+#define DC_X_MASK_VBUS_OV_VOL_EN BIT04 //VBUS over voltage IRQ enable
+#define DC_X_MASK_VBUS_HI_TO_LOW_EN_1 BIT05 //VBUS from high go low IRQ enable
+#define DC_X_MASK_VBUS_LOW_TO_HI_EN_1 BIT06 //VBUS from low go high IRQ enable
+#define DC_X_MASK_VBUS_OV_VOL_EN_1 BIT07 //VBUS over voltage IRQ enable
+
+#define DC_X_PMIC_REG_IRQ_CTRL_2 0x41
+#define DC_X_PMIC_REG_IRQ_CTRL_3 0x42
+#define DC_X_PMIC_REG_IRQ_CTRL_4 0x43
+#define DC_X_MASK_PMIC_TEMP BIT07 //The PMIC temperature over the warning level 2 IRQ (OTIRQ) enable
+#define DC_X_MASK_GPADC BIT02 //GPADC(GPIO0) ADC convert finished IRQ enable
+#define DC_X_MASK_WARN_LEVEL1 BIT01 //Enable bit for IRQ which indicate battery capacity ratio being lower than warning level1
+#define DC_X_MASK_WARN_LEVEL2 BIT00 //Enable bit for IRQ which indicate battery capacity ratio being lower than warning level2
+
+#define DC_X_PMIC_REG_IRQ_CTRL_5 0x44
+#define DC_X_PMIC_REG_IRQ_CTRL_6 0x45
+#define DC_X_PMIC_REG_IRQ_STS_1 0x48
+#define DC_X_MASK_VBUS_HI_TO_LOW BIT02 //VBUS from high go low IRQ
+#define DC_X_MASK_VBUS_LOW_TO_HI BIT03 //VBUS from low go high IRQ
+#define DC_X_MASK_VBUS_OV_VOL BIT04 //VBUS over voltage IRQ
+
+#define DC_X_PMIC_REG_IRQ_STS_2 0x49
+#define DC_X_MASK_BAT_APPEND BIT07 //Battery append IRQ
+#define DC_X_MASK_BAT_CHARGE_DONE BIT02 //Battery charge done IRQ
+
+#define DC_X_PMIC_REG_IRQ_STS_3 0x4A
+#define DC_X_PMIC_REG_IRQ_STS_4 0x4B
+#define DC_X_PMIC_REG_IRQ_STS_5 0x4C
+#define DC_X_MASK_PMIC_EVENT_IRQ_STS BIT07
+#define DC_X_MASK_PMIC_POKPIRQ_STS BIT06
+#define DC_X_MASK_PMIC_POKNIRQ_STS BIT05
+#define DC_X_MASK_PMIC_POKSIRQ_STS BIT04
+#define DC_X_MASK_PMIC_POKLIRQ_STS BIT03
+#define DC_X_MASK_PMIC_POKOIRQ_STS BIT02
+#define DC_X_MASK_PMIC_GPIO1_IRQ_STS BIT01
+#define DC_X_MASK_PMIC_GPIO0_IRQ_STS BIT00
+
+#define DC_X_PMIC_REG_IRQ_STS_6 0x4D
+
+#define DC_X_PMIC_REG_TS_PIN_INPUT_HI 0x58
+#define DC_X_PMIC_REG_TS_PIN_INPUT_LO 0x59
+#define DC_X_PMIC_REG_GPADC_INPUT_HI 0x5A
+#define DC_X_PMIC_REG_GPADC_INPUT_LO 0x5B
+
+#define DC_X_PMIC_REG_BAT_VOL_HI 0x78
+#define DC_X_PMIC_REG_BAT_VOL_LO 0x79
+#define DC_X_PMIC_REG_BAT_CHG_CURRENT_HI 0x7A
+#define DC_X_PMIC_REG_BAT_CHG_CURRENT_LO 0x7B
+#define DC_X_PMIC_REG_BAT_DISCHG_CURRENT_HI 0x7C
+#define DC_X_PMIC_REG_BAT_DISCHG_CURRENT_LO 0x7D
+
+#define DC_X_PMIC_REG_BUCK_MODE_SEL 0x80
+#define DC_X_MASK_BUCK2_PFM_PWM_CTRL BIT06 //BUCK2 PFM/PWM control: 0: auto switch 1: always PWM
+#define DC_X_MASK_BUCK3_PFM_PWM_CTRL BIT05 //BUCK3 PFM/PWM control: 0: auto switch 1: always PWM
+#define DC_X_MASK_BUCK4_PFM_PWM_CTRL BIT04 //BUCK4 PFM/PWM control: 0: auto switch 1: always PWM
+#define DC_X_MASK_BUCK1_PFM_PWM_CTRL BIT03 //BUCK1 PFM/PWM control: 0: auto switch 1: PSM/PWM
+#define DC_X_MASK_BUCK5_PFM_PWM_CTRL BIT01 //BUCK5 PFM/PWM control: 0: auto switch 1: PSM/PWM
+#define DC_X_MASK_BUCK6_PFM_PWM_CTRL BIT00 //BUCK6 PFM/PWM control: 0: auto switch 1: always PWM
+
+#define DC_X_PMIC_REG_OUTPUT_MON_CTRL 0x81
+#define DC_X_PMIC_REG_ADC_ENABLE 0x82
+#define DC_X_MASK_GPIO0_ADC_ENABLE BIT04 //GPIO0 ADC enable
+
+#define DC_X_PMIC_REG_ADC_CTRL 0x84
+#define DC_X_MASK_GPIO0_PIN_CTRL (BIT07|BIT06) //Current source from GPIO0 pin control
+#define DC_X_MASK_GPIO0_PIN_CTRL_20UA (0x0) //20uA
+#define DC_X_MASK_GPIO0_PIN_CTRL_40UA (BIT06) //40uA
+#define DC_X_MASK_GPIO0_PIN_CTRL_60UA (BIT07) //60uA
+#define DC_X_MASK_GPIO0_PIN_CTRL_80UA (BIT07|BIT06) //80uA
+
+#define DC_X_PMIC_REG_ADC_SPEED_SETTING 0x85
+#define DC_X_MASK_GPIO0_ADC_WORK_MODE (BIT02) //GPIO0 ADC work mode 1-outout current
+
+#define DC_X_PMIC_REG_TIMER_CTRL 0x8A
+#define DC_X_PMIC_REG_BUCK_OUTPUT_MON 0x8E
+#define DC_X_PMIC_REG_IRQ_HOT_OVSHDN 0x8F
+#define DC_X_MASK_POK16S_RESET_EN BIT03
+#define DC_X_MASK_OVTEMP_SHWD_EN BIT02
+#define DC_X_MASK_VOL_RECOVERY_EN BIT01
+
+#define DC_X_PMIC_REG_GPIO0_CTRL 0x90
+#define DC_X_MASK_GPIO0_PIN_FUNC_CTRL (BIT02|BIT01|BIT00) //ADC input mode
+
+#define DC_X_PMIC_REG_GPIO0_VOLTAGE 0x91
+#define DC_X_PMIC_REG_GPIO1_CTRL 0x92
+#define DC_X_PMIC_REG_GPIO1_VOLTAGE 0x93
+#define DC_X_PMIC_REG_GPIO_STATUS 0x94
+#define DC_X_PMIC_REG_GPIO_CTRL 0x97
+#define DC_X_PMIC_REG_WAKEUP_SEQUENCE1 0x9A
+
+#define DC_X_PMIC_REG_WAKEUP_SEQUENCE2 0x9B
+#define DC_X_PMIC_REG_SLEEP_SEQUENCE1 0x9C
+#define DC_X_PMIC_REG_SLEEP_SEQUENCE2 0x9D
+#define DC_X_PMIC_REG_VR_SLEEP_STATE 0x9E
+#define DC_X_MASK_BUCK2_SLP_S0IX_B BIT04 //When BUCK2 controlled by SLP_S0IX_B, power state in sleep mode: 1:Vsleep
+#define DC_X_MASK_BUCK3_SLP_S0IX_B BIT03 //When BUCK3 controlled by SLP_S0IX_B, power state in sleep mode: 1:Vsleep
+#define DC_X_MASK_BUCK1_SLP_S0IX_B BIT02 //When BUCK1 controlled by SLP_S0IX_B, power state in sleep mode: 1:Vsleep
+#define DC_X_MASK_BUCK5_SLP_S0IX_B BIT01 //When BUCK5 controlled by SLP_S0IX_B, power state in sleep mode: 1:Vsleep
+#define DC_X_MASK_FLDO1_SLP_S0IX_B BIT00 //When FLDO1 controlled by SLP_S0IX_B, power state in sleep mode: 1:Vsleep
+
+#define DC_X_PMIC_REG_RT_BAT_VOL_HI 0xA0
+#define DC_X_PMIC_REG_RT_BAT_VOL_LO 0xA1
+
+#define DC_X_PMIC_REG_FUEL_GARGE_CTRL 0xB8
+#define DC_X_PMIC_REG_BAT_CAP_PERCENT 0xB9
+#define DC_X_PMIC_REG_RDC1 0xBA
+#define DC_X_PMIC_REG_RDC0 0xBB
+#define DC_X_PMIC_REG_OCV1 0xBC
+#define DC_X_PMIC_REG_OCV0 0xBD
+#define DC_X_PMIC_REG_BAT_MAX_CAP_HI 0xE0
+#define DC_X_PMIC_REG_BAT_MAX_CAP_LO 0xE1
+#define DC_X_PMIC_REG_CLB_M_COUNTER_HI 0xE2
+#define DC_X_PMIC_REG_CLB_M_COUNTER_LO 0xE3
+#define DC_X_PMIC_REG_OCV_PERCENT_BAT_CAP 0xE4
+#define DC_X_PMIC_REG_CLB_M_PERCENT_BAT_CAP 0xE5
+#define DC_X_PMIC_REG_BAT_CAP_PERCENT_W 0xE6
+#define DC_X_PMIC_REG_FUEL_GARGE_T_CTRL_0 0xE8
+#define DC_X_PMIC_REG_FUEL_GARGE_T_CTRL_1 0xE9
+#define DC_X_PMIC_REG_FUEL_GARGE_T_CTRL_2 0xEA
+#define DC_X_PMIC_REG_FUEL_GARGE_T_CTRL_3 0xEB
+#define DC_X_PMIC_REG_FUEL_GARGE_T_CTRL_4 0xEC
+#define DC_X_PMIC_REG_FUEL_GARGE_T_CTRL_5 0xED
+
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_C0 0xC0
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_C1 0xC1
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_C2 0xC2
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_C3 0xC3
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_C4 0xC4
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_C5 0xC5
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_C6 0xC6
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_C7 0xC7
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_C8 0xC8
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_C9 0xC9
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_CA 0xCA
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_CB 0xCB
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_CC 0xCC
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_CD 0xCD
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_CE 0xCE
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_CF 0xCF
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_D0 0xD0
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_D1 0xD1
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_D2 0xD2
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_D3 0xD3
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_D4 0xD4
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_D5 0xD5
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_D6 0xD6
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_D7 0xD7
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_D8 0xD8
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_D9 0xD9
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_DA 0xDA
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_DB 0xDB
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_DC 0xDC
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_DD 0XDD
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_DE 0xDE
+#define DC_X_PMIC_REG_FUEL_GAUGE_CHAR_DF 0xDF
+
+#if 0
+//DollarCove XPOWER FG Characterization data Provided by FG Mfg
+//This Registers 0xC0-0xDF is OCV Percentage Table ( Refer AXP288 Datasheet for more detail )
+//Charcterizaiton Start ----->
+#define XPOWER_FG_OCV_C0 0x00
+#define XPOWER_FG_OCV_C1 0x00
+#define XPOWER_FG_OCV_C2 0x00
+#define XPOWER_FG_OCV_C3 0x00
+#define XPOWER_FG_OCV_C4 0x01
+#define XPOWER_FG_OCV_C5 0x01
+#define XPOWER_FG_OCV_C6 0x02
+#define XPOWER_FG_OCV_C7 0x02
+#define XPOWER_FG_OCV_C8 0x02
+#define XPOWER_FG_OCV_C9 0x03
+#define XPOWER_FG_OCV_CA 0x03
+#define XPOWER_FG_OCV_CB 0x04
+#define XPOWER_FG_OCV_CC 0x0C
+#define XPOWER_FG_OCV_CD 0x10
+#define XPOWER_FG_OCV_CE 0x16
+#define XPOWER_FG_OCV_CF 0x1C
+#define XPOWER_FG_OCV_D0 0x27
+#define XPOWER_FG_OCV_D1 0x2C
+#define XPOWER_FG_OCV_D2 0x30
+#define XPOWER_FG_OCV_D3 0x35
+#define XPOWER_FG_OCV_D4 0x3A
+#define XPOWER_FG_OCV_D5 0x3F
+#define XPOWER_FG_OCV_D6 0x43
+#define XPOWER_FG_OCV_D7 0x47
+#define XPOWER_FG_OCV_D8 0x4B
+#define XPOWER_FG_OCV_D9 0x4E
+#define XPOWER_FG_OCV_DA 0x50
+#define XPOWER_FG_OCV_DB 0x51
+#define XPOWER_FG_OCV_DC 0x54
+#define XPOWER_FG_OCV_DD 0x57
+#define XPOWER_FG_OCV_DE 0x5B
+#define XPOWER_FG_OCV_DF 0x5E
+
+#define BATTERY_MAX_CAP_HI 0x8D
+#define BATTERY_MAX_CAP_LO 0xA3
+#define BATTERY_RDC1 0xC0
+#define BATTERY_RDC0 0x97
+
+//Charcterizaiton Table End <-----------
+#endif
+
+#endif
+
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicWhiskeyCove.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicWhiskeyCove.h new file mode 100644 index 0000000000..39c7760ef1 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/PmicWhiskeyCove.h @@ -0,0 +1,939 @@ +/** @file
+
+ Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PMIC_REG_WC_H_
+#define _PMIC_REG_WC_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/I2CLib.h>
+#include <Library/PmicLib.h>
+#include <Library/TimerLib.h>
+#include <Library/PcdLib.h>
+#include "PmicReg.h"
+#include "ChvAccess.h"
+#include <Guid/PlatformInfo.h>
+#include "PmicNVMProvision.h"
+
+#define DELAY_BETWEEN_INSTRUCTION_500 500
+#define DELAY_BETWEEN_INSTRUCTION_100 100
+#define DELAY_BETWEEN_INSTRUCTION_50 50
+#define DELAY_BETWEEN_INSTRUCTION_10 10
+#define DELAY_BETWEEN_INSTRUCTION_5 5
+
+#define WC_PMIC_I2C_CHANNEL_NUMBER 0x6
+#define WC_PMIC_I2C_DEV_1_SLAVE_ADDRESS 0x4E // For BXT
+#define WC_PMIC_I2C_DEV_2_SLAVE_ADDRESS 0x4F // Common
+#define WC_PMIC_I2C_DEV_3_SLAVE_ADDRESS 0x5E // Common
+#define WC_PMIC_I2C_DEV_4_SLAVE_ADDRESS 0x5F // Common
+#define WC_PMIC_I2C_DEV_5_SLAVE_ADDRESS 0x6E // For CHT
+#define WC_PMIC_I2C_SCRATCH_SLAVE_ADDRESS 0x6F
+#define WC_PMIC_I2C_VCC0_DEVICE_ADDRESS 0x10
+#define WC_PMIC_I2C_VCC1_DEVICE_ADDRESS 0x18
+#define WC_PMIC_I2C_VNN_DEVICE_ADDRESS 0x12
+#define WC_PMIC_I2C_VGG_DEVICE_ADDRESS 0x1A
+
+//VCC0 VCC1 VNN VGG definitions
+
+#define VOUT_MAX_REG 0x30
+#define VID_MAX_REG 0x33
+
+//DEV 2 definitions
+
+#define DEV2_ID_TRMPGM_REG 0x00
+#define DEV2_ID_OTPVERSION_REG 0x01
+#define DEV2_ADC_GPADCREQ_REG 0x02
+#define DEV2_ADC_VBATRSLTH_REG 0x03
+#define DEV2_ADC_VBATRSLTL_REG 0x04
+#define DEV2_ADC_GPADCCNTL_REG 0x05
+#define DEV2_ADC_BATTIDRSLTH_REG 0x06
+#define DEV2_ADC_BATTIDRSLTL_REG 0x07
+#define DEV2_ADC_USBIDRSLTH_REG 0x08
+#define DEV2_ADC_USBIDRSLTL_REG 0x09
+#define DEV2_ADC_GPMEASRSLTH_REG 0x0A
+#define DEV2_ADC_GPMEASRSLTL_REG 0x0B
+#define DEV2_ADC_Y0DATAH_REG 0x0C
+#define DEV2_ADC_Y0DATAL_REG 0x0D
+#define DEV2_ADC_Y1DATAH_REG 0x0E
+#define DEV2_ADC_Y1DATAL_REG 0x0F
+#define DEV2_SVID_DEV2_STATUS_1_REG 0x10
+#define DEV2_SVID_DEV2_STATUS_2_REG 0x11
+#define DEV2_ADC_PEAKREQ_REG 0x12
+#define DEV2_ADC_PEAKRSLTH_REG 0x13
+#define DEV2_ADC_PEAKRSLTL_REG 0x14
+#define DEV2_THERM_BATTEMP0H_REG 0x15
+#define DEV2_THERM_BATTEMP0L_REG 0x16
+#define DEV2_THERM_BATTEMP1H_REG 0x17
+#define DEV2_THERM_BATTEMP1L_REG 0x18
+#define DEV2_THERM_STHRMIRQ0_REG 0x19
+#define DEV2_THERM_STHRMIRQ1_REG 0x1A
+#define DEV2_THERM_STHRMIRQ2_REG 0x1B
+#define DEV2_SVID_DEV2_STATUS2_LASTREAD_REG 0x1C
+#define DEV2_THERM_THRMMONCFG_REG 0x1D
+#define DEV2_THERM_THRMMONCTL_REG 0x1E
+#define DEV2_THERM_BATTHERMMONCTL_REG 0x1F
+#define DEV2_THERM_VBATMONCTL_REG 0x20
+#define DEV2_THERM_GPMONCTL_REG 0x21
+#define DEV2_THERM_THRMBATZONE_REG 0x22
+#define DEV2_THERM_SYS0ALERT0H_REG 0x23
+#define DEV2_THERM_SYS0ALERT0L_REG 0x24
+#define DEV2_THERM_SYS0ALERT1H_REG 0x25
+#define DEV2_THERM_SYS0ALERT1L_REG 0x26
+#define DEV2_THERM_SYS1ALERT0H_REG 0x27
+#define DEV2_THERM_SYS1ALERT0L_REG 0x28
+#define DEV2_THERM_SYS1ALERT1H_REG 0x29
+#define DEV2_THERM_SYS1ALERT1L_REG 0x2A
+#define DEV2_THERM_SYS2ALERT0H_REG 0x2B
+#define DEV2_THERM_SYS2ALERT0L_REG 0x2C
+#define DEV2_THERM_SYS2ALERT1H_REG 0x2D
+#define DEV2_THERM_SYS2ALERT1L_REG 0x2E
+#define DEV2_THERM_BAT0ALERT0H_REG 0x2F
+#define DEV2_THERM_BAT0ALERT0L_REG 0x30
+#define DEV2_THERM_BAT1ALERT0H_REG 0x31
+#define DEV2_THERM_BAT1ALERT0L_REG 0x32
+#define DEV2_THERM_PMICALERT0H_REG 0x33
+#define DEV2_THERM_PMICALERT0L_REG 0x34
+#define DEV2_SVID_DEV2_SETREGADR_REG 0x35
+#define DEV2_THERM_GPMEASALERTH_REG 0x36
+#define DEV2_THERM_GPMEASALERTL_REG 0x37
+#define DEV2_THERM_THRMRSLT0H_REG 0x38
+#define DEV2_THERM_THRMRSLT0L_REG 0x39
+#define DEV2_THERM_THRMRSLT1H_REG 0x3A
+#define DEV2_THERM_THRMRSLT1L_REG 0x3B
+#define DEV2_THERM_THRMRSLT2H_REG 0x3C
+#define DEV2_THERM_THRMRSLT2L_REG 0x3D
+#define DEV2_THERM_THRMRSLT3H_REG 0x3E
+#define DEV2_THERM_THRMRSLT3L_REG 0x3F
+#define DEV2_THERM_THRMRSLT4H_REG 0x40
+#define DEV2_THERM_THRMRSLT4L_REG 0x41
+#define DEV2_THERM_THRMRSLT5H_REG 0x42
+#define DEV2_THERM_THRMRSLT5L_REG 0x43
+#define DEV2_THERM_THRMZN0H_REG 0x44
+#define DEV2_THERM_THRMZN0L_REG 0x45
+#define DEV2_THERM_THRMZN1H_REG 0x46
+#define DEV2_THERM_THRMZN1L_REG 0x47
+#define DEV2_THERM_THRMZN2H_REG 0x48
+#define DEV2_THERM_THRMZN2L_REG 0x49
+#define DEV2_THERM_THRMZN3H_REG 0x4A
+#define DEV2_THERM_THRMZN3L_REG 0x4B
+#define DEV2_THERM_THRMZN4H_REG 0x4C
+#define DEV2_THERM_THRMZN4L_REG 0x4D
+#define DEV2_THERM_BATCRITCOLDH_REG 0x4E
+#define DEV2_THERM_BATCRITCOLDL_REG 0x4F
+#define DEV2_THERM_BATCRITHOTH_REG 0x50
+#define DEV2_THERM_BATCRITHOTL_REG 0x51
+#define DEV2_THERM_BATCRITH_REG 0x52
+#define DEV2_THERM_BATCRITL_REG 0x53
+#define DEV2_THERM_PMICCRITH_REG 0x54
+#define DEV2_THERM_PMICCRITL_REG 0x55
+#define DEV2_THERM_SYS0CRITH_REG 0x56
+#define DEV2_THERM_SYS0CRITL_REG 0x57
+#define DEV2_THERM_SYS1CRITH_REG 0x58
+#define DEV2_THERM_SYS1CRITL_REG 0x59
+#define DEV2_THERM_SYS2CRITH_REG 0x5A
+#define DEV2_THERM_SYS2CRITL_REG 0x5B
+#define DEV2_THERM_SYS0ALERT3H_REG 0x5C
+#define DEV2_THERM_SYS0ALERT3L_REG 0x5D
+#define DEV2_THERM_SYS1ALERT3H_REG 0x5E
+#define DEV2_THERM_SYS1ALERT3L_REG 0x5F
+#define DEV2_THERM_SYS2ALERT3H_REG 0x60
+#define DEV2_THERM_SYS2ALERT3L_REG 0x61
+#define DEV2_THERM_PMICALERT3H_REG 0x62
+#define DEV2_THERM_PMICALERT3L_REG 0x63
+#define DEV2_THERM_BAT0ALERT3H_REG 0x64
+#define DEV2_THERM_BAT0ALERT3L_REG 0x65
+#define DEV2_THERM_BAT1ALERT3H_REG 0x66
+#define DEV2_THERM_BAT1ALERT3L_REG 0x67
+#define DEV2_THERM_THRMCRITEN_REG 0x68
+#define DEV2_THERM_THRMALERT3EN_REG 0x69
+#define DEV2_THERM_THRMALERT3PAEN_REG 0x6A
+#define DEV2_IMON_CM_VCC0_MODE_CTRL_REG 0x6B
+#define DEV2_IMON_CM_VCC1_MODE_CTRL_REG 0x6C
+#define DEV2_IMON_CM_VCC_MODE_CTRL_REG 0x6D
+#define DEV2_IMON_CM_VNN_MODE_CTRL_REG 0x6E
+#define DEV2_IMON_CM_VNNAON_MODE_CTRL_REG 0x6F
+#define DEV2_IMON_CM_VDD1_MODE_CTRL_REG 0x70
+#define DEV2_IMON_CM_VDD2_MODE_CTRL_REG 0x71
+#define DEV2_IMON_CM_VCCRAM_MODE_CTRL_REG 0x72
+#define DEV2_IMON_CM_VMEM_MODE_CTRL_REG 0x73
+#define DEV2_IMON_CM_VFLEX_MODE_CTRL_REG 0x74
+#define DEV2_IMON_CM_VPROG1A_MODE_CTRL_REG 0x75
+#define DEV2_IMON_CM_VPROG1B_MODE_CTRL_REG 0x76
+#define DEV2_IMON_CM_VPROG1C_MODE_CTRL_REG 0x77
+#define DEV2_IMON_CM_VPROG1D_MODE_CTRL_REG 0x78
+#define DEV2_IMON_CM_VPROG2A_MODE_CTRL_REG 0x79
+#define DEV2_IMON_CM_VPROG2B_MODE_CTRL_REG 0x7A
+#define DEV2_IMON_CM_VPROG2C_MODE_CTRL_REG 0x7B
+#define DEV2_IMON_CM_VPROG3A_MODE_CTRL_REG 0x7C
+#define DEV2_IMON_CM_VPROG3B_MODE_CTRL_REG 0x7D
+#define DEV2_IMON_CM_TSPAN_CTRL_REG 0x7E
+#define DEV2_IMON_CM_LDO1_THRSHLD_REG 0x7F
+#define DEV2_IMON_CM_LDO2_THRSHLD_REG 0x80
+#define DEV2_IMON_CM_LDO3_THRSHLD_REG 0x81
+#define DEV2_IMON_CM_SMPS0_THRSHLD_REG 0x82
+#define DEV2_IMON_CM_SMPS1_THRSHLD_REG 0x83
+#define DEV2_IMON_CM_SMPS2_THRSHLD_REG 0x84
+#define DEV2_IMON_CM_SMPS3_THRSHLD_REG 0x85
+#define DEV2_IMON_CM_SMPS4_THRSHLD_REG 0x86
+#define DEV2_IMON_CM_SMPS5_THRSHLD_REG 0x87
+#define DEV2_IMON_CM_VCC0_DATA_REG 0x88
+#define DEV2_IMON_CM_VCC1_DATA_REG 0x89
+#define DEV2_IMON_CM_VCC_DATA_REG 0x8A
+#define DEV2_IMON_CM_VNN_DATA_REG 0x8B
+#define DEV2_IMON_CM_VNNAON_DATA_REG 0x8C
+#define DEV2_IMON_CM_VDD1_DATA_REG 0x8D
+#define DEV2_IMON_CM_VDD2_DATA_REG 0x8E
+#define DEV2_IMON_CM_VCCRAM_DATA_REG 0x8F
+#define DEV2_IMON_CM_VMEM_DATA_REG 0x90
+#define DEV2_IMON_CM_VFLEX_DATA_REG 0x91
+#define DEV2_IMON_CM_PROG1A_DATA_REG 0x92
+#define DEV2_IMON_CM_PROG1B_DATA_REG 0x93
+#define DEV2_IMON_CM_PROG1C_DATA_REG 0x94
+#define DEV2_IMON_CM_PROG1D_DATA_REG 0x95
+#define DEV2_IMON_CM_PROG2A_DATA_REG 0x96
+#define DEV2_IMON_CM_PROG2B_DATA_REG 0x97
+#define DEV2_IMON_CM_PROG2C_DATA_REG 0x98
+#define DEV2_IMON_CM_PROG3A_DATA_REG 0x99
+#define DEV2_IMON_CM_PROG3B_DATA_REG 0x9A
+#define DEV2_IMON_CM_VCC0_INT_LVL_REG 0x9B
+#define DEV2_IMON_CM_VCC1_INT_LVL_REG 0x9C
+#define DEV2_IMON_CM_VCC_INT_LVL_REG 0x9D
+#define DEV2_IMON_CM_VNN_INT_LVL_REG 0x9E
+#define DEV2_IMON_CM_VNNAON_INT_LVL_REG 0x9F
+#define DEV2_IMON_CM_VDD1_INT_LVL_REG 0xA0
+#define DEV2_IMON_CM_VDD2_INT_LVL_REG 0xA1
+#define DEV2_IMON_CM_VCCRAM_INT_LVL_REG 0xA2
+#define DEV2_IMON_CM_VMEM_INT_LVL_REG 0xA3
+#define DEV2_IMON_CM_VFLEX_INT_LVL_REG 0xA4
+#define DEV2_IMON_CM_VPROG1A_INT_LVL_REG 0xA5
+#define DEV2_IMON_CM_VPROG1B_INT_LVL_REG 0xA6
+#define DEV2_IMON_CM_VPROG1C_INT_LVL_REG 0xA7
+#define DEV2_IMON_CM_VPROG1D_INT_LVL_REG 0xA8
+#define DEV2_IMON_CM_VPROG2A_INT_LVL_REG 0xA9
+#define DEV2_IMON_CM_VPROG2B_INT_LVL_REG 0xAA
+#define DEV2_IMON_CM_VPROG2C_INT_LVL_REG 0xAB
+#define DEV2_IMON_CM_VPROG3A_INT_LVL_REG 0xAC
+#define DEV2_IMON_CM_VPROG3B_INT_LVL_REG 0xAD
+#define DEV2_IMON_CM_VROCIRQSTAT0_REG 0xAE
+#define DEV2_IMON_CM_VROCIRQSTAT1_REG 0xAF
+#define DEV2_IMON_CM_VROCIRQSTAT2_REG 0xB0
+#define DEV2_IMON_CM_VROCIRQSTAT3_REG 0xB1
+#define DEV2_RTC_VRTCCTRL_REG 0xB5
+#define DEV2_TMU_TMUIRQ_REG 0xB6
+#define DEV2_TMU_MTMUIRQ_REG 0xB7
+#define DEV2_TMU_TMUSTATUS_REG 0xB8
+#define DEV2_TMU_TMUCONFIG_REG 0xB9
+#define DEV2_TMU_SECONDS_REG 0xBA
+#define DEV2_TMU_SECONDSW_REG 0xBA
+#define DEV2_TMU_SECONDSSA_REG 0xBB
+#define DEV2_TMU_SECONDSWA_REG 0xBC
+#define DEV2_TMU_MINUTES_REG 0xBD
+#define DEV2_TMU_MINUTESW_REG 0xBD
+#define DEV2_TMU_MINUTESSA_REG 0xBE
+#define DEV2_TMU_MINUTESWA_REG 0xBF
+#define DEV2_TMU_HOURS_REG 0xC0
+#define DEV2_TMU_HOURSW_REG 0xC0
+#define DEV2_TMU_HOURSSA_REG 0xC1
+#define DEV2_TMU_HOURSWA_REG 0xC2
+#define DEV2_TMU_DWEEK_REG 0xC3
+#define DEV2_TMU_DWEEKW_REG 0xC3
+#define DEV2_TMU_DMONTH_REG 0xC4
+#define DEV2_TMU_DMONTHW_REG 0xC4
+#define DEV2_TMU_MONTH_REG 0xC5
+#define DEV2_TMU_MONTHW_REG 0xC5
+#define DEV2_TMU_YEAR_REG 0xC6
+#define DEV2_TMU_YEARW_REG 0xC6
+#define DEV2_TMU_STCB1_REG 0xC7
+#define DEV2_TMU_STCB2_REG 0xC8
+#define DEV2_TMU_STCB3_REG 0xC9
+#define DEV2_TMU_STCB4_REG 0xCA
+#define DEV2_TMU_DMONTHWA_REG 0xCB
+#define DEV2_CLK_CLKCONFIG_REG 0xCC
+#define DEV2_CLKGEN_FLLCTRL_REG 0xCD
+#define DEV2_CLKGEN_FLLDACSH_REG 0xCE
+#define DEV2_CLKGEN_FLLDACSL_REG 0xCF
+#define DEV2_CLKGEN_FLLDAC_STATUSH_REG 0xD0
+#define DEV2_CLKGEN_FLLDAC_STATUSL_REG 0xD1
+#define DEV2_CLKGEN_FLLFRQDIV_REG 0xD2
+#define DEV2_CLKGEN_CLK32CTRL_REG 0xD3
+#define DEV2_GPLED_GPLEDCTRL_REG 0xDF
+#define DEV2_GPLED_GPLEDFSM_REG 0xE0
+#define DEV2_GPLED_GPLEDPWM_REG 0xE1
+#define DEV2_INTVREF_INTVREFCTRL_REG 0xE2
+#define DEV2_INTVREF_IREFTRIM_REG 0xE3
+#define DEV2_INTVREF_VREFTRIM0_REG 0xE4
+#define DEV2_INTVREF_VREFTRIM1_REG 0xE5
+#define DEV2_COULCNT_CC_THRH_REG 0xE6
+#define DEV2_COULCNT_CC_THRL_REG 0xE7
+#define DEV2_COULCNT_CC_CURR_SHRTH_REG 0xE8
+#define DEV2_COULCNT_CC_CURR_SHRTL_REG 0xE9
+#define DEV2_COULCNT_CC_CURR_LNGH_REG 0xEA
+#define DEV2_COULCNT_CC_CURR_LNGL_REG 0xEB
+#define DEV2_COULCNT_CC_CTRL0_REG 0xEC
+#define DEV2_COULCNT_CC_CTRL1_REG 0xED
+#define DEV2_COULCNT_CC_DOWN_B3_REG 0xEE
+#define DEV2_COULCNT_CC_DOWN_B2_REG 0xEF
+#define DEV2_COULCNT_CC_DOWN_B1_REG 0xF0
+#define DEV2_COULCNT_CC_DOWN_B0_REG 0xF1
+#define DEV2_COULCNT_CC_UP_B3_REG 0xF2
+#define DEV2_COULCNT_CC_UP_B2_REG 0xF3
+#define DEV2_COULCNT_CC_UP_B1_REG 0xF4
+#define DEV2_COULCNT_CC_UP_B0_REG 0xF5
+#define DEV2_COULCNT_VBATMAXH_REG 0xF5
+#define DEV2_COULCNT_VBATMAXHW_REG 0xF6
+#define DEV2_COULCNT_VBATMAXL_REG 0xF6
+#define DEV2_COULCNT_VBATMAXLW_REG 0xF7
+#define DEV2_COULCNT_MAX_CURR_SHRTH_REG 0xF8
+#define DEV2_COULCNT_MAX_CURR_SHRTL_REG 0xF9
+#define DEV2_COULCNT_MAX_CURR_LNGH_REG 0xFA
+#define DEV2_COULCNT_MAX_CURR_LNGL_REG 0xFB
+#define DEV2_ID_PROVERSION_REG 0xFF
+
+// DEV 3 definitions
+
+#define DEV3_CRIT_PMICWDTCNT_REG 0x00
+#define DEV3_CRIT_PMICWDTTC_REG 0x01
+#define DEV3_CRIT_SCRITIRQ_REG 0x02
+#define DEV3_USB_USBIDCTRL_REG 0x05
+#define DEV3_USB_USBIDDETTYPE_REG 0x06
+#define DEV3_USB_USBPHYCTRL_REG 0x07
+#define DEV3_USB_USBRSTGPO_REG 0x08
+#define DEV3_USB_USBRSTGPI_REG 0x09
+#define DEV3_VCTRL_VSYSCTRL_REG 0x0C
+#define DEV3_VCTRL_VOTPCTRL_REG 0x0D
+#define DEV3_VCTRL_VXOCNT_REG 0x0E
+#define DEV3_SVID_DEV3_STATUS_1_REG 0x10
+#define DEV3_SVID_DEV3_STATUS_2_REG 0x11
+#define DEV3_CHARGER_CHGDETGPO_REG 0x12
+#define DEV3_CHARGER_CHGDETGPI_REG 0x13
+#define DEV3_CHARGER_DBPTIMEOUT_REG 0x14
+#define DEV3_CHARGER_DBPTIMER_REG 0x15
+#define DEV3_CHARGER_CHGRCTRL0_REG 0x16
+#define DEV3_CHARGER_CHGRCTRL1_REG 0x17
+#define DEV3_CHARGER_CHGRCTRL2_REG 0x18
+#define DEV3_CHARGER_CHGRSTATUS_REG 0x19
+#define DEV3_CHARGER_SCHGRIRQ_REG 0x1A
+#define DEV3_SVID_DEV3_STATUS2_LASTREAD_REG 0x1C
+#define DEV3_CHARGER_VBUSDETCTRL_REG 0x1D
+#define DEV3_CHARGER_VDCINDETCTRL_REG 0x1E
+#define DEV3_CHARGER_CHRLEDCTRL_REG 0x1F
+#define DEV3_CHARGER_CHRLEDFSM_REG 0x20
+#define DEV3_CHARGER_CHRLEDPWM_REG 0x21
+#define DEV3_CHARGER_CHRTTADDR_REG 0x22
+#define DEV3_CHARGER_CHRTTDATA_REG 0x23
+#define DEV3_CHARGER_I2COVRCTRL_REG 0x24
+#define DEV3_CHARGER_I2COVRDADDR_REG 0x25
+#define DEV3_CHARGER_I2COVROFFSET_REG 0x26
+#define DEV3_CHARGER_I2COVRWRDATA_REG 0x27
+#define DEV3_CHARGER_I2COVRRDDATA_REG 0x28
+#define DEV3_CHARGER_USBSRCDETSTATUS0_REG 0x29
+#define DEV3_CHARGER_USBSRCDETSTATUS1_REG 0x2A
+#define DEV3_CHARGER_CCSMCMDSKIP_REG 0x2B
+#define DEV3_CHARGER_CCSMSFTTIMER_REG 0x2C
+#define DEV3_CHARGER_SCCSMSFTTIMER_REG 0x2D
+#define DEV3_CHARGER_CHGRCTRL3_REG 0x2E
+#define DEV3_CHARGER_CHGDISCTRL_REG 0x2F
+#define DEV3_TLP_TLP1CTRL_REG 0x30
+#define DEV3_TLP_TLP1EVSTATUS0_REG 0x31
+#define DEV3_TLP_TLP1EVSTATUS1_REG 0x32
+#define DEV3_TLP_TLP1EVSTATUS2_REG 0x33
+#define DEV3_TLP_TLP1EVSTATUS3_REG 0x34
+#define DEV3_SVID_DEV3_SETREGADR_REG 0x35
+#define DEV3_TLP_TLP1TRACEINSTH_REG 0x36
+#define DEV3_TLP_TLP1TRACEINSTL_REG 0x37
+#define DEV3_TLP_TLP1INSTMEMADDRH_REG 0x38
+#define DEV3_TLP_TLP1INSTMEMADDRL_REG 0x39
+#define DEV3_TLP_TLP1INSTMEMDATAH_REG 0x3A
+#define DEV3_TLP_TLP1INSTMEMDATAHW_REG 0x3A
+#define DEV3_TLP_TLP1INSTMEMDATAL_REG 0x3B
+#define DEV3_TLP_TLP1COLDBOOTH_REG 0x3C
+#define DEV3_TLP_TLP1COLDBOOTL_REG 0x3D
+#define DEV3_TLP_TLP1COLDOFFH_REG 0x3E
+#define DEV3_TLP_TLP1COLDOFFL_REG 0x3F
+#define DEV3_TLP_TLP1COLDRSTH_REG 0x40
+#define DEV3_TLP_TLP1COLDRSTL_REG 0x41
+#define DEV3_TLP_TLP1WARMRSTH_REG 0x42
+#define DEV3_TLP_TLP1WARMRSTL_REG 0x43
+#define DEV3_TLP_TLP1ESBS0I1H_REG 0x44
+#define DEV3_TLP_TLP1ESBS0I1L_REG 0x45
+#define DEV3_TLP_TLP1ESBS0I1VNNH_REG 0x46
+#define DEV3_TLP_TLP1ESBS0I1VNNL_REG 0x47
+#define DEV3_TLP_TLP1ESBS0I1VNNLPH_REG 0x48
+#define DEV3_TLP_TLP1ESBS0I1VNNLPL_REG 0x49
+#define DEV3_TLP_TLP1ESBS0I2H_REG 0x4A
+#define DEV3_TLP_TLP1ESBS0I2L_REG 0x4B
+#define DEV3_TLP_TLP1ESBS0I3H_REG 0x4C
+#define DEV3_TLP_TLP1ESBS0I3L_REG 0x4D
+#define DEV3_TLP_TLP1ESBS0I3LPH_REG 0x4E
+#define DEV3_TLP_TLP1ESBS0I3LPL_REG 0x4F
+#define DEV3_TLP_TLP1EXSBH_REG 0x50
+#define DEV3_TLP_TLP1EXSBL_REG 0x51
+#define DEV3_TLP_TLP1ESBS0IXH_REG 0x52
+#define DEV3_TLP_TLP1ESBS0IXL_REG 0x53
+#define DEV3_TLP_TLP1ESBS3H_REG 0x54
+#define DEV3_TLP_TLP1ESBS3L_REG 0x55
+#define DEV3_TLP_TLP1EXSBS0IXH_REG 0x56
+#define DEV3_TLP_TLP1EXSBS0IXL_REG 0x57
+#define DEV3_TLP_TLP1EXSBS3H_REG 0x58
+#define DEV3_TLP_TLP1EXSBS3L_REG 0x59
+#define DEV3_TLP_TLP1MODEMRSTH_REG 0x5A
+#define DEV3_TLP_TLP1MODEMRSTL_REG 0x5B
+#define DEV3_TLP_TLP1VRSETTLED_REG 0x5C
+#define DEV3_TLP_TLP2CTRL_REG 0x61
+#define DEV3_TLP_TLP2EVSTATUS_REG 0x62
+#define DEV3_TLP_TLP2TRACEINST_REG 0x63
+#define DEV3_TLP_TLP2INSTMEMADDR_REG 0x64
+#define DEV3_TLP_TLP2INSTMEMDATA_REG 0x65
+#define DEV3_TLP_TLP2SYSTEMP_REG 0x66
+#define DEV3_TLP_TLP2BATTID_REG 0x67
+#define DEV3_TLP_TLP2BATTV_REG 0x68
+#define DEV3_TLP_TLP2USBID_REG 0x69
+#define DEV3_TLP_TLP2PEAK_REG 0x6A
+#define DEV3_TLP_TLP2GPMEAS_REG 0x6B
+#define DEV3_IMON_CM_VPROG1E_MODE_CTRL_REG 0x70
+#define DEV3_IMON_CM_VPROG1F_MODE_CTRL_REG 0x71
+#define DEV3_IMON_CM_VPROG2D_MODE_CTRL_REG 0x72
+#define DEV3_IMON_CM_VPROG4A_MODE_CTRL_REG 0x73
+#define DEV3_IMON_CM_VPROG4B_MODE_CTRL_REG 0x74
+#define DEV3_IMON_CM_VPROG4C_MODE_CTRL_REG 0x75
+#define DEV3_IMON_CM_VPROG4D_MODE_CTRL_REG 0x76
+#define DEV3_IMON_CM_VPROG5A_MODE_CTRL_REG 0x77
+#define DEV3_IMON_CM_VPROG5B_MODE_CTRL_REG 0x78
+#define DEV3_IMON_CM_VPROG6A_MODE_CTRL_REG 0x79
+#define DEV3_IMON_CM_VPROG6B_MODE_CTRL_REG 0x7A
+#define DEV3_IMON_CM_VPROG7A_MODE_CTRL_REG 0x7B
+#define DEV3_IMON_CM_LDO4_THRSHLD_REG 0x81
+#define DEV3_IMON_CM_LDO5_THRSHLD_REG 0x82
+#define DEV3_IMON_CM_LDO6_THRSHLD_REG 0x83
+#define DEV3_IMON_CM_PROG1E_DATA_REG 0x86
+#define DEV3_IMON_CM_PROG1F_DATA_REG 0x87
+#define DEV3_IMON_CM_PROG2D_DATA_REG 0x88
+#define DEV3_IMON_CM_PROG4A_DATA_REG 0x89
+#define DEV3_IMON_CM_PROG4B_DATA_REG 0x8A
+#define DEV3_IMON_CM_PROG4C_DATA_REG 0x8B
+#define DEV3_IMON_CM_PROG4D_DATA_REG 0x8C
+#define DEV3_IMON_CM_PROG5A_DATA_REG 0x8D
+#define DEV3_IMON_CM_PROG5B_DATA_REG 0x8E
+#define DEV3_IMON_CM_PROG6A_DATA_REG 0x8F
+#define DEV3_IMON_CM_PROG6B_DATA_REG 0x90
+#define DEV3_IMON_CM_PROG7A_DATA_REG 0x91
+#define DEV3_IMON_CM_VPROG1E_INT_LVL_REG 0x97
+#define DEV3_IMON_CM_VPROG1F_INT_LVL_REG 0x98
+#define DEV3_IMON_CM_VPROG2D_INT_LVL_REG 0x99
+#define DEV3_IMON_CM_VPROG4A_INT_LVL_REG 0x9A
+#define DEV3_IMON_CM_VPROG4B_INT_LVL_REG 0x9B
+#define DEV3_IMON_CM_VPROG4C_INT_LVL_REG 0x9C
+#define DEV3_IMON_CM_VPROG4D_INT_LVL_REG 0x9D
+#define DEV3_IMON_CM_VPROG5A_INT_LVL_REG 0x9E
+#define DEV3_IMON_CM_VPROG5B_INT_LVL_REG 0x9F
+#define DEV3_IMON_CM_VPROG6A_INT_LVL_REG 0xA0
+#define DEV3_IMON_CM_VPROG6B_INT_LVL_REG 0xA1
+#define DEV3_IMON_CM_VPROG7A_INT_LVL_REG 0xA2
+
+// DEV 4 definitions
+
+#define DEV4_SVID_DEV4_STATUS_1_REG 0x10
+#define DEV4_SVID_DEV4_STATUS_2_REG 0x11
+#define DEV4_SVID_DEV4_STATUS2_LASTREAD_REG 0x1C
+#define DEV4_SVID_DEV4_SETREGADR_REG 0x35
+#define DEV4_VENDOR_VENDCTL0_REG 0x36
+#define DEV4_VENDOR_VENDCTL1_REG 0x37
+#define DEV4_VENDOR_VENDCTL2_REG 0x38
+#define DEV4_VENDOR_VENDCTL3_REG 0x39
+#define DEV4_VENDOR_NVM_MB_ADDRH_REG 0x3A
+#define DEV4_VENDOR_NVM_MB_ADDRL_REG 0x3B
+#define DEV4_VENDOR_NVM_MB_DATA_REG 0x3C
+#define DEV4_VENDOR_NVMDBUF0_REG 0x3D
+#define DEV4_VENDOR_NVMDBUF1_REG 0x3E
+#define DEV4_VENDOR_NVMDBUF2_REG 0x3F
+#define DEV4_VENDOR_NVMDBUF3_REG 0x40
+#define DEV4_VENDOR_NVMDBUF4_REG 0x41
+#define DEV4_VENDOR_NVMDBUF5_REG 0x42
+#define DEV4_VENDOR_NVMDBUF6_REG 0x43
+#define DEV4_VENDOR_NVMDBUF7_REG 0x44
+#define DEV4_VENDOR_NVMDBUF8_REG 0x45
+#define DEV4_VENDOR_NVMDBUF9_REG 0x46
+#define DEV4_VENDOR_NVMDBUF10_REG 0x47
+#define DEV4_VENDOR_NVMDBUF11_REG 0x48
+#define DEV4_VENDOR_NVMDBUF12_REG 0x49
+#define DEV4_VENDOR_NVMDBUF13_REG 0x4A
+#define DEV4_VENDOR_NVMDBUF14_REG 0x4B
+#define DEV4_VENDOR_NVMDBUF15_REG 0x4C
+#define DEV4_VENDOR_NVMDBUF16_REG 0x4D
+#define DEV4_VENDOR_NVMDBUF17_REG 0x4E
+#define DEV4_VENDOR_NVMDBUF18_REG 0x4F
+#define DEV4_VENDOR_NVMDBUF19_REG 0x50
+#define DEV4_VENDOR_NVMDBUF20_REG 0x51
+#define DEV4_VENDOR_NVMDBUF21_REG 0x52
+#define DEV4_VENDOR_NVMDBUF22_REG 0x53
+#define DEV4_VENDOR_NVMDBUF23_REG 0x54
+#define DEV4_VENDOR_NVMDBUF24_REG 0x55
+#define DEV4_VENDOR_NVMDBUF25_REG 0x56
+#define DEV4_VENDOR_NVMDBUF26_REG 0x57
+#define DEV4_VENDOR_NVMDBUF27_REG 0x58
+#define DEV4_VENDOR_NVMDBUF28_REG 0x59
+#define DEV4_VENDOR_NVMDBUF29_REG 0x5A
+#define DEV4_VENDOR_NVMDBUF30_REG 0x5B
+#define DEV4_VENDOR_NVMDBUF31_REG 0x5C
+#define DEV4_VENDOR_NVMDBUF32_REG 0x5D
+#define DEV4_VENDOR_NVMDBUF33_REG 0x5E
+#define DEV4_VENDOR_NVMCTL0_REG 0x5F
+#define DEV4_VENDOR_NVMCTL1_REG 0x60
+#define DEV4_VENDOR_OTPMR_REG 0x61
+#define DEV4_VENDOR_OTPMRA_RD1_REG 0x62
+#define DEV4_VENDOR_OTPMRA_RD2_REG 0x63
+#define DEV4_VENDOR_OTPMRB0_RD1_REG 0x64
+#define DEV4_VENDOR_OTPMRB0_RD2_REG 0x65
+#define DEV4_VENDOR_OTPMRB1_REG 0x66
+#define DEV4_VENDOR_NVMSTAT0_REG 0x67
+#define DEV4_VENDOR_SOAKING_STAT0_REG 0x68
+#define DEV4_VENDOR_SOAKING_STAT1_REG 0x69
+#define DEV4_VENDOR_NVM_USAGE_STATH_REG 0x6A
+#define DEV4_VENDOR_NVM_USAGE_STATL_REG 0x6B
+#define DEV4_VENDOR_CODSRC_REG 0x6C
+#define DEV4_VENDOR_ISOCTRL_REG 0x6D
+#define DEV4_VENDOR_OTPCONFIG_REG 0x6E
+#define DEV4_VIRQ_VENDIRQLVL1_REG 0x77
+#define DEV4_VIRQ_NVMVIRQ_REG 0x78
+#define DEV4_VIRQ_ADCTLP2VIRQ_REG 0x79
+#define DEV4_VIRQ_I2CSIFVIRQ_REG 0x7A
+#define DEV4_VIRQ_REGBUSVIRQ_REG 0x7B
+#define DEV4_VIRQ_CHGRVIRQ_REG 0x7C
+#define DEV4_VIRQ_TLP1VIRQ_REG 0x7D
+#define DEV4_VIRQ_DCDCVIRQ0_REG 0x7E
+#define DEV4_VIRQ_DCDCVIRQ1_REG 0x7F
+#define DEV4_VIRQ_VROCIRQ0_REG 0x80
+#define DEV4_VIRQ_VROCIRQ1_REG 0x81
+#define DEV4_VIRQ_VROCIRQ2_REG 0x82
+#define DEV4_VIRQ_VROCIRQ3_REG 0x83
+#define DEV4_VIRQ_MVENDIRQLVL1_REG 0x84
+#define DEV4_VIRQ_MNVMVIRQ_REG 0x85
+#define DEV4_VIRQ_MADCTLP2VIRQ_REG 0x86
+#define DEV4_VIRQ_MI2CSIFVIRQ_REG 0x87
+#define DEV4_VIRQ_MREGBUSVIRQ_REG 0x88
+#define DEV4_VIRQ_MCHGRVIRQ_REG 0x89
+#define DEV4_VIRQ_MTLP1VIRQ_REG 0x8A
+#define DEV4_VIRQ_MDCDCVIRQ0_REG 0x8B
+#define DEV4_VIRQ_MDCDCVIRQ1_REG 0x8C
+#define DEV4_VIRQ_MVROCIRQ0_REG 0x8D
+#define DEV4_VIRQ_MVROCIRQ1_REG 0x8E
+#define DEV4_VIRQ_MVROCIRQ2_REG 0x8F
+#define DEV4_VIRQ_MVROCIRQ3_REG 0x90
+#define DEV4_VIRQ_M_VEND_INT_REG 0x91
+#define DEV4_VIRQ_VROCIRQ4_REG 0x92
+#define DEV4_VIRQ_MVROCIRQ4_REG 0x93
+#define DEV4_TEST_TST_STARTUP_REG 0x9A
+#define DEV4_TEST_TST_FREQ_DIV0_REG 0x9B
+#define DEV4_TEST_TST_FREQ_DIV1_REG 0x9C
+#define DEV4_TEST_TST_FREQ_SEL0_REG 0x9D
+#define DEV4_TEST_TST_FREQ_SEL1_REG 0x9E
+#define DEV4_TEST_TST_COUNT_CTRL0_REG 0x9F
+#define DEV4_TEST_TST_COUNT_CTRL1_REG 0xA0
+#define DEV4_TEST_TST_COUNT0_TIME_REG 0xA1
+#define DEV4_TEST_TST_COUNT1_TIME_REG 0xA2
+#define DEV4_TEST_TST_COUNT0_REG 0xA3
+#define DEV4_TEST_TST_COUNT1_REG 0xA4
+#define DEV4_TEST_TST_VINMON_REG 0xA5
+#define DEV4_TEST_TST_VINMONRSLT_REG 0xA6
+#define DEV4_TEST_TST_SRCDET0_REG 0xA7
+#define DEV4_TEST_TST_SRCDET1_REG 0xA8
+#define DEV4_TEST_TST_USB_REG 0xA9
+#define DEV4_TEST_TST_VSWITCH0_REG 0xAA
+#define DEV4_TEST_TST_VSWITCH1_REG 0xAB
+#define DEV4_TEST_VUSBPHY_CP_REG 0xAC
+#define DEV4_TEST_VUSBPHY_CP_VOUT_REG 0xAD
+#define DEV4_TEST_TST_ATE_STRTUP_REG 0xAE
+#define DEV4_TEST_GPADC_TEST0_REG 0xAF
+#define DEV4_TEST_GPADC_TEST1_REG 0xB0
+#define DEV4_TEST_GPADC_PKTST_REG 0xB1
+#define DEV4_TEST_COMPTEST0_REG 0xB2
+#define DEV4_TEST_COMPTEST1_REG 0xB3
+#define DEV4_TEST_TST_ATE_CFG_REG 0xB4
+#define DEV4_TEST_TST_ATE_REF0_REG 0xB5
+#define DEV4_TEST_TST_ATE_REF1_REG 0xB6
+#define DEV4_DEBUG_PMICSPARE01_AO_REG 0xC0
+#define DEV4_DEBUG_PMICSPARE02_AI_REG 0xC1
+#define DEV4_DEBUG_PMICSPARE03_AO_REG 0xC2
+#define DEV4_DEBUG_PMICSPARE04_AI_REG 0xC3
+#define DEV4_DEBUG_PMICSPARE05_REG 0xC4
+#define DEV4_DEBUG_PMICSPARE06_REG 0xC5
+#define DEV4_DEBUG_PMICSPARE07_REG 0xC6
+#define DEV4_DEBUG_PMICSPARE08_REG 0xC7
+#define DEV4_DEBUG_PMICSPARE09_REG 0xC8
+#define DEV4_DEBUG_PMICSPARE10_REG 0xC9
+#define DEV4_DEBUG_PMICSPARE11_REG 0xCA
+#define DEV4_DEBUG_PMICSPARE12_REG 0xCB
+#define DEV4_DEBUG_I2C_HS_TIMING_REG 0xCC
+#define DEV4_DEBUG_DBGMON1_BLK_SEL_REG 0xCD
+#define DEV4_DEBUG_DBGMON1_SIG_SEL_REG 0xCE
+#define DEV4_DEBUG_DBGMON2_BLK_SEL_REG 0xCF
+#define DEV4_DEBUG_DBGMON2_SIG_SEL_REG 0xD0
+#define DEV4_DEBUG_DBGMON3_BLK_SEL_REG 0xD1
+#define DEV4_DEBUG_DBGMON3_SIG_SEL_REG 0xD2
+#define DEV4_DEBUG_DBGMON4_BLK_SEL_REG 0xD3
+#define DEV4_DEBUG_DBGMON4_SIG_SEL_REG 0xD4
+#define DEV4_DEBUG_PMICDBGCTRL1_REG 0xD5
+#define DEV4_DEBUG_PMICDBGCTRL2_REG 0xD6
+#define DEV4_DEBUG_REGBUS_ERR_CTL_REG 0xD7
+#define DEV4_DEBUG_REGBUS_ERR_STATUS_REG 0xD8
+#define DEV4_DEBUG_REGBUS_ERR_ADDRH_REG 0xD9
+#define DEV4_DEBUG_REGBUS_ERR_ADDRL_REG 0xDA
+#define DEV4_DEBUG_ANAMON0CTL0_REG 0xDB
+#define DEV4_DEBUG_ANAMON0CTL1_REG 0xDC
+#define DEV4_DEBUG_ANAMON1CTL0_REG 0xDD
+#define DEV4_DEBUG_ANAMON1CTL1_REG 0xDE
+#define DEV4_DEBUG_VCOMPTEST_REG 0xDF
+#define DEV4_DEBUG_DBG_USBBC1_REG 0xE0
+#define DEV4_DEBUG_DBG_USBBC2_REG 0xE1
+#define DEV4_DEBUG_DBG_USBBCSTAT_REG 0xE2
+#define DEV4_DEBUG_ANAMON2CTL0_REG 0xE3
+#define DEV4_DEBUG_ANAMON2CTL1_REG 0xE4
+
+// DEV5 definitions
+
+#define DEV5_ID_ID0_REG 0x00
+#define DEV5_ID_ID1_REG 0x01
+#define DEV5_IRQ_IRQLVL1_REG 0x02
+#define DEV5_IRQ_PWRSRCIRQ_REG 0x03
+#define DEV5_IRQ_THRMIRQ0_REG 0x04
+#define DEV5_IRQ_THRMIRQ1_REG 0x05
+#define DEV5_IRQ_THRMIRQ2_REG 0x06
+#define DEV5_IRQ_BCUIRQ_REG 0x07
+#define DEV5_IRQ_ADCIRQ_REG 0x08
+#define DEV5_IRQ_CHGRIRQ_REG 0x0A
+#define DEV5_IRQ_GPIO0IRQ_REG 0x0B
+#define DEV5_IRQ_GPIO1IRQ_REG 0x0C
+#define DEV5_IRQ_MTHRMIRQ0_REG 0x0D
+#define DEV5_IRQ_MIRQLVL1_REG 0x0E
+#define DEV5_IRQ_MPWRSRCIRQ_REG 0x0F
+#define DEV5_SVID_DEV5_STATUS_1_REG 0x10
+#define DEV5_SVID_DEV5_STATUS_2_REG 0x11
+#define DEV5_IRQ_MTHRMIRQ1_REG 0x12
+#define DEV5_IRQ_MTHRMIRQ2_REG 0x13
+#define DEV5_IRQ_MBCUIRQ_REG 0x14
+#define DEV5_IRQ_MADCIRQ_REG 0x15
+#define DEV5_IRQ_MCHGRIRQ_REG 0x17
+#define DEV5_IRQ_MGPIO0IRQ_REG 0x19
+#define DEV5_IRQ_MGPIO1IRQ_REG 0x1A
+#define DEV5_SVID_DEV5_STATUS2_LASTREAD_REG 0x1C
+#define DEV5_PWRSRC_SPWRSRC_REG 0x1E
+#define DEV5_EXTCTRL_REGLOCK_REG 0x1F
+#define DEV5_RESET_RESETSRC0_REG 0x20
+#define DEV5_RESET_RESETSRC1_REG 0x21
+#define DEV5_WAKE_WAKESRC_REG 0x22
+#define DEV5_PWRSRC_LOWBATTDET0_REG 0x23
+#define DEV5_PWRSRC_LOWBATTDET1_REG 0x24
+#define DEV5_PWRSRC_PSDETCTRL_REG 0x25
+#define DEV5_PB_PBCONFIG1_REG 0x26
+#define DEV5_PB_PBSTATUS_REG 0x27
+#define DEV5_PB_UBSTATUS_REG 0x28
+#define DEV5_EXTCTRL_MODEMCTRL_REG 0x29
+#define DEV5_EXTCTRL_BBCHGRCFG_REG 0x2A
+#define DEV5_GPIO_GPIO0P0CTLO_REG 0x2B
+#define DEV5_GPIO_GPIO0P1CTLO_REG 0x2C
+#define DEV5_GPIO_GPIO0P2CTLO_REG 0x2D
+#define DEV5_GPIO_GPIO0P3CTLO_REG 0x2E
+#define DEV5_GPIO_GPIO0P5CTLO_REG 0x30
+#define DEV5_GPIO_GPIO0P6CTLO_REG 0x31
+#define DEV5_GPIO_GPIO0P0CTLI_REG 0x33
+#define DEV5_GPIO_GPIO0P2CTLI_REG 0x34
+#define DEV5_SVID_DEV5_SETREGADR_REG 0x35
+#define DEV5_GPIO_GPIO0P3CTLI_REG 0x36
+#define DEV5_IRQ_CRITIRQ_REG 0x37
+#define DEV5_GPIO_GPIO0P5CTLI_REG 0x38
+#define DEV5_GPIO_GPIO0P6CTLI_REG 0x39
+#define DEV5_GPIO_GPIO1P0CTLO_REG 0x3B
+#define DEV5_GPIO_GPIO1P1CTLO_REG 0x3C
+#define DEV5_GPIO_GPIO1P0CTLI_REG 0x43
+#define DEV5_GPIO_GPIO1P1CTLI_REG 0x44
+#define DEV5_RESET_COLDRST_REG 0x53
+#define DEV5_VREG_V1P8ACNT_REG 0x56
+#define DEV5_VREG_V1P8SXCNT_REG 0x57
+#define DEV5_VREG_VDDQCNT_REG 0x58
+#define DEV5_VREG_V1P2ACNT_REG 0x59
+#define DEV5_VREG_V1P2SXCNT_REG 0x5A
+#define DEV5_VREG_V1P8AVSEL_REG 0x5B
+#define DEV5_VREG_VDDQVSEL_REG 0x5C
+#define DEV5_VREG_V2P8SXCNT_REG 0x5D
+#define DEV5_VREG_V3P3ACNT_REG 0x5E
+#define DEV5_VREG_V3P3SDCNT_REG 0x5F
+#define DEV5_VREG_VNNCNT_REG 0x63
+#define DEV5_VREG_VCC0CNT_REG 0x64
+#define DEV5_VREG_VCC1CNT_REG 0x65
+#define DEV5_VREG_VGGCNT_REG 0x66
+#define DEV5_VREG_VSDIOCNT_REG 0x67
+#define DEV5_VREG_V3P3AVSEL_REG 0x68
+#define DEV5_VREG_VLDOCNT_REG 0x69
+#define DEV5_VREG_VSWITCHCNT0_REG 0x6A
+#define DEV5_VREG_VSWITCHCNT1_REG 0x6C
+#define DEV5_ID_FWREV_REG 0x6D
+#define DEV5_WAKE_SRCWAKECFG_REG 0x8B
+#define DEV5_VREG_VPROG1ACNT_REG 0x90
+#define DEV5_VREG_VPROG1BCNT_REG 0x91
+#define DEV5_VREG_VPROG1FCNT_REG 0x95
+#define DEV5_VREG_VPROG2DCNT_REG 0x99
+#define DEV5_VREG_VPROG3ACNT_REG 0x9A
+#define DEV5_VREG_VPROG3BCNT_REG 0x9B
+#define DEV5_VREG_VPROG4ACNT_REG 0x9C
+#define DEV5_VREG_VPROG4BCNT_REG 0x9D
+#define DEV5_VREG_VPROG4CCNT_REG 0x9E
+#define DEV5_VREG_VPROG4DCNT_REG 0x9F
+#define DEV5_VREG_VPROG5ACNT_REG 0xA0
+#define DEV5_VREG_VPROG5BCNT_REG 0xA1
+#define DEV5_VREG_VPROG6ACNT_REG 0xA2
+#define DEV5_VREG_VPROG6BCNT_REG 0xA3
+#define DEV5_VREG_VPROG7ACNT_REG 0xA4
+#define DEV5_BCU_VWARNA_CFG_REG 0xB4
+#define DEV5_BCU_VWARNB_CFG_REG 0xB5
+#define DEV5_BCU_VCRIT_CFG_REG 0xB6
+#define DEV5_BCU_BCUDISB_BEH_REG 0xB8
+#define DEV5_BCU_BCUDISCRIT_BEH_REG 0xB9
+#define DEV5_BCU_BCUVSYS_DRP_BEH_REG 0xBA
+#define DEV5_BCU_SBCUIRQ_REG 0xBB
+#define DEV5_BCU_SBCUCTRL_REG 0xBC
+#define DEV5_VREG_VPROG1AVSEL_REG 0xC0
+#define DEV5_VREG_VPROG1BVSEL_REG 0xC1
+#define DEV5_VREG_V1P8SXVSEL_REG 0xC2
+#define DEV5_VREG_V1P2SXVSEL_REG 0xC3
+#define DEV5_VREG_V1P2AVSEL_REG 0xC4
+#define DEV5_VREG_VPROG1FVSEL_REG 0xC5
+#define DEV5_VREG_VSDIOVSEL_REG 0xC6
+#define DEV5_VREG_V2P8SXVSEL_REG 0xC7
+#define DEV5_VREG_V3P3SDVSEL_REG 0xC8
+#define DEV5_VREG_VPROG2DVSEL_REG 0xC9
+#define DEV5_VREG_VPROG3AVSEL_REG 0xCA
+#define DEV5_VREG_VPROG3BVSEL_REG 0xCB
+#define DEV5_VREG_VPROG4AVSEL_REG 0xCC
+#define DEV5_VREG_VPROG4BVSEL_REG 0xCD
+#define DEV5_VREG_VPROG4CVSEL_REG 0xCE
+#define DEV5_VREG_VPROG4DVSEL_REG 0xCF
+#define DEV5_VREG_VPROG5AVSEL_REG 0xD0
+#define DEV5_VREG_VPROG5BVSEL_REG 0xD1
+#define DEV5_VREG_VPROG6AVSEL_REG 0xD2
+#define DEV5_VREG_VPROG6BVSEL_REG 0xD3
+#define DEV5_VREG_VPROG7AVSEL_REG 0xD4
+#define DEV5_IRQ_THRMIRQ3_REG 0xD9
+#define DEV5_IRQ_MTHRMIRQ3_REG 0xDA
+#define DEV5_PB_PBCONFIG2_REG 0xDB
+#define DEV5_PMON_PSOCMONCTL_REG 0xDC
+#define DEV5_PMON_PSOCRSLTH_REG 0xDD
+#define DEV5_PMON_PSOCRSLTL_REG 0xDE
+#define DEV5_PMON_SOC_PALERTH_REG 0xE3
+#define DEV5_PMON_SOC_PALERTL_REG 0xE4
+#define DEV5_WAKE_WAKESRC2_REG 0xE5
+#define DEV5_WAKE_SPLTIMER_REG 0xE6
+#define DEV5_WAKE_SSPLTIMER_REG 0xE7
+#define DEV5_PWRSRC_BATTDETCTRL0_REG 0xF0
+#define DEV5_PWRSRC_BATTDETCTRL1_REG 0xF1
+#define DEV5_EXTCTRL_SOCCTRL_REG 0xF8
+#define DEV5_IRQ_MCRITIRQ_REG 0xFA
+#define DEV5_BCU_ICCMAXVCC_CFG_REG 0xFB
+#define DEV5_BCU_ICCMAXVNN_CFG_REG 0xFC
+#define DEV5_BCU_ICCMAXVGG_CFG_REG 0xFD
+#define DEV5_IRQ_MSVIDALERT_REG 0xFE
+
+/*
+USB Type C PD controller I2C and register definitions
+ToDo -- Move to EM code space
+*/
+
+#define USB_TYPEC_PD_CHANNEL_NUMBER 0x0
+#define USB_TYPEC_PD_SLAVE_ADDRESS 0x22
+#define USB_TYPEC_PD_POWER_REG 0x0B
+#define USB_TYPEC_PD_SWITCH0_REG 0x02
+#define USB_TYPEC_PD_MASK0_REG 0x0A
+#define USB_TYPEC_PD_STS_REG 0x40
+#define USB_TYPEC_PD_INTR_REG 0x42
+
+typedef struct _WC_PMIC_CONFIGURATION {
+ UINT8 Offset;
+ UINT8 Value;
+}WC_PMIC_CONFIGURATION;
+
+EFI_STATUS ConfigureWcPmicDev2();
+
+EFI_STATUS ConfigureWcPmicDev5();
+
+/*
+For DDR3L memory
+Sequence needs to happen before MRC init.
+
+Write to DEV5_VDDQVSEL_REG to change voltage from 1.24V to 1.35V.
+->Write 0x6E to offset 0x5C
+Enable V1P2A LDO
+->Write 0x01 to DEV_V1P2ACNT_REG
+*/
+EFI_STATUS
+EFIAPI
+VGGWrite (
+ IN UINT8 Register,
+ IN UINT8 Value
+ );
+
+UINT8
+EFIAPI
+WcPmicRead8 (
+ IN UINT8 Register
+ );
+
+EFI_STATUS
+EFIAPI
+WcPmicWrite8 (
+ IN UINT8 Register,
+ IN UINT8 Value
+ );
+
+EFI_STATUS
+EFIAPI
+WcPmicThermInit (void);
+
+EFI_STATUS
+EFIAPI
+WcPmicGpioInit (void);
+
+EFI_STATUS
+EFIAPI
+WcPmicIntrInit (void);
+
+EFI_STATUS
+EFIAPI
+WcPmicBcuInit (void);
+
+EFI_STATUS
+EFIAPI
+WcPmicMiscInit (void);
+
+EFI_STATUS
+EFIAPI
+WcPmicPage0Init (void *Profile);
+
+UINT8
+EFIAPI
+WcPmicRead8_page0 (
+ IN UINT8 Register
+ );
+
+EFI_STATUS
+EFIAPI
+WcPmicWrite8_page0 (
+ IN UINT8 Register,
+ IN UINT8 Value
+ );
+
+EFI_STATUS
+EFIAPI
+WcPmicVbusControl (BOOLEAN bTurnOn);
+
+EFI_STATUS
+EFIAPI
+WcPmicVhostControl (BOOLEAN bTurnOn);
+
+EFI_STATUS
+EFIAPI
+WcPmicGetDevID (UINT8 *DevId, UINT8 *RevId);
+
+UINT16
+EFIAPI
+WcPmicGetBATID (void);
+
+UINT8
+EFIAPI
+WcPmicGetBoardID(void);
+
+UINT8
+EFIAPI
+WcPmicGetMemCfgID(void);
+
+UINT8
+EFIAPI
+WcPmicGetFABID(void);
+
+UINT16
+EFIAPI
+WcPmicGetVBAT (void);
+
+BOOLEAN
+EFIAPI
+WcPmicIsACOn (void);
+
+BOOLEAN
+EFIAPI
+WcPmicIsPwrBtnPressed(void);
+
+BOOLEAN
+EFIAPI
+WcPmicIsUIBtnPressed(void);
+
+UINT16
+EFIAPI
+WcPmicGetResetCause (void);
+
+VOID
+EFIAPI
+WcPmicClearResetCause (void);
+
+EFI_STATUS
+EFIAPI
+WcPmicGetWakeCause (IN OUT UINT8 *WakeCause);
+
+VOID
+EFIAPI
+WcPmicClearWakeCause (void);
+
+EFI_STATUS
+EFIAPI
+WcPmicDebugRegDump (void);
+
+BOOLEAN
+EFIAPI
+WcPmicIsUsbConnected (void);
+
+BOOLEAN
+EFIAPI
+WcPmicIsBatOn (void);
+
+EFI_STATUS
+EFIAPI
+WcPmicSetVDDQ (void);
+
+EFI_STATUS
+EFIAPI
+WcPmicGpioToggleForLpcConfig(void);
+
+VOID
+WcPmicForceOffModem (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+WcPmicBatchRegisterInit (
+ IN RegInit_st *RegInit,
+ IN UINT32 length
+ );
+
+EFI_STATUS
+EFIAPI
+WcPmicSetVIDDecayWA (void);
+
+VOID
+WcProgramPunitPwrConfigRegisters (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+WcPmicNVMUpdate(void);
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/Pmic_CrcPlus.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/Pmic_CrcPlus.h new file mode 100644 index 0000000000..f509eed632 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/Pmic_CrcPlus.h @@ -0,0 +1,315 @@ +/** @file
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PMIC_REG_CC_P_H_
+#define _PMIC_REG_CC_P_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/I2CLib.h>
+#include <Library/PmicLib.h>
+#include <Library/TimerLib.h>
+#include <Library/PcdLib.h>
+
+#include "PmicReg.h"
+#include "ChvAccess.h"
+#include <Guid/PlatformInfo.h>
+
+#define DELAY_BETWEEN_INSTRUCTION_1 50
+#define DELAY_BETWEEN_INSTRUCTION 10
+#define R_PMIC_PBCONFIG 0x26
+#define MASK_PMIC_PB_DISABLE 0xf0 //disable power button
+#define MASK_PBCONFIG_FCOT 0x0f //last 4 bits corresponds to FCOT
+
+RegInit_st g_Diaglog_ThermRegInit[]=
+{
+ {PMIC_REG_SYS0_THRMALRT0_H, REG_OVERRIDE, 0xFF, 0x4C},
+ {PMIC_REG_SYS0_THRMALRT0_L, REG_OVERRIDE, 0xFF, 0x0},
+ {PMIC_REG_SYS0_THRMALRT1_H, REG_OVERRIDE, 0xFF, 0x4C},
+ {PMIC_REG_SYS0_THRMALRT1_L, REG_OVERRIDE, 0xFF, 0x00},
+
+ {PMIC_REG_SYS1_THRMALRT0_H, REG_OVERRIDE, 0xFF, 0x4C},
+ {PMIC_REG_SYS1_THRMALRT0_L, REG_OVERRIDE, 0xFF, 0x0},
+ {PMIC_REG_SYS1_THRMALRT1_H, REG_OVERRIDE, 0xFF, 0x4C},
+ {PMIC_REG_SYS1_THRMALRT1_L, REG_OVERRIDE, 0xFF, 0x0},
+
+ {PMIC_REG_SYS2_THRMALRT0_H, REG_OVERRIDE, 0xFF, 0xCD}, // A0_P/A0_Alert/67 C
+ {PMIC_REG_SYS2_THRMALRT0_L, REG_OVERRIDE, 0xFF, 0x08},
+ {PMIC_REG_SYS2_THRMALRT1_H, REG_OVERRIDE, 0xFF, 0x4C},
+ {PMIC_REG_SYS2_THRMALRT1_L, REG_OVERRIDE, 0xFF, 0x0},
+
+ {PMIC_REG_TS_ENABLE, REG_OVERRIDE, 0xFF, 0x3f}, //enable all thermsistors
+};
+RegInit_st g_Rohm_ThermRegInit[]=
+{
+ {PMIC_REG_SYS0_THRMALRT3_H, REG_OVERRIDE, 0xFF, 0xCD}, // the values are from Peter on B0 PO
+ {PMIC_REG_SYS0_THRMALRT3_L, REG_OVERRIDE, 0xFF, 0x08}, // enabled but threshold is 0
+ {PMIC_REG_SYS0_THRMALRT1_H, REG_OVERRIDE, 0xFF, 0x4C}, //
+ {PMIC_REG_SYS0_THRMALRT1_L, REG_OVERRIDE, 0xFF, 0x00},
+
+ {PMIC_REG_SYS1_THRMALRT3_H, REG_OVERRIDE, 0xFF, 0x4C},
+ {PMIC_REG_SYS1_THRMALRT3_L, REG_OVERRIDE, 0xFF, 0x00},
+ {PMIC_REG_SYS1_THRMALRT1_H, REG_OVERRIDE, 0xFF, 0x4C},
+ {PMIC_REG_SYS1_THRMALRT1_L, REG_OVERRIDE, 0xFF, 0x00},
+
+ {PMIC_REG_SYS2_THRMALRT3_H, REG_OVERRIDE, 0xFF, 0x4C}, // A0_P/A0_Alert/67 C
+ {PMIC_REG_SYS2_THRMALRT3_L, REG_OVERRIDE, 0xFF, 0x00},
+ {PMIC_REG_SYS2_THRMALRT1_H, REG_OVERRIDE, 0xFF, 0x4C},
+ {PMIC_REG_SYS2_THRMALRT1_L, REG_OVERRIDE, 0xFF, 0x00},
+
+ {PMIC_REG_BAT0_THRMALRT3_H, REG_OVERRIDE, 0xFF, 0x3D}, // battery #0 alert0 50C (disabled)
+ {PMIC_REG_BAT0_THRMALRT3_L, REG_OVERRIDE, 0xFF, 0x97},
+ {PMIC_REG_BAT0_THRMALRT1_H, REG_OVERRIDE, 0xFF, 0x3D}, // alert 1:45C
+ {PMIC_REG_BAT0_THRMALRT1_L, REG_OVERRIDE, 0xFF, 0xCA},
+ {PMIC_REG_BAT0_THRMCRIT_H, REG_OVERRIDE, 0xFF, 0x6A}, // 75C
+ {PMIC_REG_BAT0_THRMCRIT_L, REG_OVERRIDE, 0xFF, 0xF0}, //-55C
+
+ {PMIC_REG_BAT1_THRMALRT3_H, REG_OVERRIDE, 0xFF, 0x3D}, //disabled
+ {PMIC_REG_BAT1_THRMALRT3_L, REG_OVERRIDE, 0xFF, 0x97},
+ {PMIC_REG_BAT1_THRMALRT1_H, REG_OVERRIDE, 0xFF, 0x3D},
+ {PMIC_REG_BAT1_THRMALRT1_L, REG_OVERRIDE, 0xFF, 0xCA},
+ {PMIC_REG_BAT1_THRMCRIT_H, REG_OVERRIDE, 0xFF, 0x6A},
+ {PMIC_REG_BAT1_THRMCRIT_L, REG_OVERRIDE, 0xFF, 0xF0},
+
+ {PMIC_REG_PMIC_THRMALRT3_H, REG_OVERRIDE, 0xFF, 0xFE}, // 110C
+ {PMIC_REG_PMIC_THRMALRT3_L, REG_OVERRIDE, 0xFF, 0x17},
+ {PMIC_REG_PMIC_THRMALRT1_H, REG_OVERRIDE, 0xFF, 0x7E}, // 100C
+ {PMIC_REG_PMIC_THRMALRT1_L, REG_OVERRIDE, 0xFF, 0x2A},
+ {PMIC_REG_PMIC_THRMCRIT, REG_OVERRIDE, 0xFF, 0xFF}, // 123C overflow MSB1 bit in the design. so only value higher than 123 is acceptable.
+
+ {PMIC_REG_TS_ENABLE, REG_OVERRIDE, 0xFF, 0x3F}, // Enable all thermistors
+
+ {PMIC_REG_THRMMONCTL0, REG_OVERRIDE, 0xFF, 0xB}, //enable thermal automatic monitoring timer, 1s sample interval
+};
+
+GpioCfg_st g_GPIO_cfg[]= {
+ {"GPIO0P0", PMIC_REG_GPIO0P0CTLO, PMIC_REG_GPIO0P0CTLI, DIR_INPUT, INTERRUPT_EN, (PMIC_MASK_DRV|PMIC_MASK_REN|PMIC_MASK_RVAL_50K_PU), (PMIC_MASK_GPIDBNC|PMIC_MASK_INTCNT_BOTH) },//"Volumn up" (debounce enable)
+ {"GPIO0P1", PMIC_REG_GPIO0P1CTLO, PMIC_REG_GPIO0P1CTLI, DIR_INPUT, INTERRUPT_EN, (PMIC_MASK_DRV|PMIC_MASK_REN|PMIC_MASK_RVAL_50K_PU), (PMIC_MASK_GPIDBNC|PMIC_MASK_INTCNT_BOTH) },//"Volumn down" (debounce enable)
+
+ {"GPIO1P0", PMIC_REG_GPIO1P0CTLO, PMIC_REG_GPIO1P0CTLI, DIR_INPUT, INTERRUPT_EN, (PMIC_MASK_DRV|PMIC_MASK_REN|PMIC_MASK_RVAL_50K_PU|PMIC_MASK_ALTFUNCEN), (PMIC_MASK_GPIDBNC|PMIC_MASK_INTCNT_BOTH) }, //enable altfunc "UIBTN_B" home screen (debounce enable)
+};
+
+GpioCfg_st g_Pmic_Gpio_Lpc_Cfg[]= {
+ {"GPIO1P1", PMIC_REG_GPIO1P1CTLO, PMIC_REG_GPIO1P1CTLI, DIR_OUTPUT, INTERRUPT_DIS, (PMIC_MASK_DRV|PMIC_MASK_RVAL_50K_PD|PMIC_MASK_DIR), (PMIC_MASK_GPIDBNC|PMIC_MASK_INTCNT_BOTH) },//PMIC_GPIO_1_LPC GPO low 0x3c:0x34
+
+};
+
+RegInit_st g_IntrRegInit[]=
+{
+ {PMIC_REG_MGPIO0IRQS0, REG_OVERRIDE, 0xff, 0xff}, //disable all GPIO interrupts
+ {PMIC_REG_MGPIO1IRQS0, REG_OVERRIDE, 0xff, 0xff},
+ {PMIC_REG_MGPIO0IRQSX, REG_OVERRIDE, 0xff, 0xff},
+ {PMIC_REG_MGPIO1IRQSX, REG_OVERRIDE, 0xff, 0xff},
+ {PMIC_REG_MADCIRQ0, REG_OVERRIDE, 0xff, 0xff},
+ {PMIC_REG_MADCIRQ1, REG_OVERRIDE, 0x1f, 0x1f},
+ {PMIC_REG_MCHGRIRQS0, REG_CLEAR, PMIC_MASK_MCHGR, PMIC_MASK_MCHGR}, //enable external charger interrupt
+ {PMIC_REG_MCHGRIRQSX, REG_CLEAR, PMIC_MASK_MCHGR, PMIC_MASK_MCHGR}, //enable external charger interrupt
+ {PMIC_REG_MPWRSRCIRQS0, REG_CLEAR, (PMIC_MASK_BATDET|PMIC_MASK_DCINDET|PMIC_MASK_VBUSDET), (PMIC_MASK_BATDET|PMIC_MASK_DCINDET|PMIC_MASK_VBUSDET) }, //enable power src interrupt
+ {PMIC_REG_MPWRSRCIRQSX, REG_CLEAR, (PMIC_MASK_BATDET|PMIC_MASK_DCINDET|PMIC_MASK_VBUSDET), (PMIC_MASK_BATDET|PMIC_MASK_DCINDET|PMIC_MASK_VBUSDET) },
+ {PMIC_REG_MIRQLVL1, REG_OVERRIDE, PMIC_MASK_ALL_IRQ, (PMIC_MASK_MPWRSRC|PMIC_MASK_MCHGRINT|PMIC_MASK_MADC|PMIC_MASK_MGPIO)}, //only enable 4kinds of intrs
+ {PMIC_REG_MTHRMIRQ0, REG_OVERRIDE, 0xff, 0xff}, //disable all THerm intrs
+ {PMIC_REG_MTHRMIRQ1, REG_OVERRIDE, 0xf, 0xf},
+ {PMIC_REG_MTHRMIRQ2, REG_OVERRIDE, 0x3f, 0x3f},
+
+ {PMIC_REG_GPIO0IRQ, REG_OVERRIDE, 0xff, 0xff}, //write clear
+ {PMIC_REG_GPIO1IRQ, REG_OVERRIDE, 0xff, 0xff},
+};
+
+RegInit_st g_BcuRegInit[]=
+{
+ {PMIC_REG_VWARNA_CFG, REG_CLEAR, PMIC_MASK_VWARNA_EN, PMIC_MASK_VWARNA_EN}, //TODO: require meaningful value from HW teams
+ {PMIC_REG_VWARNB_CFG, REG_CLEAR, PMIC_MASK_VWARNB_EN, PMIC_MASK_VWARNB_EN}, //disable VWENB
+ {PMIC_REG_VCRIT_CFG, REG_CLEAR, PMIC_MASK_VCRIT_EN, PMIC_MASK_VCRIT_EN}, //disable VCRIT
+ {PMIC_REG_BCUDISA_BEH, REG_OVERRIDE, 0x0, 0x0},
+ {PMIC_REG_BCUDISB_BEH, REG_OVERRIDE, 0x0, 0x0},
+ {PMIC_REG_BCUDISCRIT_BEH, REG_OVERRIDE, 0x0, 0x0},
+ {PMIC_REG_BCUPROCHOT_B_BEH,REG_OVERRIDE, 0x0, 0x0},
+ {PMIC_REG_MBCUIRQ, REG_OVERRIDE, PMIC_MASK_MBCU_ALL, PMIC_MASK_MBCU_ALL }, //mask all
+};
+
+RegInit_st g_MiscRegInit[]=
+{
+ // V2P8SX rail drops to 2.56V with Camera enabled. The voltage is at 2.8v on startup and drops to 2.56V when the camera is brought out of reset.
+ // PMIC_REG_V1P8SXCNT = 0x5D : The default and correct value is 011 for 2.8V. We are overriding the values.
+ {PMIC_REG_VBUSCNT, REG_OVERRIDE, PMIC_VR_SEL_BIT | PMIC_VR_EN_BIT, PMIC_VR_SEL_BIT | PMIC_VR_EN_BIT}, //0-VBUS_EN is controlled by ULPI_VBUS_EN
+ {PMIC_REG_VHDMICNT, REG_OVERRIDE, PMIC_VR_SEL_BIT | PMIC_VR_EN_BIT, PMIC_VR_SEL_BIT | PMIC_VR_EN_BIT}, //0-VBUS_EN is controlled by ULPI_VBUS_EN
+ {PMIC_REG_GPIO0P3CTLO,REG_OVERRIDE, 0xFF, 0x21}, //for PMIC audio reset GPIO
+ {PMIC_REG_V3P3SXCNT, REG_OVERRIDE, PMIC_VR_EN_BIT | PMIC_VR_LPEN_BIT | BIT7 | BIT6 | BIT5, PMIC_VR_EN_BIT | PMIC_VR_LPEN_BIT | BIT6 | BIT5},
+};
+
+UINT8
+EFIAPI
+CrcPlusPmicRead8 (
+ IN UINT8 Register
+ );
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicWrite8 (
+ IN UINT8 Register,
+ IN UINT8 Value
+ );
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicThermInit (void);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicGpioInit (void);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicIntrInit (void);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicBcuInit (void);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicMiscInit (void);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicPage0Init (void *Profile);
+
+UINT8
+EFIAPI
+CrcPlusPmicRead8_page0 (
+ IN UINT8 Register
+ );
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicWrite8_page0 (
+ IN UINT8 Register,
+ IN UINT8 Value
+ );
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicVbusControl (BOOLEAN bTurnOn);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicVhostControl (BOOLEAN bTurnOn);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicGetDevID (UINT8 *DevId, UINT8 *RevId);
+
+UINT16
+EFIAPI
+CrcPlusPmicGetBATID (void);
+
+UINT8
+EFIAPI
+CrcPlusPmicGetBoardID(void);
+
+UINT8
+EFIAPI
+CrcPlusPmicGetMemCfgID(void);
+
+UINT8
+EFIAPI
+CrcPlusPmicGetFABID(void);
+
+UINT16
+EFIAPI
+CrcPlusPmicGetVBAT (void);
+
+BOOLEAN
+EFIAPI
+CrcPlusPmicIsACOn (void);
+
+BOOLEAN
+EFIAPI
+CrcPlusPmicIsPwrBtnPressed(void);
+
+BOOLEAN
+EFIAPI
+CrcPlusPmicIsUIBtnPressed(void);
+
+UINT16
+EFIAPI
+CrcPlusPmicGetResetCause (void);
+
+VOID
+EFIAPI
+CrcPlusPmicClearResetCause (void);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicGetWakeCause (IN OUT UINT8 *WakeCause);
+
+VOID
+EFIAPI
+CrcPlusPmicClearWakeCause (void);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicDebugRegDump (void);
+
+BOOLEAN
+EFIAPI
+CrcPlusPmicIsUsbConnected (void);
+
+BOOLEAN
+EFIAPI
+CrcPlusPmicIsBatOn (void);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicSetVDDQ (void);
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicGpioToggleForLpcConfig(void);
+
+VOID
+CrcPlusPmicModemWa(void);
+
+VOID
+CrcPlusPmicForceOffModem (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicBatchRegisterInit (
+ IN RegInit_st *RegInit,
+ IN UINT32 length
+ );
+
+EFI_STATUS
+EFIAPI
+CrcPlusPmicSetVIDDecayWA (void);
+
+VOID
+CrcPlusProgramPunitPwrConfigRegisters (
+ VOID
+ );
+
+EFI_STATUS
+CrcPlusPmicDisablePowerButton(
+ OUT UINT8 *ButtonHoldTime
+);
+
+EFI_STATUS
+CrcPlusPmicEnablePowerButton (
+ IN UINT8 ButtonHoldTime
+);
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/Pmic_DollarCove_TI.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/Pmic_DollarCove_TI.h new file mode 100644 index 0000000000..88dfb31233 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/Pmic_DollarCove_TI.h @@ -0,0 +1,173 @@ +/** @file
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PMIC_REG_TIDC_P_H_
+#define _PMIC_REG_TIDC_P_H_
+
+#define PMIC_DEV_TI (0x3<<6) //b'11
+#define PMIC_TI_MAJOR_PG10 (0x0<<3)
+#define PMIC_TI_MAJOR_PG20 (0x1<<3)
+
+#define PMIC_TI_I2C_SLAVE_ADDR_1 0x5C //7bits address
+#define PMIC_TI_I2C_SLAVE_ADDR_2 0x5D
+#define PMIC_TI_I2C_SLAVE_ADDR_3 0x5E //default from SPEC
+#define PMIC_TI_I2C_SLAVE_ADDR_4 0x5F
+
+#define PMIC_TI_I2C_1_SLAVE_ADDR_0 0x6B
+#define PMIC_TI_I2C_1_SLAVE_ADDR_1 0x68
+
+#define PMIC_TI_I2C_BUS_NO 0x2
+
+#define TI_POWERSRC_AND_CHARGER_STATUS 0x12
+
+#define USB3750_ADDR 0x68
+#define USB3750_CHRG_TYPE_REG 0x0
+
+#define TI_BATTERY_BPTH_VALID 0x380
+
+//Charger
+#define CHG_TI_BQ24296_REG0 0x00
+#define CHG_TI_BQ24296_REG1 0x01
+#define CHG_TI_BQ24296_REG2 0x02
+#define CHG_TI_BQ24296_REG3 0x03
+#define CHG_TI_BQ24296_REG4 0x04
+#define CHG_TI_BQ24296_REG5 0x05
+#define CHG_TI_BQ24296_REG6 0x06
+#define CHG_TI_BQ24296_REG7 0x07
+#define CHG_TI_BQ24296_REG8 0x08
+#define CHG_TI_BQ24296_REG9 0x09
+#define CHG_TI_BQ24296_REG10 0x0A
+//FuelGauge
+#define TI_BATT_CAPACITY 5100
+#define REG_TI_MIRQ_ADDR 0x02 //MIRQ Register
+#define REG_TI_ADCCTRL_ADDR 0x50 //ADC Control Register
+#define REG_TI_VBATLO_ADDR 0x55 //VBATLO
+#define REG_TI_VBATHI_ADDR 0x54 //VBATHigh
+#define REG_TI_DITEMPHI_ADDR 0x56 //Die Temp High
+#define REG_TI_BPTEMPHI_ADDR 0x58 //BP Temp High
+#define REG_TI_GPTEMPHI_ADDR 0x5A //GP ADC High
+#define REG_TI_IRQ_ADDR 0x01 //IRQ Register
+#define REG_TI_BPTHREMHI 0x58 //BPTHERM High
+#define REG_TI_BPTHERMLO 0x59 //BPTHERM Low
+#define REG_TI_CC_CTRL 0x60 //CC Control
+
+#define REG_TI_CC_ACC_BYT0 0x66 //CC accumulator Reg.
+#define REG_TI_CC_ACC_BYT1 0x65 //CC accumulator Reg.
+#define REG_TI_CC_ACC_BYT2 0x64 //CC accumulator Reg.
+#define REG_TI_CC_ACC_BYT3 0x63 //CC accumulator Reg.
+
+#define REG_TI_CC_SMPL_BYT0 0x69 //CC Sample counter BYTE
+#define REG_TI_CC_SMPL_BYT1 0x68 //CC Sample counter BYTE
+#define REG_TI_CC_SMPL_BYT2 0x67 //CC Sample counter BYTE
+
+#define REG_TI_CC_INTG1_BYT1 0x6A //CC integrator Register MSB (0:5,6-7 = rsvd)
+#define REG_TI_CC_INTG1_BYT0 0x6B //CC integrator Register LSB
+
+#define EEPROM_ACCESS_CTRL 0x88
+#define EEPROM_REG20 0xF3 // 4:7 : CC offset
+#define EEPROM_GAIN_REG 0xF4 // 4:7 : CC gain
+#define OFFSET_REG_TRIM_REV_3 0xFD
+#define TRIM_REV_3_OFFSET_STEP 1
+#define DEFAULT_CC_OFFSET_STEP 2
+#define DEFAULT_CC_OFFSET_SHIFT 0
+#define TRIM_REV_3_OFFSET_SHIFT 1
+
+#define EEPROM_CTRL 0xFE
+#define EEPROM_CTRL_EEPSEL 0x3
+#define EEPROM_CTRL_EEPSEL_MASK 0x03
+#define EEPROM_BANK0_SEL 0x01
+#define EEPROM_BANK1_SEL 0x02
+
+#define REG_TI_ADCVBATZSEGE 0x53 //Data Register for ADC Calibration
+#define REG_TI_ADCVBATZSEGE_SHIFT 4
+
+#define SMPL_INTVL 0x03
+#define CURRENT_GAIN 366 //TBD from hw team, Rsens = 10 gain = 0.366, Rsens = 20 gain = 0.1831
+ //Rsens = 30, gain = 0.122066667
+#define MAX_CC_SCALE 3662 /*CC Accumulator Bit unit 3.662uV/10mohm */
+#define CC_SMPL_CTR_MAX_VAL 0xFFFFFF
+#define CC_CNTL_CC_CTR_EN BIT0
+#define CC_CNTL_CC_CLR_EN BIT1
+#define CC_CNTL_CC_CAL_EN BIT2
+#define CC_CNTL_CC_OFFSET_EN BIT3
+#define CC_CNTL_SMPL_INTVL (BIT4 | BIT5) //TODO: Check with hw for sample interval
+#define CC_GAIN_STEP 25
+#define DEFAULT_CC_OFFSET_STEP 2
+#define TRIM_REV_3_OFFSET_STEP 1
+
+//
+// 0x01- SDP
+// 0x02- CDP
+// 0x03- DCP
+// 0x04- ACA
+// 0x05- Unknow or Other Charger Type
+//
+#define CHG_SDP 0x01
+#define CHG_CDP 0x02
+#define CHG_DCP 0x03
+#define CHG_ACA 0x04
+#define CHG_UNKNW 0x05
+//ADC Channel
+#define CH_VBAT 0
+#define CH_DIETEMP 1
+#define CH_BPTHERM 2
+#define CH_GPADC 3
+
+//Following two macros return TRUE(1) if bit is set/cleared
+#define ISBITSET(var,bitpos) ((var & (1<<bitpos))>>bitpos)
+#define ISBITCLR(var,bitpos) (~(var | (~(1<<bitpos)))>>bitpos)
+
+#define BITSET(Data,BitPos) Data |= (1<<BitPos)
+#define BITCLR(Data,BitPos) Data &= ~(1<<BitPos)
+#define BITINV(Data,BitPos) Data ^= (1<<BitPos)
+
+//Get structure offset - Pass sturcuture name and element name as parameter
+#define OFFSETOF_STURCT(STRUCTURE,ELEMENT) ((int) (&(((STRUCTURE*)(0))->ELEMENT)))
+#define CONVERT8to16BIT(Lsb,Msb,Result) Result = (UINT16) (Lsb | ((UINT16)(Msb << 8)))
+#define CONVERT8to32BIT(BYT0,BYT1,BYT2,BYT3,Result) Result = (UINT32)(BYT0 | ((UINT32)(BYT1 << 8)) | ((UINT32)(BYT2 << 16)) | ((UINT32)(BYT3 << 24)))
+#define CONVERT8to24BIT(BYT0,BYT1,BYT2,Result) Result = (UINT32)(BYT0 | ((UINT32)(BYT1 << 8)) | ((UINT32)(BYT2 << 16)))
+
+static void ResetSemaphore(void);
+
+void SendDoorBellToPunit(void);
+
+EFI_STATUS
+EFIAPI
+AcquireOwnership(void);
+
+EFI_STATUS
+EFIAPI
+ReleaseOwnership(void);
+
+EFI_STATUS
+EFIAPI
+TiPmicDVFSInit(void);
+
+EFI_STATUS
+EFIAPI
+TiReadEeprom(void);
+
+EFI_STATUS
+EFIAPI
+TiReadOffsetGainCompensation(void);
+
+UINT16
+EFIAPI
+TiPmicGetCorrectedVoltage(void);
+
+#define DIV_ROUND_CLOSEST(x, divisor) \
+ (x > 0) ? ((x + divisor / 2) / divisor) : ((x - divisor / 2) / divisor)
+
+#endif
+
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/Pmic_DollarCove_XPOWERS.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/Pmic_DollarCove_XPOWERS.h new file mode 100644 index 0000000000..e1b042dcc5 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/PmicLib/Pmic_DollarCove_XPOWERS.h @@ -0,0 +1,121 @@ +/** @file
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PMIC_REG_DCX_P_H_
+#define _PMIC_REG_DCX_P_H_
+
+#define PMIC_DC_X_I2C_BUSNO 6 //I2C6 is used. index from 0
+#define PMIC_DC_X_I2C_ADDR 0x34
+#define PMIC_DEV_DC_XPOWERS 0x41 // bit 7-6 & bit 3-0: 010001: IC is AXP288
+
+#define USB3750_ADDR 0x68
+#define USB3750_CHRG_TYPE_REG 0x0
+
+#define XPOWER_POWERSRC_AND_CHARGER_STATUS 0x02
+#define XPOWER_REG_SOC 0xB9 // Bit 7=soc is valid(1) or not valid(0)
+ // BIT 0 - 6 = SOC in %
+#define XPOWER_REG_MAXCAP1 0xE0 // Bit 7=Capacity is valid(1) or not valid(0)
+ // BIT 0 - 6 = Batt max capacity bit[14:8]
+#define XPOWER_REG_MAXCAP2 0xE1 // BIT 0 - 7 = Batt max capacity bit[7:0] multiply by 1.456mah
+#define XPOWER_REG_VOLTAGE1 0x78 // BIT[11:4]
+#define XPOWER_REG_VOLTAGE2 0x79 // BIT[3:0] = rsvd, BIT[7:4] = [3:0]
+#define XPOWER_REG_CHG_CU1 0x7A // BIT 0- 7 = Charging current [11:4]
+#define XPOWER_REG_CHG_CU2 0x7B // BIT 0- 3 =RSVD, 4-7 = Charging current [3:0] multiply by 1ma
+#define XPOWER_REG_DISCHG_CU1 0x7C // BIT 0- 7 = Charging current [11:4]
+#define XPOWER_REG_DISCHG_CU2 0x7D // BIT 0- 3 =RSVD, 4-7 = Charging current [3:0] multiply by 1ma
+#define XPOWER_REG_CHR_TYP 0x2F // BIT 0 - 4 = Reserved, 7-5 = chg src (01 = SDP, 02 = CPD, 03 = DCP)
+#define XPOWER_REG_CHG_STS 0x01 // BIT6 = Charging Indication, BIT5 = Battery pres
+#define XPOWER_BATT_CAPACITY 5100
+#define XPOWER_BATT_CHG_CNTL 0x2C //BIT 0 intiate charging
+#define XPOWER_BATT_ILIM 0x30 //30[0:1] : ilim
+#define XPOWER_BATT_ICHG 0x33 //33[3:0] : Ichg
+#define XPOWER_VBUS_CLIM_SET 0x35 //35[7:4] : vbus current limit set
+
+//DollarCove XPOWER FG Characterization data Provided by FG Mfg
+//This Registers 0xC0-0xDF is OCV Percentage Table ( Refer AXP288 Datasheet for more detail )
+//Characterization Start ----->
+#define XPOWER_FG_OCV_C0 00
+#define XPOWER_FG_OCV_C1 00
+#define XPOWER_FG_OCV_C2 00
+#define XPOWER_FG_OCV_C3 00
+#define XPOWER_FG_OCV_C4 00
+#define XPOWER_FG_OCV_C5 00
+
+#define XPOWER_FG_OCV_C6 01
+#define XPOWER_FG_OCV_C7 01
+#define XPOWER_FG_OCV_C8 02
+#define XPOWER_FG_OCV_C9 03
+#define XPOWER_FG_OCV_CA 04
+
+#define XPOWER_FG_OCV_CB 11
+#define XPOWER_FG_OCV_CC 17
+#define XPOWER_FG_OCV_CD 25
+#define XPOWER_FG_OCV_CE 37
+#define XPOWER_FG_OCV_CF 42
+#define XPOWER_FG_OCV_D0 45
+
+#define XPOWER_FG_OCV_D1 49
+#define XPOWER_FG_OCV_D2 52
+#define XPOWER_FG_OCV_D3 57
+#define XPOWER_FG_OCV_D4 61
+#define XPOWER_FG_OCV_D5 65
+#define XPOWER_FG_OCV_D6 68
+
+#define XPOWER_FG_OCV_D7 71
+#define XPOWER_FG_OCV_D8 75
+#define XPOWER_FG_OCV_D9 78
+
+#define XPOWER_FG_OCV_DA 80
+#define XPOWER_FG_OCV_DB 82
+#define XPOWER_FG_OCV_DC 86
+#define XPOWER_FG_OCV_DD 91
+#define XPOWER_FG_OCV_DE 95
+#define XPOWER_FG_OCV_DF 100
+
+#define BATRDC 75 //mO
+#define BATCAP 10164 //mAh
+
+#define BATTERY_MAX_CAP_HI (0x80|(((BATCAP*1000/1456)>>8)&0X7F))
+#define BATTERY_MAX_CAP_LO ((BATCAP*1000/1456)&0xFF)
+
+#define BATTERY_RDC1 (0xC0|((((BATRDC*10000+5371)/10742)>>8)&0x1F))
+#define BATTERY_RDC0 (((BATRDC*10000+5371)/10742)&0xFF)
+
+#define XPOWER_BATTERY_BPTH_VALID 0x0F00
+
+//Characterization Table End <-----------
+
+#define DC_X_PMIC_REG_VR_CTRL_DLDO1 0x15
+#define DC_X_PMIC_REG_VR_CTRL_DLDO2 0x16
+#define DC_X_PMIC_REG_VR_CTRL_DLDO3 0x17
+#define DC_X_PMIC_REG_VR_CTRL_DLDO4 0x18
+#define DC_X_PMIC_REG_VR_CTRL_ELDO1 0x19
+#define DC_X_PMIC_REG_VR_CTRL_ELDO2 0x1A
+#define DC_X_PMIC_REG_VR_CTRL_ELDO3 0x1B
+#define DC_X_MASK_ELDO_VOL_18 (BIT04|BIT02|BIT01)
+
+EFI_STATUS
+EFIAPI
+AcquireOwnership(void);
+
+EFI_STATUS
+EFIAPI
+ReleaseOwnership(void);
+
+EFI_STATUS
+EFIAPI
+DcXPmicDVFSInit(void);
+
+#endif
+
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/SpiHostPlatform.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/SpiHostPlatform.h new file mode 100644 index 0000000000..4067edf138 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Include/Library/SpiHostPlatform.h @@ -0,0 +1,33 @@ +/** @file
+ Declare the platform requirements for the SPI controller
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SPI_PORT_H
+#define _SPI_PORT_H
+
+//------------------------------------------------------------------------------
+// Types
+//------------------------------------------------------------------------------
+
+//
+// Context passed from platform (board) layer to the SPI port driver.
+//
+typedef struct {
+ EFI_PHYSICAL_ADDRESS BaseAddress;
+ UINT32 InputFrequencyHertz;
+} SPI_PLATFORM_CONTEXT;
+
+//------------------------------------------------------------------------------
+
+#endif // _SPI_PORT_H
|