diff options
| author | Guo Mang <mang.guo@intel.com> | 2016-06-02 11:33:49 +0800 |
|---|---|---|
| committer | Hao Wu <hao.a.wu@intel.com> | 2016-06-07 09:55:16 +0800 |
| commit | 5526fca2fe67d46a8593580292ee6d533c12488a (patch) | |
| tree | 671ecd3001e72f7c48dc2f9eba36e4c8420c39ce /ChvRefCodePkg/Include | |
| parent | 846bc02cf31d8754217a180ab7a18e44201fe9fb (diff) | |
| download | edk2-platforms-5526fca2fe67d46a8593580292ee6d533c12488a.tar.xz | |
ChvRefCodePkg: Add Include files.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Diffstat (limited to 'ChvRefCodePkg/Include')
78 files changed, 5344 insertions, 0 deletions
diff --git a/ChvRefCodePkg/Include/Bemt.h b/ChvRefCodePkg/Include/Bemt.h new file mode 100644 index 0000000000..d8812507ee --- /dev/null +++ b/ChvRefCodePkg/Include/Bemt.h @@ -0,0 +1,179 @@ +/** @file
+ Battery and Energe Management Table.
+
+ Copyright (c) 1996 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _BEMT_H
+#define _BEMT_H
+
+//
+// Statements that include other files
+//
+#include <IndustryStandard/Acpi10.h>
+#include <IndustryStandard/Acpi20.h>
+#include <IndustryStandard/Acpi30.h>
+
+#define EFI_ACPI_OEM0_REVISION 0x05
+#define EFI_ACPI_OEM0_SIGNATURE SIGNATURE_32 ('O', 'E', 'M', '0')
+
+#define EFI_ACPI_OEM_ID 'I','N','T','E','L',' ' // OEMID 6 bytes long
+#define EFI_ACPI_OEM0_TABLE_ID SIGNATURE_64 ('B','A','T','T','E','R','Y',' ') // OEM table id 8 bytes long
+#define CREATOR_ID SIGNATURE_32 ('I','N','T','L')
+#define EFI_FIX_BATTARY_ID SIGNATURE_64 ('I','N','T','N','0','0','0','1')
+#define ACPI_TEMP_RANGES_NUMBER 6
+
+#define EFI_ACPI_BAT_CONF_SIGNATURE SIGNATURE_32 ('B', 'C', 'F', 'G')
+#define EFI_ACPI_BAT_CONF_REVISION 0x01
+#define EFI_ACPI_BAT_CONF_TABLE_ID SIGNATURE_64 ('B', 'A', 'T', 'T', 'C', 'O', 'N', 'F') // OEM table id 8 bytes long
+
+#pragma pack(1)
+
+//
+// Oem0 ACPI table structure
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 BatteryId;
+ UINT8 TurboChargingSupport;
+ UINT8 BatteryType;
+ UINT16 Capacity;
+ UINT16 MaxVoltage;
+ UINT16 ChargeTermiationCurrent;
+ UINT16 LowBatteryThreshold;
+ INT8 SafeDischargeTemperatureUL;
+ INT8 SafeDischargeTemperatureLL;
+ UINT16 TempMonitoringRanges;
+ struct {
+ INT16 TempUL;
+ UINT16 FullChargeVolt;
+ UINT16 FullChargeCurr;
+ UINT16 MaintChargeStartThreshVolt;
+ UINT16 MaintChargeStopThreshVolt;
+ UINT16 MaintChargeCurr;
+ } TempMonitorRanges [ACPI_TEMP_RANGES_NUMBER];
+ INT16 TempLL;
+} EFI_ACPI_OEM0_TABLE;
+
+//
+// Battery Config ACPI table structure
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 FG_Name;
+ UINT64 BatteryId;
+ UINT16 Size;
+ UINT8 FG_ConfigOption;
+ UINT16 PrimaryChecksum;
+ //
+ // Use the maximum fuel gauge config data size.
+ // MAXIM - 200 Bytes
+ // XPOWER - 36 Bytes
+ // $Cove SW FG - 256 Bytes
+ // TI BQ - Factory Programmed into the chip
+ //
+ UINT8 ConfigData[256];
+} EFI_ACPI_BAT_CONF_TABLE;
+
+//
+// Battery Config Variable structure
+//
+typedef struct {
+ UINT64 FG_Name;
+ UINT16 Size;
+ UINT16 Checksum; // Checksum for variable config data
+ UINT16 PrimaryChecksum; // Primary config data checksum
+ //
+ // Use the maximum fuel gauge config data size.
+ // MAXIM - 200 Bytes
+ // XPOWER - 36 Bytes
+ // $Cove SW FG - 256 Bytes
+ // TI BQ - Factory Programmed into the chip
+ //
+ UINT8 ConfigData[256];
+} FUEL_GAUGE_VARIABLE;
+
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ struct{
+ UINT8 Averaging;
+ UINT8 Seq_edv;
+ UINT8 Overload_current[2];
+ UINT8 Term_voltage[2];
+ UINT8 Z_factor[2];
+ UINT8 Edv[9];
+ }EDV_configuration;
+ struct{
+ UINT8 Voltage_diff;
+ UINT8 Current_diff;
+ UINT8 Sleep_enter_current[2];
+ UINT8 Sleep_enter_samples;
+ UINT8 Sleep_exit_current[2];
+ UINT8 Sleep_exit_samples;
+ UINT8 Long_sleep_current[2];
+ UINT8 Ocv_period[4];
+ UINT8 Relax_period[4];
+ UINT8 Flat_zone_low[2];
+ UINT8 Flat_zone_high[2];
+ UINT8 C_factor[2];
+ UINT8 Z_factor[2];
+ UINT8 Max_delta;
+ UINT8 Fcc_update_valid_min[2];
+ UINT8 Fcc_update_valid_max[2];
+ UINT8 Ocv_table[42];
+ }OCV_configuration;
+ struct{
+ UINT8 Max_rate[2];
+ UINT8 Min_rate[2];
+ UINT8 Chg_gain[2];
+ UINT8 Dsg_gain[2];
+ }Rate_configuration;
+ struct{
+ UINT8 Cc_voltage[2];
+ UINT8 Cc_current[2];
+ UINT8 Cc_q[4];
+ UINT8 Seq_cc;
+ UINT8 Cc_term_voltage[2];
+ UINT8 Ocv_below_edv1;
+ UINT8 Design_capacity[4];
+ UINT8 R_sense;
+ UINT8 Fcc_adjust[2];
+ UINT8 Max_impedance[2];
+ UINT8 Max_overcharge;
+ UINT8 Max_fcc_delta;
+ UINT8 Low_temp;
+ UINT8 Light_load;
+ UINT8 Near_full;
+ UINT8 Recharge;
+ UINT8 Mode_switch_capacity[4];
+ }Cell_configuration;
+ UINT8 Cal_volt[4];
+ UINT8 Cal_cur[4];
+ UINT8 Cal_temp[4];
+ UINT8 ChgReg00;
+ UINT8 ChgReg01;
+ UINT8 ChgReg02;
+ UINT8 ChgReg03;
+ UINT8 ChgReg04;
+ UINT8 ChgReg05;
+ UINT8 ChgReg06;
+ UINT8 ChgReg07;
+ UINT8 SDP_ilim;
+ UINT8 CDP_ilim;
+ UINT8 DCP_ilim;
+ UINT8 MaintainanceChg;
+
+} EFI_ACPI_WIN_BAT_CONF_TABLE;
+
+#pragma pack()
+
+#endif
diff --git a/ChvRefCodePkg/Include/ChvA0PowerOn.h b/ChvRefCodePkg/Include/ChvA0PowerOn.h new file mode 100644 index 0000000000..7e128d831e --- /dev/null +++ b/ChvRefCodePkg/Include/ChvA0PowerOn.h @@ -0,0 +1,132 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+//Use SPI Register as a scratch pad for A0 PO
+//
+
+#ifndef __CHVA0POWERON_H__
+#define __CHVA0POWERON_H__
+
+/**
+@todo add description
+
+**/
+UINT32 GetSskpdReg( UINT32 PortId, UINT32 Register ) //Use the C-Unit Msg Bus to read from SB
+{
+ UINT32 OpCode = 0x10000000;
+ //
+ // The Msg Bus addresses can be simplifed since the C-Unit B-D-F is 0-0-0.
+ // eg: *(MmPcieAddr32(0, 0, 0, MC_MCRX)) = *(EC_BASE + MC_MCRX) = 0xE00000D8
+ //
+ // MCRX
+ *((UINT32 *)((UINTN) 0xE00000D8)) = (UINT32) (Register & 0xFFFFFF00);
+ // MCR: Opcode[31:24], PortId[23:16], AddrL[15:08], WriteEnBytes[07:04]
+ *((UINT32 *)((UINTN) 0xE00000D0)) = (UINT32) (OpCode | (PortId <<16) | ((Register & 0x000000FF)<<8) | 0xF0);
+ // MDR
+ return *((UINT32 *)((UINTN) 0xE00000D4));
+}
+
+//Bypass is active low, so get the value and invert it.
+#define A0_PO_REG ~(*((volatile UINT16*)(UINTN)0xFED010A2))
+#define A0_PO_REG1 ~GetSskpdReg(0x1, 0x4A)
+
+//Feature Enable Register, not inverted
+#define A0_PO_FEATURE_REG_0 GetSskpdReg(0x1, 0x4B)
+
+//A0_PO_REG // These are the Values of A0_PO_REG, NOT the actual Register.
+#define ENABLE_SWSMI 0x00000001 // BIT0, 1 = Enable SWSMI triggering, 0 = Bypass SWSMI triggering
+#define BYPASS_GEN 0x00000002 // BIT1, 1 = Bypass access to B0:D2:F0, 0 = Allow access to B0:D2:F0
+#define BYPASS_ISH 0x00000004 // BIT2 1 = Bypass ISH Init, 0 = Regular ISH flow
+#define BYPASS_IUNIT 0x00000008 // BIT3, 1 = Bypass access to B0:D3:F0, 0 = Allow access to B0:D3:F0
+#define ENABLE_INT_UART 0x00000010 // BIT4, 1 = Enable Internal-UART, 0 = Bypass Int-UART (use External-UART)
+#define BYPASS_DISPLAY 0x00000020 // BIT5, 1 = Bypass GOP Policy, 0 = Regular GOP flow (default Enabled)
+#define BYPASS_GPIO 0x00000040 // BIT6, 1 = Bypass GPIO, 0 = Regular GPIO flow
+#define BYPASS_AUDIO 0x00000080 // BIT7, 1 = Bypass Audio, 0 = Regular Audio flow
+#define BYPASS_USB2PHY 0x00000100 // BIT8, 1 = Bypass USB2 PHY Workaround, 0 = Perform USB2 PHY Workaround
+#define BYPASS_UNUSED9 0x00000200 // BIT9
+#define BYPASS_UNUSED10 0x00000400 // BIT10
+#define NO_LPC_REWORK 0x00000800 // BIT11, 1 = Board w/3V LPC, 0 = Board has 1.8V LPC Rework
+#define GOP_RSVD 0x00001000 // BIT12, Reserved for GOP driver - not currently used
+#define BYPASS_MMC_HS 0x00002000 // BIT13, 1 = ByPass MMC HighSpeed, 0 = Enable MMC HighSpeed
+#define BYPASS_USB 0x00004000 // BIT14, 1 = Bypass EFI USB driver, 0 = Load EFI USB driver
+#define BYPASS_UCODE 0x00008000 // BIT15, 1 = Bypass Microcode loading, 0 = Allow Microcode loading
+
+//A0_PO_REG1 // These are the Values of A0_PO_REG1, NOT the actual Register.
+#define BYPASS1_UNUSED0 0x00000001 //bit0
+#define BYPASS1_UNUSED1 0x00000002 //bit1
+#define BYPASS1_UNUSED2 0x00000004 //bit2
+#define BYPASS1_UNUSED3 0x00000008 //bit3
+#define BYPASS1_UNUSED4 0x00000010 //bit4
+#define BYPASS1_UNUSED5 0x00000020 //bit5
+#define BYPASS1_UNUSED6 0x00000040 //bit6
+#define BYPASS1_UNUSED7 0x00000080 //bit7
+#define BYPASS1_UNUSED8 0x00000100 //bit8
+#define BYPASS1_UNUSED9 0x00000200 //bit9
+#define BYPASS1_UNUSED10 0x00000400 //bit10
+#define BYPASS1_UNUSED11 0x00000800 //bit11
+#define BYPASS1_UNUSED12 0x00001000 //bit12
+#define BYPASS1_UNUSED13 0x00002000 //bit13
+#define BYPASS1_UNUSED14 0x00004000 //bit14
+#define BYPASS1_UNUSED15 0x00008000 //bit15
+#define BYPASS1_UNUSED16 0x00010000 //bit16
+#define BYPASS1_UNUSED17 0x00020000 //bit17
+#define BYPASS1_UNUSED18 0x00040000 //bit18
+#define BYPASS1_UNUSED19 0x00080000 //bit19
+#define BYPASS1_UNUSED20 0x00100000 //bit20
+#define BYPASS1_UNUSED21 0x00200000 //bit21
+#define BYPASS1_UNUSED22 0x00400000 //bit22
+#define BYPASS1_UNUSED23 0x00800000 //bit23
+#define BYPASS1_UNUSED24 0x01000000 //bit24
+#define BYPASS1_UNUSED25 0x02000000 //bit25
+#define BYPASS1_UNUSED26 0x04000000 //bit26
+#define BYPASS1_UNUSED27 0x08000000 //bit27
+#define BYPASS1_UNUSED28 0x10000000 //bit28
+#define BYPASS1_UNUSED29 0x20000000 //bit29
+#define BYPASS1_UNUSED30 0x40000000 //bit30
+#define BYPASS1_UNUSED31 0x80000000 //bit31
+
+//A0_PO_FEATURE_REG_0 // These are the Values of A0_PO_REG1, NOT the actual Register.
+#define FEATURE_0_MRC_VERBOSE 0x00000001 //bit0, 0 = Silent; 1 = Verbose
+#define FEATURE_0_SELECT_MRC_CH 0x00000002 //bit1 0 = Single Channel, 1 = Dual Channel
+#define FEATURE_0_SELECT_DVFS_EN 0x00000004 //bit2 0 = DVFS Disabled, 1 = DVFS Enabled
+#define FEATURE_0_DUAL_RANK_EN 0x00000008 //bit3 0 = Single Rank, 1 = Dual Rank
+#define FEATURE_0_SELECT_MRC_FA 0x00000030 //bit[5:4] 00 = 800MHz, 01 = 1066MHz, 10 = 1333MHz, 11 = 1600MHz //DVFS Frequency A
+#define FEATURE_0_UNUSED6 0x00000040 //bit6
+#define FEATURE_0_UNUSED7 0x00000080 //bit7
+#define FEATURE_0_SELECT_MRC_FB 0x00000300 //bit[9:8] 00 = 800MHz, 01 = 1066MHz, 10 = 1333MHz, 11 = 1600MHz //DVFS Frequency B
+#define FEATURE_0_UNUSED10 0x00000400 //bit10
+#define FEATURE_0_UNUSED11 0x00000800 //bit11
+#define FEATURE_0_TX_PWR_T_DIS 0x00001000 //bit12
+#define FEATURE_0_RX_PWR_T_DIS 0x00002000 //bit13
+#define FEATURE_0_AUTODETECT_DIS 0x00004000 //bit14 - 0 = AutoDetectEnabled; 1 = AutoDetectDisabled
+#define FEATURE_0_UNUSED15 0x00008000 //bit15
+#define FEATURE_0_UNUSED16 0x00010000 //bit16
+#define FEATURE_0_UNUSED17 0x00020000 //bit17
+#define FEATURE_0_UNUSED18 0x00040000 //bit18
+#define FEATURE_0_UNUSED19 0x00080000 //bit19
+#define FEATURE_0_UNUSED20 0x00100000 //bit20
+#define FEATURE_0_UNUSED21 0x00200000 //bit21
+#define FEATURE_0_UNUSED22 0x00400000 //bit22
+#define FEATURE_0_UNUSED23 0x00800000 //bit23
+#define FEATURE_0_UNUSED24 0x01000000 //bit24
+#define FEATURE_0_UNUSED25 0x02000000 //bit25
+#define FEATURE_0_UNUSED26 0x04000000 //bit26
+#define FEATURE_0_UNUSED27 0x08000000 //bit27
+#define FEATURE_0_UNUSED28 0x10000000 //bit28
+#define FEATURE_0_MRC_EV_RMT 0x20000000 //bit29 0 = Disabled, 1 = Enabled
+#define FEATURE_0_MRC_EV_RMT_COMMAND_MODE 0x40000000 //bit30 0 = Disabled, 1 = Enabled
+#define FEATURE_0_MRC_OVRRIDE_EN 0x80000000 //bit31 0 = Disable memory configuration override, 1 = Enable memory configuration override
+
+#endif
diff --git a/ChvRefCodePkg/Include/Emt1.h b/ChvRefCodePkg/Include/Emt1.h new file mode 100644 index 0000000000..3637da2f47 --- /dev/null +++ b/ChvRefCodePkg/Include/Emt1.h @@ -0,0 +1,66 @@ +/** @file
+ Energe Management Table extra.
+
+ Copyright (c) 1996 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _EMT1_H
+#define _EMT1_H
+
+//
+// Statements that include other files
+//
+#include <IndustryStandard/Acpi10.h>
+#include <IndustryStandard/Acpi20.h>
+#include <IndustryStandard/Acpi30.h>
+
+#define EFI_ACPI_EMT1_REVISION 0x00000000
+#define EFI_ACPI_OEM1_REVISION 0x00000001
+#define EFI_ACPI_EMT1_SIGNATURE SIGNATURE_32('E', 'M', '_', '1')
+#define EFI_ACPI_OEM1_SIGNATURE SIGNATURE_32('O', 'E', 'M', '1')
+
+#define EFI_ACPI_EMT1_TABLE_ID SIGNATURE_64('O','E','M','1',' ',' ',' ',' ') // OEM table id 8 bytes long
+#define EFI_ACPI_OEM1_TABLE_ID SIGNATURE_64('E','N','R','G','Y','M','G','T') // OEM table id 8 bytes long
+
+#pragma pack(1)
+
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT16 IaAppsRun;
+ UINT8 IaAppsCap;
+ UINT8 CapOrVoltFlag;
+ UINT8 BootOnInvalidBatt;
+} EFI_ACPI_ENERGY_MANAGEMENT_1_TABLE;
+
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 FixedOption0;
+ UINT8 FixedOption1;
+ UINT8 DBIInGpioNumber;
+ UINT8 DBIOutGpioNumber;
+ UINT8 BatChpType;
+ UINT16 IaAppsRun;
+ UINT8 BatIdDBIBase;
+ UINT8 BatIdAnlgBase;
+ UINT8 IaAppsCap;
+ UINT16 VBattFreqLmt;
+ UINT8 CapFreqIdx;
+ UINT8 Rsvd1;
+ UINT8 BatIdx;
+ UINT8 IaAppsToUse;
+ UINT8 TurboChrg;
+ UINT8 Rsvd2[11];
+}EFI_ACPI_EM_OEM_1_TABLE;
+
+#pragma pack()
+
+#endif
diff --git a/ChvRefCodePkg/Include/Guid/AcpiTableStorage.h b/ChvRefCodePkg/Include/Guid/AcpiTableStorage.h new file mode 100644 index 0000000000..e7a3278a7e --- /dev/null +++ b/ChvRefCodePkg/Include/Guid/AcpiTableStorage.h @@ -0,0 +1,25 @@ +/** @file
+ GUID for the ACPI Table Storage filename.
+ This GUID is defined in the Tiano ACPI Table Storage EPS.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _ACPI_TABLE_STORAGE_H_
+#define _ACPI_TABLE_STORAGE_H_
+
+#define EFI_ACPI_TABLE_STORAGE_GUID \
+ { 0x594C5339, 0x3DE5, 0x4ccc, {0x88, 0x86, 0x9C, 0x62, 0x7D, 0xD9, 0xF6, 0x2B}}
+
+extern EFI_GUID gEfiAcpiTableStorageGuid;
+
+#endif
diff --git a/ChvRefCodePkg/Include/Library/AslUpdateLib.h b/ChvRefCodePkg/Include/Library/AslUpdateLib.h new file mode 100644 index 0000000000..4e26bc4e38 --- /dev/null +++ b/ChvRefCodePkg/Include/Library/AslUpdateLib.h @@ -0,0 +1,183 @@ +/** @file
+ ASL dynamic update library definitions.
+ This library provides dymanic update to various ASL structures.
+ There may be different libraries for different environments (PEI, BS, RT, SMM).
+ Make sure you meet the requirements for the library (protocol dependencies, use
+ restrictions, etc).
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _ASL_UPDATE_LIB_H_
+#define _ASL_UPDATE_LIB_H_
+
+//
+// Include files
+//
+#include <IndustryStandard/Acpi.h>
+#include <Protocol/AcpiTable.h>
+#include <Protocol/AcpiSystemDescriptionTable.h>
+
+//
+// AML parsing definitions
+//
+#define AML_NAME_OP 0x08
+#define AML_SCOPE_OP 0x10
+#define AML_PACKAGE_OP 0x12
+#define AML_METHOD_OP 0x14
+#define AML_OPREGION_OP 0x80
+#define AML_DEVICE_OP 0x82
+#define AML_PROCESSOR_OP 0x83
+#define AML_RESRC_TEMP_END_TAG 0x0079
+
+//
+// ASL PSS package structure layout
+//
+#pragma pack (1)
+typedef struct {
+ UINT8 NameOp; // 12h ;First opcode is a NameOp.
+ UINT8 PackageLead; // 20h ;First opcode is a NameOp.
+ UINT8 NumEntries; // 06h ;First opcode is a NameOp.
+ UINT8 DwordPrefix1; // 0Ch
+ UINT32 CoreFrequency; // 00h
+ UINT8 DwordPrefix2; // 0Ch
+ UINT32 Power; // 00h
+ UINT8 DwordPrefix3; // 0Ch
+ UINT32 TransLatency; // 00h
+ UINT8 DwordPrefix4; // 0Ch
+ UINT32 BMLatency; // 00h
+ UINT8 DwordPrefix5; // 0Ch
+ UINT32 Control; // 00h
+ UINT8 DwordPrefix6; // 0Ch
+ UINT32 Status; // 00h
+} PSS_PACKAGE_LAYOUT;
+#pragma pack()
+
+/**
+ Initialize the ASL update library state.
+ This must be called prior to invoking other library functions.
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+**/
+EFI_STATUS
+InitializeAslUpdateLib (
+ VOID
+ );
+
+/**
+ This procedure will update immediate value assigned to a Name
+
+ @param[in] AslSignature The signature of Operation Region that we want to update.
+ @param[in] Buffer source of data to be written over original aml
+ @param[in] Length length of data to be overwritten
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+**/
+EFI_STATUS
+UpdateNameAslCode (
+ IN UINT32 AslSignature,
+ IN VOID *Buffer,
+ IN UINTN Length
+ );
+
+/**
+ This function locates an ACPI structure and updates it.
+ This function knows how to update operation regions and BUFA/BUFB resource structures.
+
+ This function may not be implemented in all instantiations of this library.
+
+ @param[in] AslSignature The signature of Operation Region that we want to update.
+ @param[in] BufferName signature of the Buffer inside OpRegion that we want to update
+ @param[in] MacroAmlEncoding type of entry inside Buffer.
+ @param[in] MacroEntryNumber number of entry of the above type
+ @param[in] Offset offset (in bytes) inside entry where update will be performed
+ @param[in] Buffer source of data to be written over original aml
+ @param[in] Length length of data to be overwritten
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+**/
+EFI_STATUS
+UpdateResourceTemplateAslCode (
+ IN UINT32 AslSignature,
+ IN UINT32 BufferName,
+ IN UINT8 MacroAmlEncoding,
+ IN UINT8 MacroEntryNumber,
+ IN UINT8 Offset,
+ IN VOID *Buffer,
+ IN UINTN Length
+ );
+
+/**
+ This function uses the ACPI support protocol to locate an ACPI table using the .
+ It is really only useful for finding tables that only have a single instance,
+ e.g. FADT, FACS, MADT, etc. It is not good for locating SSDT, etc.
+ Matches are determined by finding the table with ACPI table that has
+ a matching signature and version.
+
+ @param[in] Signature Pointer to an ASCII string containing the Signature to match
+ @param[in, out] Table Updated with a pointer to the table
+ @param[in, out] Handle AcpiSupport protocol table handle for the table found
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+**/
+EFI_STATUS
+LocateAcpiTableBySignature (
+ IN UINT32 Signature,
+ IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table,
+ IN OUT UINTN *Handle
+ );
+
+/**
+ This function uses the ACPI support protocol to locate an ACPI SSDT table.
+ The table is located by searching for a matching OEM Table ID field.
+ Partial match searches are supported via the TableIdSize parameter.
+
+ @param[in] TableId Pointer to an ASCII string containing the OEM Table ID from the ACPI table header
+ @param[in] TableIdSize Length of the TableId to match. Table ID are 8 bytes long, this function
+ will consider it a match if the first TableIdSize bytes match
+ @param[in, out] Table Updated with a pointer to the table
+ @param[in, out] Handle AcpiSupport protocol table handle for the table found
+ @param[in, out] Version See AcpiSupport protocol, GetAcpiTable function for use
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+**/
+EFI_STATUS
+LocateAcpiTableByOemTableId (
+ IN UINT8 *TableId,
+ IN UINT8 TableIdSize,
+ IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table,
+ IN OUT UINTN *Handle
+ );
+
+/**
+ This function calculates and updates an UINT8 checksum.
+
+ @param[in] Buffer Pointer to buffer to checksum
+ @param[in] Size Number of bytes to checksum
+ @param[in] ChecksumOffset Offset to place the checksum result in
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+**/
+EFI_STATUS
+AcpiChecksum (
+ IN VOID *Buffer,
+ IN UINTN Size,
+ IN UINTN ChecksumOffset
+ );
+
+#endif
diff --git a/ChvRefCodePkg/Include/Library/DfuCapsuleLib.h b/ChvRefCodePkg/Include/Library/DfuCapsuleLib.h new file mode 100644 index 0000000000..a5a7b759e6 --- /dev/null +++ b/ChvRefCodePkg/Include/Library/DfuCapsuleLib.h @@ -0,0 +1,66 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _DFU_CAPSULE_LIB_H
+#define _DFU_CAPSULE_LIB_H
+#include <Uefi.h>
+#include <Uefi/UefiSpec.h>
+
+#define UPDATE_SUCCESS 0
+#define UPDATE_FAIL_GENERIC 1
+#define UPDATE_NO_RESOURCE 2
+#define UPDATE_VERSION_INCORRECT 3
+#define UPDATE_INVALID_IMAGE 4
+#define UPDATE_AUTH_ERROR 5
+#define UPDATE_AC_NOT_CONNECTED 6
+#define UPDATE_LOW_BATTERY 7
+
+typedef enum {
+ NO_FAILURE = 0,
+ NOT_UPDATED = 1,
+ PARTIAL_UPDATED = 2
+}DFU_FAILURE_REASON;
+
+extern EFI_GUID gEfiDFUResultGuid;
+extern EFI_GUID gEfiDFUVerGuid;
+
+typedef struct {
+ EFI_GUID DFU_DEVICE_GUID;
+ UINT32 UpdateStatus;
+ DFU_FAILURE_REASON Failure;
+} DFU_UPDATE_STATUS;
+
+/**
+ @todo add description
+
+**/
+extern EFI_STATUS
+EFIAPI
+LoadDFUImage (
+ void **pFileBuffer,
+ UINT64 *pFileSize
+);
+
+/**
+ @todo add description
+
+**/
+extern EFI_STATUS
+EFIAPI
+ReportUpdateStatus(
+ UINT32 UpdateStatus,
+ DFU_FAILURE_REASON failure
+);
+
+#endif
diff --git a/ChvRefCodePkg/Include/Library/I2CLib.h b/ChvRefCodePkg/Include/Library/I2CLib.h new file mode 100644 index 0000000000..7b498a94e4 --- /dev/null +++ b/ChvRefCodePkg/Include/Library/I2CLib.h @@ -0,0 +1,221 @@ +/** @file
+ Register Definitions for I2C Driver/PEIM.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+
+#ifndef I2C_REGS_A0_H
+#define I2C_REGS_A0_H
+
+//
+// FIFO write workaround value.
+//
+#define FIFO_WRITE_DELAY 2
+
+//
+// MMIO Register Definitions
+//
+#define R_IC_CON ( 0x00) // I2C Control
+#define B_IC_RESTART_EN BIT5
+#define B_IC_SLAVE_DISABLE BIT6
+#define V_SPEED_STANDARD 0x02
+#define V_SPEED_FAST 0x04
+#define V_SPEED_HIGH 0x06
+#define B_MASTER_MODE BIT0
+
+#define R_IC_TAR ( 0x04) // I2C Target Address
+#define IC_TAR_10BITADDR_MASTER BIT12
+
+#define R_IC_SAR ( 0x08) // I2C Slave Address
+#define R_IC_HS_MADDR ( 0x0C) // I2C HS MasterMode Code Address
+#define R_IC_DATA_CMD ( 0x10) // I2C Rx/Tx Data Buffer and Command
+
+#define B_READ_CMD BIT8 // 1 = read, 0 = write
+#define B_CMD_STOP BIT9 // 1 = STOP
+#define B_CMD_RESTART BIT10 // 1 = IC_RESTART_EN
+
+#define V_WRITE_CMD_MASK ( 0xFF)
+
+#define R_IC_SS_SCL_HCNT ( 0x14) // Standard Speed I2C Clock SCL High Count
+#define R_IC_SS_SCL_LCNT ( 0x18) // Standard Speed I2C Clock SCL Low Count
+#define R_IC_FS_SCL_HCNT ( 0x1C) // Full Speed I2C Clock SCL High Count
+#define R_IC_FS_SCL_LCNT ( 0x20) // Full Speed I2C Clock SCL Low Count
+#define R_IC_HS_SCL_HCNT ( 0x24) // High Speed I2C Clock SCL High Count
+#define R_IC_HS_SCL_LCNT ( 0x28) // High Speed I2C Clock SCL Low Count
+#define R_IC_INTR_STAT ( 0x2C) // I2C Inetrrupt Status
+#define R_IC_INTR_MASK ( 0x30) // I2C Interrupt Mask
+#define I2C_INTR_GEN_CALL BIT11 // General call received
+#define I2C_INTR_START_DET BIT10
+#define I2C_INTR_STOP_DET BIT9
+#define I2C_INTR_ACTIVITY BIT8
+#define I2C_INTR_TX_ABRT BIT6 // Set on NACK
+#define I2C_INTR_TX_EMPTY BIT4
+#define I2C_INTR_TX_OVER BIT3
+#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
+#define I2C_INTR_RX_OVER BIT1
+#define I2C_INTR_RX_UNDER BIT0
+#define R_IC_RAW_INTR_STAT ( 0x34) // I2C Raw Interrupt Status
+#define R_IC_RX_TL ( 0x38) // I2C Receive FIFO Threshold
+#define R_IC_TX_TL ( 0x3C) // I2C Transmit FIFO Threshold
+#define R_IC_CLR_INTR ( 0x40) // Clear Combined and Individual Interrupts
+#define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER Interrupt
+#define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinterrupt
+#define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER interrupt
+#define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt
+#define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt
+#define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE interrupt
+#define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt
+#define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET interrupt
+#define R_IC_CLR_START_DET ( 0x64) // Clear START_DET interrupt
+#define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL interrupt
+#define R_IC_ENABLE ( 0x6C) // I2C Enable
+#define R_IC_STATUS ( 0x70) // I2C Status
+
+#define R_IC_SDA_HOLD ( 0x7C) // I2C IC_DEFAULT_SDA_HOLD//16bits
+
+#define STAT_MST_ACTIVITY BIT5 // Master FSM Activity Status.
+#define STAT_RFF BIT4 // RX FIFO is completely full
+#define STAT_RFNE BIT3 // RX FIFO is not empty
+#define STAT_TFE BIT2 // TX FIFO is completely empty
+#define STAT_TFNF BIT1 // TX FIFO is not full
+
+#define R_IC_TXFLR ( 0x74) // Transmit FIFO Level Register
+#define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register
+#define R_IC_TX_ABRT_SOURCE ( 0x80) // I2C Transmit Abort Status Register
+#define R_IC_SLV_DATA_NACK_ONLY ( 0x84) // Generate SLV_DATA_NACK Register
+#define R_IC_DMA_CR ( 0x88) // DMA Control Register
+#define R_IC_DMA_TDLR ( 0x8C) // DMA Transmit Data Level
+#define R_IC_DMA_RDLR ( 0x90) // DMA Receive Data Level
+#define R_IC_SDA_SETUP ( 0x94) // I2C SDA Setup Register
+#define R_IC_ACK_GENERAL_CALL ( 0x98) // I2C ACK General Call Register
+#define R_IC_ENABLE_STATUS ( 0x9C) // I2C Enable Status Register
+#define R_IC_COMP_PARAM ( 0xF4) // Component Parameter Register
+#define R_IC_COMP_VERSION ( 0xF8) // Component Version ID
+#define R_IC_COMP_TYPE ( 0xFC) // Component Type
+
+#define I2C_FS_SCL_HCNT_VALUE_100M 0x54
+#define I2C_FS_SCL_LCNT_VALUE_100M 0x9a
+#define I2C_HS_SCL_HCNT_VALUE_100M 0x7
+#define I2C_HS_SCL_LCNT_VALUE_100M 0xE
+
+#define IC_TAR_10BITADDR_MASTER BIT12
+#define FIFO_SIZE 32
+#define R_IC_INTR_STAT ( 0x2C) // I2c Inetrrupt Status
+#define R_IC_INTR_MASK ( 0x30) // I2c Interrupt Mask
+#define I2C_INTR_GEN_CALL BIT11 // General call received
+#define I2C_INTR_START_DET BIT10
+#define I2C_INTR_STOP_DET BIT9
+#define I2C_INTR_ACTIVITY BIT8
+#define I2C_INTR_TX_ABRT BIT6 // Set on NACK
+#define I2C_INTR_TX_EMPTY BIT4
+#define I2C_INTR_TX_OVER BIT3
+#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
+#define I2C_INTR_RX_OVER BIT1
+#define I2C_INTR_RX_UNDER BIT0
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS ProgramAllPciLpssI2C (
+ VOID
+);
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS ProgramPciLpssI2C (
+ IN UINT8 BusNo
+);
+EFI_STATUS ByteReadI2C_Basic(
+ IN UINT8 BusNo,
+ IN UINT8 SlaveAddress,
+ IN UINTN ReadBytes,
+ OUT UINT8 *ReadBuffer,
+ IN UINT8 Start,
+ IN UINT8 End
+);
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS ByteWriteI2C_Basic(
+ IN UINT8 BusNo,
+ IN UINT8 SlaveAddress,
+ IN UINTN WriteBytes,
+ IN UINT8 *WriteBuffer,
+ IN UINT8 Start,
+ IN UINT8 End
+);
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS ByteReadI2C(
+ IN UINT8 BusNo,
+ IN UINT8 SlaveAddress,
+ IN UINT8 Offset,
+ IN UINTN ReadBytes,
+ OUT UINT8 *ReadBuffer
+);
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS ByteWriteI2C(
+ IN UINT8 BusNo,
+ IN UINT8 SlaveAddress,
+ IN UINT8 Offset,
+ IN UINTN WriteBytes,
+ IN UINT8 *WriteBuffer
+);
+
+/**
+ This function initiates an I2C operation on the controller.
+
+ The operation is performed by selecting the I2C device with its slave
+ address and then sending all write data to the I2C device. If read data
+ is requested, a restart is sent followed by the slave address and then
+ the read data is clocked into the I2C controller and placed in the read
+ buffer. When the operation completes, the status value is returned and
+ then the event is set.
+
+ @param[in] BusNo I2C Bus no to which the I2C device has been connected
+ @param[in] SlaveAddress Device Address from which the byte value has to be read
+ @param[in] WriteBytes Number of bytes to send
+ @param[in] WriteBuffer Address of buffer containing data to send
+ @param[in] ReadBytes Number of bytes to read
+ @param[out] ReadBuffer Address of buffer to receive data
+
+ @retval RETURN_SUCCESS The operation completed successfully.
+ @retval RETURN_DEVICE_ERROR There was an I2C error (NACK) during the operation.
+ This could indicate the slave device is not present
+
+**/
+EFI_STATUS
+I2cRequest (
+ IN UINT8 BusNo,
+ IN UINT16 SlaveAddress,
+ IN UINTN WriteBytes,
+ IN UINT8 *WriteBuffer,
+ IN UINTN ReadBytes,
+ OUT UINT8 *ReadBuffer
+ );
+
+#endif // I2C_REGS_A0_H
diff --git a/ChvRefCodePkg/Include/Library/PmicLib.h b/ChvRefCodePkg/Include/Library/PmicLib.h new file mode 100644 index 0000000000..501abd608c --- /dev/null +++ b/ChvRefCodePkg/Include/Library/PmicLib.h @@ -0,0 +1,532 @@ +/** @file
+ Header file of PMIC hardware definition.
+
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PMIC_LIB_H_
+#define _PMIC_LIB_H_
+
+#define CRC_PLUS_SVID_CONFIGURATION 1
+#define WHISKEYCOVE_SVID_CONFIGURATION 2
+#define DC_XPOWER_SVID_CONFIGURATION 3
+#define DC_TI_SVID_CONFIGURATION 4
+#define MTV_PLUS_SVID_CONFIGURATION 5
+
+typedef enum {
+ REG_OVERRIDE = 0,
+ REG_AND = 1,
+ REG_OR = 2,
+ REG_CLEAR = 3
+} RegAction;
+
+typedef struct RegInit{
+ UINT8 regoffset;
+ RegAction action;
+ UINT8 mask;
+ UINT8 value;
+}RegInit_st;
+
+typedef enum {
+ DIR_INPUT = 0,
+ DIR_OUTPUT = 1,
+}GpioAttrib;
+
+typedef struct Gpio{
+ UINT8 *PinName;
+ UINT8 OutputReg;
+ UINT8 InputReg;
+ GpioAttrib Direction;
+ UINT8 IsIntr; //is it an interrupt
+ UINT8 GPOCtrlVal;
+ UINT8 GPICtrlVal;
+}GpioCfg_st;
+
+#define PMIC_I2C_BUSNO 6 //I2C6 is used. index from 0
+
+//Separated registers into two pages: page 0 (accessible through I2C bus address 0x5E) and page 1 (accessible through I2C bus address 0x6E).
+//Page 0 is for OTP. Assigned addresses to registers on page 1.
+#define PMIC_PAGE_0_I2C_ADDR 0x5E
+#define PMIC_PAGE_1_I2C_ADDR 0x6E
+
+#define INTERRUPT_EN 1
+#define INTERRUPT_DIS 0
+
+#define PMIC_DEV_ROHM 0x1F
+#define PMIC_DEV_DIALOG 0x00
+#define PMIC_DEV_DIALOG_1 0x2B
+#define PMIC_DEV_MOUNTVILLE 0x01
+
+#define PMIC_REVID_B0 0xB0
+
+#define PMIC_ROHM_REVID_A1 0xA1
+#define PMIC_ROHM_REVID_A2 0xA2
+#define PMIC_ROHM_REVID_B0 0xB0
+#define PMIC_ROHM_REVID_B1 0xB1
+#define PMIC_ROHM_REVID_B2 0xB2
+#define PMIC_ROHM_REVID_B3 0xB3
+#define PMIC_MOUNTVILLE_REVID_1 0x15
+
+#define PMIC_DIALOG_REVID_A0 0x0A
+#define PMIC_DIALOG_REVID_B0 0xB0
+#define PMIC_DIALOG_REVID_C0 0xC0
+
+#define PMIC_REG_MODEMCTRL_CRCP 0x29
+
+// USB charger type definition for SMSC3750
+#define CHARGER_TYPE_DCP BIT5
+#define CHARGER_TYPE_CDP BIT6
+#define CHARGER_TYPE_SDP (BIT5 | BIT6)
+#define CHARGER_TYPE_SEL1_LOW BIT7
+#define CHARGER_TYPE_SEL1_HIGH (BIT5 | BIT7)
+#define CHARGER_TYPE_INVALID 0x00
+
+/**
+ @todo add description
+
+**/
+UINT8
+EFIAPI
+PmicRead8 (
+ IN UINT8 Register
+ );
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS
+EFIAPI
+PmicWrite8 (
+ IN UINT8 Register,
+ IN UINT8 Value
+ );
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS
+EFIAPI
+PmicThermInit (void);
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS
+EFIAPI
+PmicGpioInit (void);
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS
+EFIAPI
+PmicIntrInit (void);
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS
+EFIAPI
+PmicBcuInit (void);
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS
+EFIAPI
+PmicMiscInit (void);
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS
+EFIAPI
+PmicPage0Init (void *Profile);
+
+/**
+ @todo add description
+
+**/
+UINT8
+EFIAPI
+PmicRead8_page0 (
+ IN UINT8 Register
+ );
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS
+EFIAPI
+PmicWrite8_page0 (
+ IN UINT8 Register,
+ IN UINT8 Value
+ );
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS
+EFIAPI
+PmicVbusControl (BOOLEAN bTurnOn);
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS
+EFIAPI
+PmicClearGPIOIRQ (void);
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS
+EFIAPI
+PmicVhostControl (BOOLEAN bTurnOn);
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS
+EFIAPI
+PmicGetDevID (UINT8 *DevId, UINT8 *RevId);
+
+/**
+ @todo add description
+
+**/
+UINT16
+EFIAPI
+PmicGetBATID (void);
+
+EFI_STATUS
+EFIAPI
+PmicEnableDCPWakeSource(BOOLEAN IsEnabled);
+
+BOOLEAN
+EFIAPI
+PmicGetBPTherm (UINT16 *PmicBattId);
+
+EFI_STATUS
+EFIAPI
+PmicGetBatTSAdc (
+ IN OUT UINT16 *TSAdc
+ );
+/**
+ @todo add description
+
+**/
+BOOLEAN
+EFIAPI
+PmicGetBatteryPresence (VOID);
+
+/**
+ @todo add description
+
+**/
+UINT8
+EFIAPI
+PmicGetBoardID(void);
+
+/**
+ @todo add description
+
+**/
+UINT8
+EFIAPI
+PmicGetMemCfgID(void);
+
+/**
+ @todo add description
+
+**/
+UINT8
+EFIAPI
+PmicGetFABID(void);
+
+/**
+ @todo add description
+
+**/
+UINT16
+EFIAPI
+PmicGetVBAT (void);
+
+/**
+ @todo add description
+
+**/
+BOOLEAN
+EFIAPI
+PmicIsACOn (void);
+
+/**
+ @todo add description
+
+**/
+BOOLEAN
+EFIAPI
+PmicIsPwrBtnPressed(void);
+
+/**
+ @todo add description
+
+**/
+BOOLEAN
+EFIAPI
+PmicIsUIBtnPressed(void);
+
+/**
+ @todo add description
+
+**/
+UINT16
+EFIAPI
+PmicGetResetCause (void);
+
+EFI_STATUS
+EFIAPI
+PmicSetVDDQ (void);
+
+UINT32
+EFIAPI
+PmicStateOfCharge(void);
+
+EFI_STATUS
+EFIAPI
+PmicConfigureCharger(void);
+
+BOOLEAN
+EFIAPI
+PmicCheckForChargerPresent(UINT8* Type);
+
+EFI_STATUS
+EFIAPI
+PmicCheckWakeSrc(UINTN *Source);
+
+EFI_STATUS
+EFIAPI
+PmicSetChargeCurrent(UINT32 ChargeRate);
+
+UINT16
+EFIAPI
+PmicGetVoltage (void);
+
+UINT32
+EFIAPI
+PmicGetACCUMCURR (void);
+
+UINT32
+EFIAPI
+PmicGetSAMPLCURR (void);
+
+UINT8
+EFIAPI
+PmicClearPowerButtonStatus(void);
+
+EFI_STATUS
+EFIAPI
+TiReadEeprom(void);
+
+EFI_STATUS
+EFIAPI
+TiReadOffsetGainCompensation(void);
+
+UINT16
+EFIAPI
+TiPmicGetCorrectedVoltage(void);
+
+UINT32
+EFIAPI
+TiCCCompensation(INT32 DeltaQ, INT32 DeltaSample);
+
+/**
+ @todo add description
+
+**/
+VOID
+EFIAPI
+PmicClearResetCause (void);
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS
+EFIAPI
+PmicGetWakeCause (UINT8 *WakeCause);
+
+/**
+ @todo add description
+
+**/
+VOID
+EFIAPI
+PmicClearWakeCause (void);
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS
+EFIAPI
+PmicDebugRegDump (void);
+
+/**
+ @todo add description
+
+**/
+BOOLEAN
+EFIAPI
+PmicIsUsbConnected (void);
+
+/**
+ @todo add description
+
+**/
+BOOLEAN
+EFIAPI
+PmicIsBatOn (void);
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS
+EFIAPI
+PmicSetVDDQ (void);
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS
+EFIAPI
+PmicGpioToggleForLpcConfig(void);
+
+/**
+ @todo add description
+
+**/
+VOID
+PmicForceVggPwmModeWA(void);
+
+VOID
+PmicModemWa (
+ VOID
+ );
+
+/**
+ @todo add description
+
+**/
+UINT16
+EFIAPI
+PmicGetBatteryCap (VOID);
+
+/**
+ @todo add description
+
+**/
+VOID
+PmicForceOffModem (
+ VOID
+ );
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS
+EFIAPI
+PmicBatchRegisterInit (
+ IN RegInit_st *RegInit,
+ IN UINT32 length
+ );
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS
+EFIAPI
+PmicSetVIDDecayWA (void);
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS
+PmicGetShutdownCause (
+ IN OUT UINT32 *ShutdownCause
+ );
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS
+PmicGetPwrSrcIrq (
+ IN OUT UINT32 *PowerSrcIrq
+ );
+
+/**
+ @todo add description
+
+**/
+EFI_STATUS
+PmicClearShutdownCause (VOID);
+
+/**
+ @todo add description
+
+**/
+VOID
+PmicForceOffModem (
+ VOID
+ );
+
+EFI_STATUS
+PmicDisablePowerButton(
+ OUT UINT8 *
+);
+
+EFI_STATUS
+PmicEnablePowerButton (
+ IN UINT8
+);
+
+EFI_STATUS
+EFIAPI
+PmicGetBatTSAdc (
+ IN OUT UINT16 *TSAdc
+ );
+
+BOOLEAN
+EFIAPI
+PmicIsPowerOnReset (
+ VOID
+ );
+
+#endif
diff --git a/ChvRefCodePkg/Include/Library/SocSkuLib.h b/ChvRefCodePkg/Include/Library/SocSkuLib.h new file mode 100644 index 0000000000..274d89a39b --- /dev/null +++ b/ChvRefCodePkg/Include/Library/SocSkuLib.h @@ -0,0 +1,55 @@ +/** @file
+ Defines SocSkuLib.
+
+ Copyright (c) 2005 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef SOCSKULIB_H_
+#define SOCSKULIB_H_
+
+typedef enum {
+ SOC_SKU_200 = 0,
+ SOC_SKU_320 = 1,
+ SOC_SKU_333 = 3,
+ SOC_SKU_400 = 4,
+ SOC_SKU_360 = 5,
+ SOC_SKU_373 = 6,
+ SOC_SKU_MAX = 7
+} SOC_SKU;
+
+typedef enum {
+ SKU_INDEX_SOC200_SOC320_SOC400 = 0,
+ SKU_INDEX_SOC333 = 1,
+ SKU_INDEX_SOC360 = 2,
+ SKU_INDEX_SOC373 = 3,
+ SKU_INDEX_MAX = 4,
+} SKU_INDEX;
+
+/**
+ @todo add description
+
+**/
+SOC_SKU
+GetSocSku (
+ VOID
+ );
+
+/**
+ @todo add description
+
+**/
+SKU_INDEX
+GetMrcSkuIndex (
+ VOID
+ );
+
+#endif /* SOCSKULIB_H_ */
diff --git a/ChvRefCodePkg/Include/Library/UsbDeviceLib.h b/ChvRefCodePkg/Include/Library/UsbDeviceLib.h new file mode 100644 index 0000000000..2405cdda04 --- /dev/null +++ b/ChvRefCodePkg/Include/Library/UsbDeviceLib.h @@ -0,0 +1,323 @@ +/** @file
+
+ Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _EFI_XDCI_LIB_H_
+#define _EFI_XDCI_LIB_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/UsbIo.h>
+
+#define MAX_DESCRIPTOR_SIZE 64
+#define STRING_ARR_SIZE (MAX_DESCRIPTOR_SIZE - 2)
+#define USB_ADDRESS_TABLE_SIZE 16 //4
+
+//
+// Endpoint Zero
+//
+#define USB_EP0_MAX_PKT_SIZE_HS 0x40 // High Speed mode is explicitly set as 64 bytes
+#define USB_EP0_MAX_PKT_SIZE_SS 0x9 // Must be 0x9 (2^9 = 512 Bytes) in SuperSpeed mode
+#define USB_EPO_MAX_PKT_SIZE_ALL 512 // Overall max bytes for any type
+
+//
+// Bulk Endpoints
+//
+#define USB_BULK_EP_PKT_SIZE_HS 0x200 // Bulk-Endpoint HighSpeed
+#define USB_BULK_EP_PKT_SIZE_SS 0x400 // Bulk-Endpoint SuperSpeed
+#define USB_BULK_EP_PKT_SIZE_MAX USB_BULK_EP_PKT_SIZE_SS
+
+//
+// Transmit Direction Bits
+//
+#define USB_ENDPOINT_DIR_OUT 0x00
+
+//
+// Endpoint Companion Bulk Attributes
+//
+#define USB_EP_BULK_BM_ATTR_MASK 0x1F
+
+//
+// Configuration Modifiers (Attributes)
+//
+#define USB_BM_ATTR_RESERVED 0x80
+#define USB_BM_ATTR_SELF_POWERED 0x40
+#define USB_BM_ATTR_REMOTE_WAKE 0X20
+
+//
+// USB BCD version
+//
+#define USB_BCD_VERSION_LS 0x0110
+#define USB_BCD_VERSION_HS 0x0200
+#define USB_BCD_VERSION_SS 0x0300
+
+//
+// Device RequestType Flags
+//
+#define USB_RT_TX_DIR_H_TO_D (0x0) // Tx direction Host to Device
+#define USB_RT_TX_DIR_D_TO_H (0x1 << 7) // Tx direction Device to Host
+#define USB_RT_TX_DIR_MASK (0x80)
+
+//
+// USB request type
+//
+#define USB_REQ_TYPE_MASK (0x60)
+
+//
+// Usb control transfer target
+//
+#define USB_TARGET_MASK (0x1F)
+
+//
+// Device GetStatus bits
+//
+#define USB_STATUS_SELFPOWERED (0x01)
+#define USB_STATUS_REMOTEWAKEUP (0x02)
+
+//
+// USB Device class identifiers
+//
+#define USB_DEVICE_MS_CLASS (0x08)
+#define USB_DEVICE_VENDOR_CLASS (0xFF)
+
+//
+// USB Descriptor types
+//
+#define USB_DESC_TYPE_BOS 0x0F
+#define USB_DESC_TYPE_DEVICE_CAPABILITY 0x10
+#define USB_DESC_TYPE_SS_ENDPOINT_COMPANION 0x30
+
+#ifdef SUPPORT_SUPER_SPEED
+//
+// USB device capability Type Codes
+// USB3 Table 9-13
+//
+typedef enum {
+ WirelessUSB = 0x01,
+ USB2Extension,
+ SuperSpeedUSB,
+ ContainerID,
+ SuperSpeedPlusUSB = 0x0A
+} USB_DEVICE_CAP_TYPE_CODE;
+#endif
+
+//
+// USB device states from USB spec sec 9.1
+//
+typedef enum {
+ UsbDevStateOff = 0,
+ UsbDevStateInit,
+ UsbDevStateAttached,
+ UsbDevStatePowered,
+ UsbDevStateDefault,
+ UsbDevStateAddress,
+ UsbDevStateConfigured,
+ UsbDevStateSuspended,
+ UsbDevStateError
+} USB_DEVICE_STATE;
+
+//
+// The following set of structs are used during USB data transaction
+// operatitions, including requests and completion events.
+//
+#pragma pack(1)
+
+typedef struct {
+ UINT32 EndpointNum;
+ UINT8 EndpointDir;
+ UINT8 EndpointType;
+ UINT32 Length;
+ VOID *Buffer;
+} EFI_USB_DEVICE_XFER_INFO;
+
+//
+// SuperSpeed Endpoint companion descriptor
+// USB3 table 9-22
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT8 MaxBurst;
+ UINT8 Attributes;
+ UINT16 BytesPerInterval;
+} EFI_USB_ENDPOINT_COMPANION_DESCRIPTOR;
+
+typedef struct {
+ EFI_USB_ENDPOINT_DESCRIPTOR *EndpointDesc;
+ EFI_USB_ENDPOINT_COMPANION_DESCRIPTOR *EndpointCompDesc;
+} USB_DEVICE_ENDPOINT_INFO, USB_DEVICE_ENDPOINT_OBJ;
+
+typedef struct {
+ VOID *Buffer;
+ UINT32 Length;
+} USB_DEVICE_IO_INFO;
+
+typedef struct {
+ USB_DEVICE_IO_INFO IoInfo;
+ USB_DEVICE_ENDPOINT_INFO EndpointInfo;
+} USB_DEVICE_IO_REQ;
+
+//
+// Optional string descriptor
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT16 LangID[STRING_ARR_SIZE];
+} USB_STRING_DESCRIPTOR;
+
+//
+// The following structures abstract the device descriptors a class
+// driver needs to provide to the USBD core.
+// These structures are filled & owned by the class/function layer.
+//
+typedef struct {
+ EFI_USB_INTERFACE_DESCRIPTOR *InterfaceDesc;
+ USB_DEVICE_ENDPOINT_OBJ *EndpointObjs;
+} USB_DEVICE_INTERFACE_OBJ;
+
+typedef struct {
+ EFI_USB_CONFIG_DESCRIPTOR *ConfigDesc;
+ VOID *ConfigAll;
+ USB_DEVICE_INTERFACE_OBJ *InterfaceObjs;
+} USB_DEVICE_CONFIG_OBJ;
+
+#ifdef SUPPORT_SUPER_SPEED
+//
+// SuperSpeed Binary Device Object Store(BOS) descriptor
+// USB3 9.6.2
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT16 TotalLength;
+ UINT8 NumDeviceCaps;
+} EFI_USB_BOS_DESCRIPTOR;
+
+//
+// Generic Header of Device Capability descriptor
+// USB3 9.6.2.2
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT8 DevCapabilityType;
+ UINT8 CapDependent;
+} EFI_USB_SS_DEVICE_CAP_DESCRIPTOR;
+
+//
+// USB2.0 Extension descriptor
+// USB3 Table 9-14
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT8 DeviceCapabilityType;
+ UINT32 Attributes;
+} EFI_USB_USB2_EXT_CAP_DESCRIPTOR;
+
+//
+// SuperSpeed USB Device Capability descriptor
+// USB3 Table 9-15
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT8 DeviceCapabilityType;
+ UINT8 Attributes;
+ UINT16 SpeedSupported;
+ UINT8 FunctionalitySupport;
+ UINT8 U1DevExitLat;
+ UINT16 U2DevExitLat;
+} EFI_USB_SS_USB_DEV_CAP_DESCRIPTOR;
+
+//
+// Container ID descriptor
+// USB3 Table 9-16
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT8 DeviceCapabilityType;
+ UINT8 Reserved;
+ UINT8 UUID[16];
+} EFI_USB_CONTAINER_ID_DESCRIPTOR;
+
+//
+// Container ID descriptor
+// USB3 Table 9-16
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT8 DeviceCapabilityType;
+ UINT8 ReservedByte;
+ UINT32 Attributes;
+ UINT16 FunctionalitySupport;
+ UINT16 ReservedWord;
+ UINT32 SublinkSpeedAttr[2];
+} EFI_USB_SS_PLUS_USB_DEV_CAP_DESCRIPTOR;
+
+#endif
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_USB_CONFIG_CALLBACK) (
+ IN UINT8 CfgVal
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_USB_SETUP_CALLBACK) (
+ IN EFI_USB_DEVICE_REQUEST *CtrlRequest,
+ IN USB_DEVICE_IO_INFO *IoInfo
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_USB_DATA_CALLBACK) (
+ IN EFI_USB_DEVICE_XFER_INFO *XferInfo
+ );
+
+typedef struct {
+ USB_DEVICE_DESCRIPTOR *DeviceDesc;
+ USB_DEVICE_CONFIG_OBJ *ConfigObjs;
+ USB_STRING_DESCRIPTOR *StringTable;
+#ifdef SUPPORT_SUPER_SPEED
+ EFI_USB_BOS_DESCRIPTOR *BosDesc;
+#endif
+ UINT8 StrTblEntries;
+ EFI_USB_CONFIG_CALLBACK ConfigCallback;
+ EFI_USB_SETUP_CALLBACK SetupCallback;
+ EFI_USB_DATA_CALLBACK DataCallback;
+} USB_DEVICE_OBJ;
+
+//
+// Main USBD driver object structure containing all data necessary
+// for USB device mode processing at this layer
+//
+typedef struct {
+ USB_DEVICE_OBJ *UsbdDevObj; /* pointer to a Device Object */
+ VOID *XdciDrvObj; /* Opaque handle to XDCI driver */
+ BOOLEAN XdciInitialized; /* flag to specify if the XDCI driver is initialized */
+ USB_DEVICE_CONFIG_OBJ *ActiveConfigObj; /* pointer to currently active configuraiton */
+ USB_DEVICE_STATE State; /* current state of the USB Device state machine */
+ UINT8 Address; /* configured device address */
+} USB_DEVICE_DRIVER_OBJ;
+
+#pragma pack()
+
+#endif
diff --git a/ChvRefCodePkg/Include/Library/UsbDeviceModeLib.h b/ChvRefCodePkg/Include/Library/UsbDeviceModeLib.h new file mode 100644 index 0000000000..3bb4849ff5 --- /dev/null +++ b/ChvRefCodePkg/Include/Library/UsbDeviceModeLib.h @@ -0,0 +1,247 @@ +/** @file
+
+ Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __BASE_USBDEVICEMODE_LIB_H__
+#define __BASE_USBDEVICEMODE_LIB_H__
+
+#pragma pack(1)
+typedef struct {
+ UINT8 bLength;
+ UINT8 bDescriptorType;
+ UINT8 bMaxBurst;
+ UINT8 bmAttributes;
+ UINT16 wBytesPerInterval;
+} endpointCompanionDescriptor;
+#pragma pack()
+
+#pragma pack(1)
+typedef struct {
+ UINT8 bLength;
+ UINT8 bDescriptorType;
+ UINT8 bEndpointAddress;
+ UINT8 bmAttributes;
+ UINT16 wMaxPacketSize;
+ UINT8 bInterval;
+} endpointDescriptor;
+#pragma pack()
+
+typedef struct {
+ endpointDescriptor *pEpDesc;
+ endpointCompanionDescriptor *pEpCompDesc;
+} USB_DEV_EP_INFO; //usbdEpInfo;
+
+typedef struct {
+ VOID *pBuf;
+ UINT32 dataLen;
+} USBD_IO_INFO;
+
+typedef struct {
+ USBD_IO_INFO ioInfo;
+ USB_DEV_EP_INFO epInfo;
+} USBD_IO_REQ;
+
+/**
+**/
+UINTN
+EFIAPI
+usbdInitDCI (
+ VOID
+ );
+
+/**
+ @todo add description
+
+**/
+BOOLEAN
+EFIAPI
+fbInit (
+ OUT VOID *pParams
+ );
+
+/**
+ @todo add description
+
+**/
+BOOLEAN
+EFIAPI
+fbDeinit (
+ VOID
+ );
+
+/**
+ @todo add description
+**/
+BOOLEAN
+EFIAPI
+fbStart (
+ VOID
+ );
+
+/**
+ @todo add description
+**/
+BOOLEAN
+EFIAPI
+fbStop (
+ VOID
+ );
+
+/**
+ @todo add description
+**/
+BOOLEAN
+EFIAPI
+usbdSetMmioBar (
+ UINT32 mmioBar
+ );
+
+/**
+ @todo add description
+**/
+BOOLEAN
+EFIAPI
+udciDeinit (
+ VOID *pUdciHndl,
+ UINT32 flags
+ );
+
+/**
+ @todo add description
+**/
+BOOLEAN
+EFIAPI
+udciIsr (
+ VOID *pUdciHndl
+ );
+
+/**
+ @todo add description
+**/
+BOOLEAN
+EFIAPI
+udciConnect (
+ VOID *pUdciHndl
+ );
+
+/**
+ @todo add description
+**/
+BOOLEAN
+EFIAPI
+udciDisconnect (
+ VOID *pUdciHndl
+ );
+
+/**
+ @todo add description
+**/
+BOOLEAN
+EFIAPI
+udciSetAddress (
+ VOID *pUdciHndl,
+ UINT8 address
+ );
+
+/**
+ @todo add description
+**/
+BOOLEAN
+EFIAPI
+udciInitEp (
+ VOID *pUdciHndl,
+ USB_DEV_EP_INFO *pEpInfo
+ );
+
+
+/**
+ @todo add description
+**/
+BOOLEAN
+EFIAPI
+udciEnableEp (
+ VOID *pUdciHndl,
+ USB_DEV_EP_INFO *pEpInfo
+ );
+
+/**
+ @todo add description
+**/
+BOOLEAN
+EFIAPI
+udciDisableEp (
+ VOID *pUdciHndl,
+ USB_DEV_EP_INFO *pEpInfo
+ );
+
+/**
+ @todo add description
+**/
+BOOLEAN
+EFIAPI
+udciStallEp (
+ VOID *pUdciHndl,
+ USB_DEV_EP_INFO *pEpInfo
+ );
+
+/**
+ @todo add description
+**/
+BOOLEAN
+EFIAPI
+udciClearStallEp (
+ VOID *pUdciHndl,
+ USB_DEV_EP_INFO *pEpInfo
+ );
+
+
+/**
+ @todo add description
+**/
+BOOLEAN
+EFIAPI
+udciEp0TxStatus (
+ VOID *pUdciHndl
+ );
+
+/**
+ @todo add description
+**/
+BOOLEAN
+EFIAPI
+udciEpTxData (
+ VOID *pUdciHndl,
+ USBD_IO_REQ *pIoReq
+ );
+
+/**
+ @todo add description
+**/
+BOOLEAN
+EFIAPI
+udciEpRxData (
+ VOID *pUdciHndl,
+ USBD_IO_REQ *pIoReq
+ );
+
+/**
+ @todo add description
+**/
+BOOLEAN
+EFIAPI
+udciRegisterCallbacks (
+ VOID *pUdciHndl
+ );
+
+
+#endif //
diff --git a/ChvRefCodePkg/Include/Pidv.h b/ChvRefCodePkg/Include/Pidv.h new file mode 100644 index 0000000000..e1918e6351 --- /dev/null +++ b/ChvRefCodePkg/Include/Pidv.h @@ -0,0 +1,95 @@ +/** @file
+
+ Copyright (c) 1996 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PIDV_H
+#define _PIDV_H
+
+//
+// Statements that include other files
+//
+#include <IndustryStandard/Acpi10.h>
+#include <IndustryStandard/Acpi20.h>
+#include <IndustryStandard/Acpi30.h>
+
+//
+// Definitions
+//
+#define EFI_ACPI_OEM_PIDV_REVISION 0x00000002
+#define EFI_ACPI_PLATFORM_ID_V_SIGNATURE SIGNATURE_32('P', 'I', 'D', 'V')
+#define PIDV_PART_NUMBER_LEN_MAX 32
+#define PIDV_EXT_ID_LEN_MAX 32
+#define PIDV_SYSTEM_UUID_LEN_MAX 16
+
+#pragma pack(1)
+
+typedef struct {
+ UINT8 Fru1:4;
+ UINT8 Fru2:4;
+ UINT8 Fru3:4;
+ UINT8 Fru4:4;
+ UINT8 Fru5:4;
+ UINT8 Fru6:4;
+ UINT8 Fru7:4;
+ UINT8 Fru8:4;
+ UINT8 Fru9:4;
+ UINT8 Fru10:4;
+ UINT8 Fru11:4;
+ UINT8 Fru12:4;
+ UINT8 Fru13:4;
+ UINT8 Fru14:4;
+ UINT8 Fru15:4;
+ UINT8 Fru16:4;
+ UINT8 Fru17:4;
+ UINT8 Fru18:4;
+ UINT8 Fru19:4;
+ UINT8 Fru20:4;
+} FIELD_REPLACEABLE_UNITS;
+
+//
+// SPID - 32 bytes
+//
+typedef struct {
+ UINT16 CustomerID;
+ UINT16 VendorID;
+ UINT16 DeviceManufacturerID;
+ UINT16 PlatformFamilyID;
+ UINT16 ProductLineID;
+ UINT16 HardwareID;
+ FIELD_REPLACEABLE_UNITS Fru;
+ UINT16 Reserved[5];
+} SOFTWARE_PLATFORM_ID;
+//
+// PIDV structure
+//
+//
+// Ensure proper structure formats
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PartNumber[32];
+ SOFTWARE_PLATFORM_ID ExtID1;
+ UINT8 ExtID2[32];
+ UINT8 SystemUuid[16];
+ UINT8 IaFwBuildId[32]; /* unusedon Revision#2 */
+ UINT32 IaSvn; /* unusedon Revision#2 */
+ UINT32 SecSvn; /* unusedon Revision#2 */
+ UINT32 PdrSvn; /* unusedon Revision#2 */
+ UINT16 IaFwRevValues[4]; /* unusedon Revision#2 */
+ UINT16 SecRevValues[4]; /* unusedon Revision#2 */
+ UINT16 PdrRevValues[4]; /* unusedon Revision#2 */
+ UINT32 OEM_TAG; /* unusedon Revision#2 */
+} EFI_ACPI_PLATFORM_ID_V_TABLE;
+#pragma pack()
+
+#endif
diff --git a/ChvRefCodePkg/Include/PmicReg.h b/ChvRefCodePkg/Include/PmicReg.h new file mode 100644 index 0000000000..8ad6e5839f --- /dev/null +++ b/ChvRefCodePkg/Include/PmicReg.h @@ -0,0 +1,398 @@ +/** @file
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PMIC_REG_H_
+#define _PMIC_REG_H_
+
+#define BIT00 0x01
+#define BIT01 0x02
+#define BIT02 0x04
+#define BIT03 0x08
+#define BIT04 0x10
+#define BIT05 0x20
+#define BIT06 0x40
+#define BIT07 0x80
+
+#define PMIC_REG_ID0 0x0
+#define PMIC_REG_REV 0x1
+#define PMIC_REG_IRQLVL1 0x2
+#define PMIC_REG_PWRSRCIRQ 0x3
+#define B_PMIC_PWRSRCIRQ_BATDET BIT02
+#define B_PMIC_PWRSRCIRQ_DCINDET BIT01
+#define B_PMIC_PWRSRCIRQ_VBUSDET BIT00
+#define PMIC_REG_THRMIRQ0 0x4
+#define PMIC_REG_THRMIRQ1 0x5
+#define PMIC_REG_THRMIRQ2 0x6
+#define PMIC_REG_BCUIRQ 0x7
+#define PMIC_REG_ADCIRQ0 0x8
+#define PMIC_REG_ADCIRQ1 0x9
+#define PMIC_REG_CHGRIRQ 0xA
+#define PMIC_REG_GPIO0IRQ 0xB
+#define PMIC_REG_GPIO1IRQ 0xC
+#define PMIC_REG_VHDMIIRQ 0xD
+#define PMIC_REG_MIRQLVL1 0xE
+#define PMIC_MASK_MVHMDI BIT06
+#define PMIC_MASK_MGPIO BIT05
+#define PMIC_MASK_MCHGRINT BIT04
+#define PMIC_MASK_MADC BIT03
+#define PMIC_MASK_MBCU BIT02
+#define PMIC_MASK_MTHRM BIT01
+#define PMIC_MASK_MPWRSRC BIT00
+#define PMIC_MASK_ALL_IRQ 0x7F
+
+#define PMIC_REG_MPWRSRCIRQS0 0xF
+#define PMIC_MASK_BATDET BIT02 //Battery Detection Mask in S0 State
+#define PMIC_MASK_DCINDET BIT01 //AC/DC Adapter Detection Mask in S0 State
+#define PMIC_MASK_VBUSDET BIT00 //VBUS Detection Mask in S0 State
+
+#define PMIC_REG_MPWRSRCIRQSX 0x10
+#define PMIC_REG_MTHRMIRQ0 0x11
+#define PMIC_REG_MTHRMIRQ1 0x12
+#define PMIC_REG_MTHRMIRQ2 0x13
+#define PMIC_REG_MBCUIRQ 0x14
+#define PMIC_MASK_VCRIT BIT02
+#define PMIC_MASK_VWARNA BIT01
+#define PMIC_MASK_VWARNB BIT00
+#define PMIC_MASK_MBCU_ALL (BIT02|BIT01|BIT00)
+
+#define PMIC_REG_MADCIRQ0 0x15
+#define PMIC_REG_MADCIRQ1 0x16
+#define PMIC_REG_MCHGRIRQS0 0x17
+#define PMIC_MASK_MCHGR BIT00
+#define PMIC_REG_MCHGRIRQSX 0x18
+#define PMIC_REG_MGPIO0IRQS0 0x19
+#define PMIC_REG_MGPIO1IRQS0 0x1A
+#define PMIC_REG_MGPIO0IRQSX 0x1B
+#define PMIC_REG_MGPIO1IRQSX 0x1C
+#define PMIC_REG_MVHDMIIRQ 0x1D
+#define PMIC_REG_SPWRSRC 0x1E
+#define PMIC_MASK_BATDET BIT02
+#define PMIC_MASK_DCINDET BIT01
+#define PMIC_MASK_VBUSDET BIT00
+
+#define PMIC_REG_REGLOCK 0x1F
+#define PMIC_REGLOCK_VREG_BIT BIT0
+#define PMIC_REGLOCK_VCRIT_CFG_BIT BIT1
+#define PMIC_REGLOCK_THERMAL_BIT BIT2
+#define PMIC_REGLOCK_LOWBATDET_BIT BIT3
+
+//
+// Mask via Crystal Cove Plus spec 0.7
+// BUGBUG: we added the TBD into PMIC definition, and need update the TBD when PMIC spec is >0.7
+//
+#define PMIC_REG_RESETSRC0 0x20
+#define PMIC_MASK_RBATRM BIT06
+#define PMIC_MASK_RVSYSOVP BIT05
+#define PMIC_MASK_RVSYSUVP BIT04
+#define PMIC_MASK_RBATTEMP BIT03
+#define PMIC_MASK_RSYSTEMP BIT02
+#define PMIC_MASK_RPMICTEMP BIT01
+
+#define PMIC_REG_RESETSRC1 0x21
+#define PMIC_MASK_RFCO BIT02
+#define PMIC_MASK_RIDBATRM BIT01
+#define PMIC_MASK_RVCRIT BIT00
+
+#define PMIC_REG_WAKESRC 0x22
+#define PMIC_MASK_WAKEADPT BIT03
+#define PMIC_MASK_WAKEUSB BIT02
+#define PMIC_MASK_WAKEBAT BIT01
+#define PMIC_MASK_WAKEPBTN BIT00
+
+#define PMIC_REG_LOWBATDET0 0x23
+#define PMIC_MASK_DCBOOT BIT07 //0--BATLOW_B status depending on battery voltage set by LOWBATDC[3:0]
+#define PMIC_MASK_LOWBATDC (BIT06|BIT05|BIT04) // Valid Battery Detection Threshold with AC/DC adapter
+#define PMIC_MASK_LOWBAT (BIT03|BIT02|BIT01|BIT00) //Valid Battery Detection Threshold with No Charge source
+
+#define PMIC_REG_LOWBATDET1 0x24
+#define PMIC_MASK_LOWBATDCP (BIT07|BIT06|BIT05|BIT04) // Valid Battery Detection Threshold with DCP Charge Source
+#define PMIC_MASK_LOWBATSDP (BIT03|BIT02|BIT01|BIT00) //Valid Battery Detection Threshold with SDP Charge
+
+#define PMIC_REG_PSDETCTRL 0x25
+#define PMIC_MASK_DBIEN BIT05 //Digital Battery Communication enable
+#define PMIC_MASK_BATRMSRC BIT04 //Battery removal Dectection Source 0-VBAT Comparator 1-BATID
+#define PMIC_MASK_BATRMPDEN BIT03 //Battery Removal Power Down Enable
+#define PMIC_MASK_BATDBEN BIT02 //Battery Detection Debounce timer
+#define PMIC_MASK_VDCINDBEN BIT01 //Enables or disables VDCIN comparator debounce window.
+#define PMIC_MASK_VBUSDBEN BIT00 //Enables or disables VBUS comparator debounce window.
+
+#define PMIC_REG_PBCONFIG0 0x26
+#define PMIC_MASK_PBDIS (BIT07|BIT06) //disable UI button func
+#define PMIC_MASK_FCOT (BIT03|BIT02|BIT01|BIT0) //Time that the power button has to be held down before a forced system shutdown is triggered.
+
+#define PMIC_REG_PBSTATUS 0x27
+#define PMIC_MASK_PBLVL BIT04 //0 = Power button pressed
+#define PMIC_MASK_PBHT (BIT03|BIT02|BIT01|BIT00) //Time that the power button has been held down
+
+#define PMIC_REG_UIBSTATUS 0x28
+#define PMIC_MASK_UIBLVL BIT04 //0 = UI button pressed
+#define PMIC_MASK_UIBHT (BIT03|BIT02|BIT01|BIT00) //Time that the UI button has been held down
+
+#define PMIC_REG_MODEMCTRL 0x29
+#define PMIC_REG_BBCHGRCFG 0x2A
+#define PMIC_REG_GPIO0P0CTLO 0x2B
+#define PMIC_MASK_ALTFUNCEN BIT06 //alternative function enable bit
+#define PMIC_MASK_DIR BIT05 //GPIO pin direction 0-input 1-output
+#define PMIC_MASK_DRV BIT04 //GPIO output driver type 0-CMOS 1-Open Drain
+#define PMIC_MASK_REN BIT03 //Internal Pullup/pulldown Enable Bit
+#define PMIC_MASK_RVAL (BIT02|BIT01) //Internal pullup resistor value 00-2kohm pulldown 01-2kohm pullup 10-50kohm pulldown 11-50kohm pullup
+#define PMIC_MASK_RVAL_2K_PD 0x0
+#define PMIC_MASK_RVAL_2K_PU (0x1<<1)
+#define PMIC_MASK_RVAL_50K_PD (0x2<<1)
+#define PMIC_MASK_RVAL_50K_PU (0x3<<1)
+#define PMIC_MASK_DOUT BIT00 //GPIO Pin outpin value 0--Electrical Low 1-Electrical High (CMOS) or High-Z (OD)
+#define PMIC_MASK_OUTPUT_ALL 0x7f
+
+#define PMIC_REG_GPIO0P1CTLO 0x2C
+#define PMIC_REG_GPIO0P2CTLO 0x2D
+#define PMIC_REG_GPIO0P3CTLO 0x2E
+#define PMIC_REG_GPIO0P4CTLO 0x2F
+#define PMIC_REG_GPIO0P5CTLO 0x30
+#define PMIC_REG_GPIO0P6CTLO 0x31
+#define PMIC_REG_GPIO0P0CTLI 0x33
+#define PMIC_MASK_POL BIT04 //Input polarity
+#define PMIC_MASK_GPIDBNC BIT03 //GPIO input pin debounce enable
+#define PMIC_MASK_INTCNT (BIT02|BIT01) //GPIO input pin interrupt detected
+#define PMIC_MASK_INTCNT_DISABLE 0x0
+#define PMIC_MASK_INTCNT_NEGA (0x1<<1) //negative edge
+#define PMIC_MASK_INTCNT_POS (0x2<<1) //positive edge
+#define PMIC_MASK_INTCNT_BOTH (0x3<<1) //both edge
+#define PMIC_MASK_DIN BIT00 //GPIO input pin status
+#define PMIC_MASK_INPUT_ALL 0x1f
+
+#define PMIC_REG_GPIO0P1CTLI 0x34
+#define PMIC_REG_GPIO0P2CTLI 0x35
+#define PMIC_REG_GPIO0P3CTLI 0x36
+#define PMIC_REG_GPIO0P4CTLI 0x37
+#define PMIC_REG_GPIO0P5CTLI 0x38
+#define PMIC_REG_GPIO0P6CTLI 0x39
+#define PMIC_REG_GPIO1P0CTLO 0x3B
+#define PMIC_REG_GPIO1P1CTLO 0x3C
+#define PMIC_REG_GPIO1P2CTLO 0x3D
+#define PMIC_REG_GPIO1P3CTLO 0x3E
+#define PMIC_REG_GPIO1P4CTLO 0x3F
+#define PMIC_REG_GPIO1P5CTLO 0x40
+#define PMIC_REG_GPIO1P6CTLO 0x41
+#define PMIC_REG_GPIO1P7CTLO 0x42
+#define PMIC_REG_GPIO1P0CTLI 0x43
+#define PMIC_REG_GPIO1P1CTLI 0x44
+#define PMIC_REG_GPIO1P2CTLI 0x45
+#define PMIC_REG_GPIO1P3CTLI 0x46
+#define PMIC_REG_GPIO1P4CTLI 0x47
+#define PMIC_REG_GPIO1P5CTLI 0x48
+#define PMIC_REG_GPIO1P6CTLI 0x49
+#define PMIC_REG_GPIO1P7CTLI 0x4A
+#define PMIC_REG_PWM0CLKDIV 0x4B
+#define PMIC_REG_PWM1CLKDIV 0x4C
+#define PMIC_REG_PWM0DUTYCYCLE 0x4E
+#define PMIC_REG_PWM1DUTYCYCLE 0x4F
+#define PMIC_REG_BACKLIGHT_EN 0x51
+#define PMIC_REG_PANEL_EN 0x52
+#define PMIC_REG_COLD_RESET 0x53
+#define PMIC_REG_VDDQVTTCNT 0x55
+#define PMIC_REG_V1P8ACNT 0x56
+#define PMIC_REG_V1P8SXCNT 0x57
+#define PMIC_REG_VDDQCNT 0x58
+#define PMIC_REG_V1P2ACNT 0x59
+#define PMIC_REG_V1P2SXCNT 0x5A
+#define PMIC_REG_VSYSACNT 0x5B
+#define PMIC_REG_VSYSSXCNT 0x5C
+#define PMIC_REG_V2P85SXCNT 0x5D
+#define PMIC_REG_V3P3ACNT 0x5E
+#define PMIC_REG_V3P3SXCNT 0x5F
+#define PMIC_REG_V5P0ACNT 0x60
+#define PMIC_REG_VBUSCNT 0x61
+#define PMIC_MASK_VBUSSEL BIT01 //0 = VBUS_EN is controlled by ULPI_VBUS_EN
+#define PMIC_MASK_VBUSEN BIT00
+
+#define PMIC_REG_VHDMICNT 0x62
+#define PMIC_VR_SEL_BIT BIT01
+#define PMIC_VR_EN_BIT BIT00
+#define PMIC_VR_LPEN_BIT BIT02
+#define PMIC_REG_PBCONFIG1 0x6A
+#define PMIC_REG_PWROKCNTL 0x6B
+#define PMIC_REG_DEBUG0 0x6C
+#define PMIC_REG_FWREV 0x6D
+#define PMIC_REG_BATID_WIAT 0x71
+#define PMIC_REG_MANCONV0 0x72
+#define PMIC_MASK_BATID BIT01
+#define PMIC_MASK_VBAT BIT00
+
+#define PMIC_REG_MANCONV1 0x73
+
+#define PMIC_REG_SYS0_THRM_RSLTH 0x74
+#define PMIC_REG_SYS0_THRM_RSLTL 0x75
+#define PMIC_REG_SYS1_THRM_RSLTH 0x76
+#define PMIC_REG_SYS1_THRM_RSLTL 0x77
+#define PMIC_REG_SYS2_THRM_RSLTH 0x78
+#define PMIC_REG_SYS2_THRM_RSLTL 0x79
+#define PMIC_REG_BAT0_THRM_RSLTH 0x7A
+#define PMIC_REG_BAT0_THRM_RSLTL 0x7B
+#define PMIC_REG_BAT1_THRM_RSLTH 0x7C
+#define PMIC_REG_BAT1_THRM_RSLTL 0x7D
+#define PMIC_REG_PMIC_THRM_RSLTH 0x7E
+#define PMIC_REG_PMIC_THRM_RSLTL 0x7F
+#define PMIC_REG_VBATRSLTH 0x80
+#define PMIC_REG_VBATRSLTL 0x81
+#define PMIC_REG_BATIDRSLTH 0x82
+#define PMISC_MASK_BATID_HIGH (BIT01|BIT00)
+#define PMIC_REG_BATIDRSLTL 0x83
+
+#define PMIC_REG_PPLTMONCTL 0x84
+#define PMIC_REG_PPLTRSLTH 0x85
+#define PMIC_REG_PPLTRSLTL 0x86
+#define PMIC_REG_VPPLTRSLTH 0x87
+#define PMIC_REG_VPPLTRSLTL 0x88
+#define PMIC_REG_IPPLTRSLTH 0x89
+#define PMIC_REG_IPPLTRSLTL 0x8A
+#define PMIC_REG_SRCWAKECFG 0x8B
+#define PMIC_MASK_ADPWAKEEN BIT02
+#define PMIC_MASK_USBWAKEEN BIT01
+#define PMIC_MASK_BATWAKEEN BIT00
+#define PMIC_REG_PWRSEQCFG 0x8C
+#define PMIC_REG_THRMMONCTL0 0x8E
+#define PMIC_MASK_SYSFRQS BIT06
+#define PMIC_MASK_BATFRQS BIT05
+#define PMIC_MASK_SYSFRQA (BIT04|BIT03)
+#define PMIC_MASK_BATFRQA (BIT02|BIT01)
+#define PMIC_MASK_THERM_EN BIT00
+
+#define PMIC_REG_THRMMONCTL1 0x8F
+#define PMIC_MASK_PMICFRQS BIT02
+#define PMIC_MASK_PMICFRQA (BIT01|BIT00)
+
+#define PMIC_REG_TS_ENABLE 0x90
+#define PMIC_MASK_PMIC_EN BIT05
+#define PMIC_MASK_BAT1_EN BIT04
+#define PMIC_MASK_BAT0_EN BIT03
+#define PMIC_MASK_SYS2_EN BIT02
+#define PMIC_MASK_SYS1_EN BIT01
+#define PMIC_MASK_SYS0_EN BIT00
+#define PMIC_MASK_ALL_EN (BIT05|BIT04|BIT03|BIT02|BIT01|BIT00)
+
+#define PMIC_REG_TS__CRIT_ENABLE 0x91
+#define PMIC_MASK_PMIC_CRIT_EN BIT05
+#define PMIC_MASK_BAT1_CRIT_EN BIT04
+#define PMIC_MASK_BAT0_CRIT_EN BIT03
+#define PMIC_MASK_SYS2_CRIT_EN BIT02
+#define PMIC_MASK_SYS1_CRIT_EN BIT01
+#define PMIC_MASK_SYS0_CRIT_EN BIT00
+#define PMIC_MASK_ALL_EN (BIT05|BIT04|BIT03|BIT02|BIT01|BIT00)
+
+#define PMIC_REG_TS_A0_STATUS 0x92
+#define PMIC_REG_TS_A1_STATUS 0x93
+#define PMIC_REG_SYS0_THRMALRT0_H 0x94
+#define PMIC_REG_SYS0_THRMALRT0_L 0x95
+#define PMIC_REG_SYS0_THRMALRT1_H 0x96
+#define PMIC_REG_SYS0_THRMALRT1_L 0x97
+#define PMIC_REG_SYS0_THRMALRT2_H 0xC1
+#define PMIC_REG_SYS0_THRMALRT2_L 0xC2
+#define PMIC_REG_SYS0_THRMALRT3_H 0xC3
+#define PMIC_REG_SYS0_THRMALRT3_L 0xC4
+#define PMIC_REG_SYS0_THRMCRIT 0x98
+#define PMIC_REG_SYS1_THRMALRT0_H 0x99
+#define PMIC_REG_SYS1_THRMALRT0_L 0x9A
+#define PMIC_REG_SYS1_THRMALRT1_H 0x9B
+#define PMIC_REG_SYS1_THRMALRT1_L 0x9C
+#define PMIC_REG_SYS1_THRMCRIT 0x9D
+#define PMIC_REG_SYS1_THRMALRT2_H 0xC5
+#define PMIC_REG_SYS1_THRMALRT2_L 0xC6
+#define PMIC_REG_SYS1_THRMALRT3_H 0xC7
+#define PMIC_REG_SYS1_THRMALRT3_L 0xC8
+#define PMIC_REG_SYS2_THRMALRT0_H 0x9E
+#define PMIC_REG_SYS2_THRMALRT0_L 0x9F
+#define PMIC_REG_SYS2_THRMALRT1_H 0xA0
+#define PMIC_REG_SYS2_THRMALRT1_L 0xA1
+#define PMIC_REG_SYS2_THRMCRIT 0xA2
+#define PMIC_REG_SYS2_THRMALRT2_H 0xC9
+#define PMIC_REG_SYS2_THRMALRT2_L 0xCA
+#define PMIC_REG_SYS2_THRMALRT3_H 0xCB
+#define PMIC_REG_SYS2_THRMALRT3_L 0xCC
+#define PMIC_REG_BAT0_THRMALRT0_H 0xA3
+#define PMIC_REG_BAT0_THRMALRT0_L 0xA4
+#define PMIC_REG_BAT0_THRMALRT1_H 0xA5
+#define PMIC_REG_BAT0_THRMALRT1_L 0xA6
+#define PMIC_REG_BAT0_THRMCRIT_H 0xA7
+#define PMIC_REG_BAT0_THRMCRIT_L 0xA8
+#define PMIC_REG_BAT0_THRMALRT2_H 0xCD
+#define PMIC_REG_BAT0_THRMALRT2_L 0xCE
+#define PMIC_REG_BAT0_THRMALRT3_H 0xCF
+#define PMIC_REG_BAT0_THRMALRT3_L 0xD0
+#define PMIC_REG_BAT1_THRMALRT0_H 0xA9
+#define PMIC_REG_BAT1_THRMALRT0_L 0xAA
+#define PMIC_REG_BAT1_THRMALRT1_H 0xAB
+#define PMIC_REG_BAT1_THRMALRT1_L 0xAC
+#define PMIC_REG_BAT1_THRMCRIT_H 0xAD
+#define PMIC_REG_BAT1_THRMCRIT_L 0xAE
+#define PMIC_REG_BAT1_THRMALRT2_H 0xD1
+#define PMIC_REG_BAT1_THRMALRT2_L 0xD2
+#define PMIC_REG_BAT1_THRMALRT3_H 0xD3
+#define PMIC_REG_BAT1_THRMALRT3_L 0xD4
+#define PMIC_REG_PMIC_THRMALRT0_H 0xAF
+#define PMIC_REG_PMIC_THRMALRT0_L 0xB0
+#define PMIC_REG_PMIC_THRMALRT1_H 0xB1
+#define PMIC_REG_PMIC_THRMALRT1_L 0xB2
+#define PMIC_REG_PMIC_THRMCRIT 0xB3
+#define PMIC_REG_PMIC_THRMALRT2_H 0xD5
+#define PMIC_REG_PMIC_THRMALRT2_L 0xD6
+#define PMIC_REG_PMIC_THRMALRT3_H 0xD7
+#define PMIC_REG_PMIC_THRMALRT3_L 0xD8
+#define PMIC_REG_VWARNA_CFG 0xB4
+#define PMIC_MASK_VWARNA_EN BIT03
+#define PMIC_REG_VWARNB_CFG 0xB5
+#define PMIC_MASK_VWARNB_EN BIT03
+#define PMIC_REG_VCRIT_CFG 0xB6
+#define PMIC_MASK_VCRITSDWNEN BIT04
+#define PMIC_MASK_VCRIT_EN BIT03
+#define PMIC_REG_BCUDISA_BEH 0xB7
+#define PMIC_MASK_STICKY BIT02 //0--output signal assertion is not sticky
+#define PMIC_MASK_PIN_POL BIT01 //0--active low
+#define PMIC_MASK_EN BIT00 // 0-disable behavivor
+
+#define PMIC_REG_BCUDISB_BEH 0xB8
+#define PMIC_REG_BCUDISCRIT_BEH 0xB9
+#define PMIC_REG_BCUPROCHOT_B_BEH 0xBA
+#define PMIC_REG_SBCUIRQ 0xBB
+#define PMIC_REG_SBCUCTRL 0xBC
+#define PMIC_REG_TS_CRIT_ST 0xBD
+
+#define PMIC_REG_TS_A2_STATUS 0xBF
+#define PMIC_REG_TS_A3_STATUS 0xC0
+
+#define PMIC_REG_ALERT0LOCK 0xC5
+#define PMIC_MASK_A0LOCK BIT00
+#define PMIC_REG_VREFDQ1CNT 0xC6
+
+#define PMIC_REG_THRMIRQ3 0xD9
+#define PMIC_REG_MTHRMIRQ3 0xDA
+#define PMIC_REG_UIBCONFIG 0xDB
+#define PMIC_REG_PSOCMONCTL 0xDC
+#define PMIC_REG_PSOCRSLTH 0xDD
+#define PMIC_REG_PSOCRSLTL 0xDE
+#define PMIC_REG_VSOCRSLTH 0xDF
+#define PMIC_REG_VSOCRSLTL 0xE0
+#define PMIC_REG_ISOCRSLTH 0xE1
+#define PMIC_REG_ISOCRSLTL 0xE2
+#define PMIC_REG_SOC_PALERTH 0xE3
+#define PMIC_REG_SOC_PALERTL 0xE4
+
+//Changes specific to Dialog PMIC
+#define PMIC_REG_PWRSEQCFG_DIALOG_B0 0xE0
+#define PMIC_REG_SRCWAKECFG_DIALOG_B0 0xDF
+#define PMIC_MASK_ILIM500 BIT04 // choose the current limit source for the external charger. 1 = 500mA USB charger available 0 = 100mA ..
+#define PMIC_MASK_VCCPWRCFG BIT03 // de-assert VCCAPWROK when PMIC enters SOC S0IX state.
+#define PMIC_MASK_SUSPWRDNNACK BIT02 // when SLP_S3_B=0 it decides if the power sequencer should go to SOC_G3 if SUSPWRDNNACK is asserted
+#define PMIC_MASK_DTPWROK (BIT01|BIT00) // The delay time for Core rails valid to VCCAPWEROK and COREPWROK assertion 00-1ms 01-10ms 10-100ms 11-120ms
+
+#endif
diff --git a/ChvRefCodePkg/Include/PnP/Aunit_bios_settings.h b/ChvRefCodePkg/Include/PnP/Aunit_bios_settings.h new file mode 100644 index 0000000000..4d58fa4496 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/Aunit_bios_settings.h @@ -0,0 +1,125 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef AUNIT_BIOS_SETTINGS_HH
+#define AUNIT_BIOS_SETTINGS_HH
+
+#define AUNIT_VALUEFORPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x00, 0x18, 0, 0, 0x1, /* ACKGATE.CONFIG_REGS */ \
+ 0x00, 0x18, 1, 1, 0x1, /* ACKGATE.TA_DATA_QUEUE */ \
+ 0x00, 0x18, 2, 2, 0x1, /* ACKGATE.TA_REQ_QUEUE */ \
+ 0x00, 0x18, 3, 3, 0x1, /* ACKGATE.AT_DATA_QUEUE */ \
+ 0x00, 0x18, 4, 4, 0x1, /* ACKGATE.AT_REQ_QUEUE */ \
+ 0x00, 0x18, 5, 5, 0x1, /* ACKGATE.AIOSFDOWN_CMD_DATA_BUFF */ \
+ 0x00, 0x18, 6, 6, 0x1, /* ACKGATE.AIOSFDOWN_CMD_DRVR */ \
+ 0x00, 0x18, 7, 7, 0x1, /* ACKGATE.AREQDOWN_DATA_QUEUE */ \
+ 0x00, 0x18, 8, 8, 0x1, /* ACKGATE.AREQDOWN_RSP_QUEUE */ \
+ 0x00, 0x18, 9, 9, 0x1, /* ACKGATE.AREQUP_DATA_QUEUE */ \
+ 0x00, 0x18, 10, 10, 0x1, /* ACKGATE.AREQUP_CMD_QUEUE */ \
+ 0x00, 0x18, 11, 11, 0x1, /* ACKGATE.ASCLUP_DATA_QUEUE */ \
+ 0x00, 0x18, 12, 12, 0x1, /* ACKGATE.ASCLUP_CMD_QUEUE */ \
+ 0x00, 0x18, 14, 14, 0x1, /* ACKGATE.ASCLUP_IOSF_ADAPTER */ \
+ 0x00, 0x18, 15, 15, 0x1, /* ACKGATE.AIOSFDOWN_DATA */ \
+ 0x00, 0x18, 16, 16, 0x1, /* ACKGATE.ASCLUP_FAIR_ARBITER */ \
+ 0x00, 0x18, 17, 17, 0x1, /* ACKGATE.AREQDOWN_CREDIT */ \
+ 0x00, 0x18, 18, 18, 0x1, /* ACKGATE.AREQDOWN_TAREQQ */ \
+ 0x00, 0x18, 19, 19, 0x1, /* ACKGATE.AREQTAHACK */ \
+ 0x00, 0x18, 20, 20, 0x1, /* ACKGATE.AREQUP_MIRROR */ \
+ 0x00, 0x18, 21, 21, 0x1, /* ACKGATE.AREQDOWN_SCL0_ARB */ \
+ 0x00, 0x18, 22, 22, 0x1, /* ACKGATE.AMESSAGE_MSGIF */ \
+ 0x00, 0x20, 8, 0, 0x1, /* AISOCHCTL.VC1_ISOC_CH_DEFAULT_DDLINE_DLY */ \
+ 0x00, 0x21, 31, 31, 0x1, /* AVCCTL.EFFICIENT_PERF_UP_EN */ \
+ 0x00, 0xc0, 3, 0, 0x4, /* AARBCTL0.IOSF0VC0_WGT */ \
+ 0x00, 0xc0, 7, 4, 0x4, /* AARBCTL0.IOSF0VC1_WGT */ \
+ 0x00, 0xc0, 11, 8, 0x4, /* AARBCTL0.IOSF0VC2_WGT */ \
+ 0x00, 0xd0, 3, 0, 0x8, /* ADNARBCTL.VC0_WGT */ \
+ 0x00, 0xd0, 7, 4, 0x4, /* ADNARBCTL.VC1_WGT */ \
+ 0x00, 0xd0, 11, 8, 0x4, /* ADNARBCTL.VC2_WGT */ \
+ 0x00, 0xd1, 3, 0, 0x4, /* AVC0ARBCTL.BA_WGT */ \
+ 0x00, 0xd1, 7, 4, 0x4, /* AVC0ARBCTL.TA_WGT */ \
+/* end of AUNIT_VALUEFORPERF_VALUES_PLATFORM_DEFAULT */
+
+#define AUNIT_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x00, 0x18, 0, 0, 0x1, /* ACKGATE.CONFIG_REGS */ \
+ 0x00, 0x18, 1, 1, 0x1, /* ACKGATE.TA_DATA_QUEUE */ \
+ 0x00, 0x18, 2, 2, 0x1, /* ACKGATE.TA_REQ_QUEUE */ \
+ 0x00, 0x18, 3, 3, 0x1, /* ACKGATE.AT_DATA_QUEUE */ \
+ 0x00, 0x18, 4, 4, 0x1, /* ACKGATE.AT_REQ_QUEUE */ \
+ 0x00, 0x18, 5, 5, 0x1, /* ACKGATE.AIOSFDOWN_CMD_DATA_BUFF */ \
+ 0x00, 0x18, 6, 6, 0x1, /* ACKGATE.AIOSFDOWN_CMD_DRVR */ \
+ 0x00, 0x18, 7, 7, 0x1, /* ACKGATE.AREQDOWN_DATA_QUEUE */ \
+ 0x00, 0x18, 8, 8, 0x1, /* ACKGATE.AREQDOWN_RSP_QUEUE */ \
+ 0x00, 0x18, 9, 9, 0x1, /* ACKGATE.AREQUP_DATA_QUEUE */ \
+ 0x00, 0x18, 10, 10, 0x1, /* ACKGATE.AREQUP_CMD_QUEUE */ \
+ 0x00, 0x18, 11, 11, 0x1, /* ACKGATE.ASCLUP_DATA_QUEUE */ \
+ 0x00, 0x18, 12, 12, 0x1, /* ACKGATE.ASCLUP_CMD_QUEUE */ \
+ 0x00, 0x18, 14, 14, 0x1, /* ACKGATE.ASCLUP_IOSF_ADAPTER */ \
+ 0x00, 0x18, 15, 15, 0x1, /* ACKGATE.AIOSFDOWN_DATA */ \
+ 0x00, 0x18, 16, 16, 0x1, /* ACKGATE.ASCLUP_FAIR_ARBITER */ \
+ 0x00, 0x18, 17, 17, 0x1, /* ACKGATE.AREQDOWN_CREDIT */ \
+ 0x00, 0x18, 18, 18, 0x1, /* ACKGATE.AREQDOWN_TAREQQ */ \
+ 0x00, 0x18, 19, 19, 0x1, /* ACKGATE.AREQTAHACK */ \
+ 0x00, 0x18, 20, 20, 0x1, /* ACKGATE.AREQUP_MIRROR */ \
+ 0x00, 0x18, 21, 21, 0x1, /* ACKGATE.AREQDOWN_SCL0_ARB */ \
+ 0x00, 0x18, 22, 22, 0x1, /* ACKGATE.AMESSAGE_MSGIF */ \
+ 0x00, 0x20, 8, 0, 0x1, /* AISOCHCTL.VC1_ISOC_CH_DEFAULT_DDLINE_DLY */ \
+ 0x00, 0x21, 31, 31, 0x1, /* AVCCTL.EFFICIENT_PERF_UP_EN */ \
+ 0x00, 0xc0, 3, 0, 0x4, /* AARBCTL0.IOSF0VC0_WGT */ \
+ 0x00, 0xc0, 7, 4, 0x4, /* AARBCTL0.IOSF0VC1_WGT */ \
+ 0x00, 0xc0, 11, 8, 0x4, /* AARBCTL0.IOSF0VC2_WGT */ \
+ 0x00, 0xd0, 3, 0, 0x8, /* ADNARBCTL.VC0_WGT */ \
+ 0x00, 0xd0, 7, 4, 0x4, /* ADNARBCTL.VC1_WGT */ \
+ 0x00, 0xd0, 11, 8, 0x4, /* ADNARBCTL.VC2_WGT */ \
+ 0x00, 0xd1, 3, 0, 0x4, /* AVC0ARBCTL.BA_WGT */ \
+ 0x00, 0xd1, 7, 4, 0x4, /* AVC0ARBCTL.TA_WGT */ \
+/* end of AUNIT_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define AUNIT_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x00, 0x18, 0, 0, 0x1, /* ACKGATE.CONFIG_REGS */ \
+ 0x00, 0x18, 1, 1, 0x1, /* ACKGATE.TA_DATA_QUEUE */ \
+ 0x00, 0x18, 2, 2, 0x1, /* ACKGATE.TA_REQ_QUEUE */ \
+ 0x00, 0x18, 3, 3, 0x1, /* ACKGATE.AT_DATA_QUEUE */ \
+ 0x00, 0x18, 4, 4, 0x1, /* ACKGATE.AT_REQ_QUEUE */ \
+ 0x00, 0x18, 5, 5, 0x1, /* ACKGATE.AIOSFDOWN_CMD_DATA_BUFF */ \
+ 0x00, 0x18, 6, 6, 0x1, /* ACKGATE.AIOSFDOWN_CMD_DRVR */ \
+ 0x00, 0x18, 7, 7, 0x1, /* ACKGATE.AREQDOWN_DATA_QUEUE */ \
+ 0x00, 0x18, 8, 8, 0x1, /* ACKGATE.AREQDOWN_RSP_QUEUE */ \
+ 0x00, 0x18, 9, 9, 0x1, /* ACKGATE.AREQUP_DATA_QUEUE */ \
+ 0x00, 0x18, 10, 10, 0x1, /* ACKGATE.AREQUP_CMD_QUEUE */ \
+ 0x00, 0x18, 11, 11, 0x1, /* ACKGATE.ASCLUP_DATA_QUEUE */ \
+ 0x00, 0x18, 12, 12, 0x1, /* ACKGATE.ASCLUP_CMD_QUEUE */ \
+ 0x00, 0x18, 14, 14, 0x1, /* ACKGATE.ASCLUP_IOSF_ADAPTER */ \
+ 0x00, 0x18, 15, 15, 0x1, /* ACKGATE.AIOSFDOWN_DATA */ \
+ 0x00, 0x18, 16, 16, 0x1, /* ACKGATE.ASCLUP_FAIR_ARBITER */ \
+ 0x00, 0x18, 17, 17, 0x1, /* ACKGATE.AREQDOWN_CREDIT */ \
+ 0x00, 0x18, 18, 18, 0x1, /* ACKGATE.AREQDOWN_TAREQQ */ \
+ 0x00, 0x18, 19, 19, 0x1, /* ACKGATE.AREQTAHACK */ \
+ 0x00, 0x18, 20, 20, 0x1, /* ACKGATE.AREQUP_MIRROR */ \
+ 0x00, 0x18, 21, 21, 0x1, /* ACKGATE.AREQDOWN_SCL0_ARB */ \
+ 0x00, 0x18, 22, 22, 0x1, /* ACKGATE.AMESSAGE_MSGIF */ \
+ 0x00, 0x20, 8, 0, 0x1, /* AISOCHCTL.VC1_ISOC_CH_DEFAULT_DDLINE_DLY */ \
+ 0x00, 0xc0, 3, 0, 0x4, /* AARBCTL0.IOSF0VC0_WGT */ \
+ 0x00, 0xc0, 7, 4, 0x4, /* AARBCTL0.IOSF0VC1_WGT */ \
+ 0x00, 0xc0, 11, 8, 0x4, /* AARBCTL0.IOSF0VC2_WGT */ \
+ 0x00, 0xd0, 3, 0, 0x8, /* ADNARBCTL.VC0_WGT */ \
+ 0x00, 0xd0, 7, 4, 0x4, /* ADNARBCTL.VC1_WGT */ \
+ 0x00, 0xd0, 11, 8, 0x4, /* ADNARBCTL.VC2_WGT */ \
+ 0x00, 0xd1, 3, 0, 0x4, /* AVC0ARBCTL.BA_WGT */ \
+ 0x00, 0xd1, 7, 4, 0x4, /* AVC0ARBCTL.TA_WGT */ \
+/* end of AUNIT_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // AUNIT_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/Bunit_bios_settings.h b/ChvRefCodePkg/Include/PnP/Bunit_bios_settings.h new file mode 100644 index 0000000000..2311454ff8 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/Bunit_bios_settings.h @@ -0,0 +1,135 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef BUNIT_BIOS_SETTINGS_HH
+#define BUNIT_BIOS_SETTINGS_HH
+
+#define BUNIT_VALUEFORPERF_VALUES_PLATFORM_DEFAULT \
+ 0x03, 0xb, 5, 0, 0x2f, /* BALIMIT0.AGENT0_LIMIT */ \
+ 0x03, 0xb, 13, 8, 0x2f, /* BALIMIT0.AGENT1_LIMIT */ \
+ 0x03, 0xb, 21, 16, 0x2f, /* BALIMIT0.AGENT2_LIMIT */ \
+ 0x03, 0xb, 29, 24, 0x2f, /* BALIMIT0.AGENT3_LIMIT */ \
+ 0x03, 0xc, 5, 0, 0x2f, /* BALIMIT1.AGENT4_LIMIT */ \
+ 0x03, 0xc, 13, 8, 0x2f, /* BALIMIT1.AGENT5_LIMIT */ \
+ 0x03, 0xc, 21, 16, 0x2f, /* BALIMIT1.AGENT6_LIMIT */ \
+ 0x03, 0xc, 29, 24, 0x2f, /* BALIMIT1.AGENT7_LIMIT */ \
+ 0x03, 0xd, 5, 0, 0x2f, /* BALIMIT2.AGENT8_LIMIT */ \
+ 0x03, 0xd, 13, 8, 0x2f, /* BALIMIT2.AGENT9_LIMIT */ \
+ 0x03, 0xd, 21, 16, 0x2f, /* BALIMIT2.AGENT10_LIMIT */ \
+ 0x03, 0xd, 29, 24, 0x2f, /* BALIMIT2.AGENT11_LIMIT */ \
+ 0x03, 0xe, 5, 0, 0x2f, /* BALIMIT3.AGENT12_LIMIT */ \
+ 0x03, 0xe, 13, 8, 0x2f, /* BALIMIT3.AGENT13_LIMIT */ \
+ 0x03, 0xe, 21, 16, 0x2f, /* BALIMIT3.AGENT14_LIMIT */ \
+ 0x03, 0xe, 29, 24, 0x2f, /* BALIMIT3.AGENT15_LIMIT */ \
+ 0x03, 0x12, 7, 6, 0x1, /* BCOSCAT.COS_CAT_AGENT3 */ \
+ 0x03, 0x12, 9, 8, 0x1, /* BCOSCAT.COS_CAT_AGENT4 */ \
+ 0x03, 0x12, 13, 12, 0x1, /* BCOSCAT.COS_CAT_AGENT6 */ \
+ 0x03, 0x14, 5, 0, 0x10, /* BFLWT.READ_WEIGHTS */ \
+ 0x03, 0x16, 5, 0, 0x10, /* BISOCWT.NON_ISOC_REQUEST_WEIGHTS */ \
+ 0x03, 0x16, 13, 8, 0x3f, /* BISOCWT.ISOC_REQUEST_WEIGHTS */ \
+ 0x03, 0x18, 6, 0, 0x20, /* BSCHCTRL0.BE_OOO_SCH_LIMIT */ \
+ 0x03, 0x18, 23, 21, 0x6, /* BSCHCTRL0.PAGE_HIT_DELAY */ \
+ 0x03, 0x18, 31, 24, 0x7f, /* BSCHCTRL0.BEST_EFFORT_MAX_LATENCY */ \
+ 0x03, 0x3b, 23, 16, 0x4, /* BDEBUG0.CASUAL_TIMER */ \
+ 0x03, 0x3c, 2, 2, 0x0, /* BDEBUG1.EXIT_SR_FOR_CASUAL_FLUSH */ \
+ 0x03, 0x3c, 31, 16, 0x0, /* BDEBUG1.AGENT_WEIGHT_ENABLE */ \
+ 0x03, 0x3d, 0, 0, 0x1, /* BCTRL.REQUESTCLK_GATE_EN */ \
+ 0x03, 0x3d, 1, 1, 0x1, /* BCTRL.MASTERCLK_GATE_EN */ \
+ 0x03, 0x3d, 2, 2, 0x1, /* BCTRL.BECLK_GATE_EN */ \
+ 0x03, 0x3d, 14, 14, 0x1, /* BCTRL.BANK_STATUS_ENABLE */ \
+ 0x03, 0x7, 31, 24, 0x30, /* BWFLUSH.FLUSH_THRSHOLD */ \
+ 0x03, 0x7, 15, 8, 0x10, /* BWFLUSH.DIRTY_LWM */ \
+ 0x03, 0x7, 7, 0, 0x18, /* BWFLUSH.DIRTY_HWM */ \
+
+/* end of BUNIT_VALUEFORPERF_VALUES_PLATFORM_DEFAULT */
+
+#define BUNIT_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, Offset, MSB, LSB, Value */ \
+ 0x03, 0xb, 5, 0, 0x2f, /* BALIMIT0.AGENT0_LIMIT */ \
+ 0x03, 0xb, 13, 8, 0x2f, /* BALIMIT0.AGENT1_LIMIT */ \
+ 0x03, 0xb, 21, 16, 0x2f, /* BALIMIT0.AGENT2_LIMIT */ \
+ 0x03, 0xb, 29, 24, 0x2b, /* BALIMIT0.AGENT3_LIMIT */ \
+ 0x03, 0xc, 5, 0, 0x2f, /* BALIMIT1.AGENT4_LIMIT */ \
+ 0x03, 0xc, 13, 8, 0x2f, /* BALIMIT1.AGENT5_LIMIT */ \
+ 0x03, 0xc, 21, 16, 0x2f, /* BALIMIT1.AGENT6_LIMIT */ \
+ 0x03, 0xc, 29, 24, 0x2f, /* BALIMIT1.AGENT7_LIMIT */ \
+ 0x03, 0xd, 5, 0, 0x2f, /* BALIMIT2.AGENT8_LIMIT */ \
+ 0x03, 0xd, 13, 8, 0x2f, /* BALIMIT2.AGENT9_LIMIT */ \
+ 0x03, 0xd, 21, 16, 0x2f, /* BALIMIT2.AGENT10_LIMIT */ \
+ 0x03, 0xd, 29, 24, 0x2f, /* BALIMIT2.AGENT11_LIMIT */ \
+ 0x03, 0xe, 5, 0, 0x2f, /* BALIMIT3.AGENT12_LIMIT */ \
+ 0x03, 0xe, 13, 8, 0x2f, /* BALIMIT3.AGENT13_LIMIT */ \
+ 0x03, 0xe, 21, 16, 0x2f, /* BALIMIT3.AGENT14_LIMIT */ \
+ 0x03, 0xe, 29, 24, 0x2f, /* BALIMIT3.AGENT15_LIMIT */ \
+ 0x03, 0x12, 7, 6, 0x1, /* BCOSCAT.COS_CAT_AGENT3 */ \
+ 0x03, 0x12, 9, 8, 0x1, /* BCOSCAT.COS_CAT_AGENT4 */ \
+ 0x03, 0x12, 13, 12, 0x1, /* BCOSCAT.COS_CAT_AGENT6 */ \
+ 0x03, 0x14, 5, 0, 0x10, /* BFLWT.READ_WEIGHTS */ \
+ 0x03, 0x16, 13, 8, 0x3f, /* BISOCWT.ISOC_REQUEST_WEIGHTS */ \
+ 0x03, 0x18, 6, 0, 0x20, /* BSCHCTRL0.BE_OOO_SCH_LIMIT */ \
+ 0x03, 0x18, 23, 21, 0x6, /* BSCHCTRL0.PAGE_HIT_DELAY */ \
+ 0x03, 0x18, 31, 24, 0xff, /* BSCHCTRL0.BEST_EFFORT_MAX_LATENCY */ \
+ 0x03, 0x3b, 23, 16, 0x4, /* BDEBUG0.CASUAL_TIMER */ \
+ 0x03, 0x3c, 2, 2, 0x0, /* BDEBUG1.EXIT_SR_FOR_CASUAL_FLUSH */ \
+ 0x03, 0x3d, 0, 0, 0x1, /* BCTRL.REQUESTCLK_GATE_EN */ \
+ 0x03, 0x3d, 2, 2, 0x1, /* BCTRL.BECLK_GATE_EN */ \
+ 0x03, 0x3d, 14, 14, 0x1, /* BCTRL.BANK_STATUS_ENABLE */ \
+ 0x03, 0x3e, 31, 16, 0xffff, /* BTHCTRL.AGENT_THROTTLING_ENABLE */ \
+ 0x03, 0x3f, 7, 0, 0xaa, /* BTHMASK.READ_MASK */ \
+ 0x03, 0x3f, 15, 8, 0xaa, /* BTHMASK.WRITE_MASK */ \
+/* end of BUNIT_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define BUNIT_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, Offset, MSB, LSB, Value */ \
+ 0x03, 0x7, 7, 0, 0x18, \
+ 0x03, 0x7, 15, 8, 0x10, \
+ 0x03, 0x7, 31, 24, 0x30, \
+ 0x03, 0xb, 5, 0, 0x2f, /* BALIMIT0.AGENT0_LIMIT */ \
+ 0x03, 0xb, 13, 8, 0x2f, /* BALIMIT0.AGENT1_LIMIT */ \
+ 0x03, 0xb, 21, 16, 0x2f, /* BALIMIT0.AGENT2_LIMIT */ \
+ 0x03, 0xb, 29, 24, 0x2f, /* BALIMIT0.AGENT3_LIMIT */ \
+ 0x03, 0xc, 5, 0, 0x2f, /* BALIMIT1.AGENT4_LIMIT */ \
+ 0x03, 0xc, 13, 8, 0x2f, /* BALIMIT1.AGENT5_LIMIT */ \
+ 0x03, 0xc, 21, 16, 0x2f, /* BALIMIT1.AGENT6_LIMIT */ \
+ 0x03, 0xc, 29, 24, 0x2f, /* BALIMIT1.AGENT7_LIMIT */ \
+ 0x03, 0xd, 5, 0, 0x2f, /* BALIMIT2.AGENT8_LIMIT */ \
+ 0x03, 0xd, 13, 8, 0x2f, /* BALIMIT2.AGENT9_LIMIT */ \
+ 0x03, 0xd, 21, 16, 0x2f, /* BALIMIT2.AGENT10_LIMIT */ \
+ 0x03, 0xd, 29, 24, 0x2f, /* BALIMIT2.AGENT11_LIMIT */ \
+ 0x03, 0xe, 5, 0, 0x2f, /* BALIMIT3.AGENT12_LIMIT */ \
+ 0x03, 0xe, 13, 8, 0x2f, /* BALIMIT3.AGENT13_LIMIT */ \
+ 0x03, 0xe, 21, 16, 0x2f, /* BALIMIT3.AGENT14_LIMIT */ \
+ 0x03, 0xe, 29, 24, 0x2f, /* BALIMIT3.AGENT15_LIMIT */ \
+ 0x03, 0x12, 7, 6, 0x1, /* BCOSCAT.COS_CAT_AGENT3 */ \
+ 0x03, 0x12, 9, 8, 0x1, /* BCOSCAT.COS_CAT_AGENT4 */ \
+ 0x03, 0x12, 13, 12, 0x1, /* BCOSCAT.COS_CAT_AGENT6 */ \
+ 0x03, 0x14, 5, 0, 0x10, /* BFLWT.READ_WEIGHTS */ \
+ 0x03, 0x16, 5, 0, 0x10, /* BISOCWT.NON_ISOC_REQUEST_WEIGHTS */ \
+ 0x03, 0x16, 13, 8, 0x3f, /* BISOCWT.ISOC_REQUEST_WEIGHTS */ \
+ 0x03, 0x18, 6, 0, 0x20, /* BSCHCTRL0.BE_OOO_SCH_LIMIT */ \
+ 0x03, 0x18, 23, 21, 0x6, /* BSCHCTRL0.PAGE_HIT_DELAY */ \
+ 0x03, 0x18, 31, 24, 0x7f, /* BSCHCTRL0.BEST_EFFORT_MAX_LATENCY */ \
+ 0x03, 0x3b, 7, 0, 0x1, \
+ 0x03, 0x3b, 23, 16, 0x4, /* BDEBUG0.CASUAL_TIMER */ \
+ 0x03, 0x3b, 27, 25, 0x1, \
+ 0x03, 0x3c, 2, 2, 0x0, /* BDEBUG1.EXIT_SR_FOR_CASUAL_FLUSH */ \
+ 0x03, 0x3c, 31, 16, 0x0, /* BDEBUG1.AGENT_WEIGHT_ENABLE */ \
+ 0x03, 0x3d, 0, 0, 0x1, /* BCTRL.REQUESTCLK_GATE_EN */ \
+ 0x03, 0x3d, 1, 1, 0x1, /* BCTRL.MASTERCLK_GATE_EN */ \
+ 0x03, 0x3d, 2, 2, 0x1, /* BCTRL.BECLK_GATE_EN */ \
+ 0x03, 0x3d, 8, 8, 0x0, \
+ 0x03, 0x3d, 14, 14, 0x1, /* BCTRL.BANK_STATUS_ENABLE */ \
+/* end of BUNIT_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // BUNIT_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/Cunit_bios_settings.h b/ChvRefCodePkg/Include/PnP/Cunit_bios_settings.h new file mode 100644 index 0000000000..f018a3cc72 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/Cunit_bios_settings.h @@ -0,0 +1,39 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef CUNIT_BIOS_SETTINGS_HH
+#define CUNIT_BIOS_SETTINGS_HH
+
+#define CUNIT_VALUEFORPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x08, 0x43, 7, 0, 0x30, /* CUNIT_SSA_REGIONAL_TRUNKGATE_CTL.IDLE_CNT_VAL */ \
+ 0x08, 0x43, 16, 16, 0x1, /* CUNIT_SSA_REGIONAL_TRUNKGATE_CTL.IDLE_CNT_DEC_CTL */ \
+ 0x08, 0x43, 18, 18, 0x1, /* CUNIT_SSA_REGIONAL_TRUNKGATE_CTL.SSA_CORE_CLK_GATE_EN */ \
+/* end of CUNIT_VALUEFORPERF_VALUES_PLATFORM_DEFAULT */
+
+#define CUNIT_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x08, 0x43, 7, 0, 0x30, /* CUNIT_SSA_REGIONAL_TRUNKGATE_CTL.IDLE_CNT_VAL */ \
+ 0x08, 0x43, 16, 16, 0x1, /* CUNIT_SSA_REGIONAL_TRUNKGATE_CTL.IDLE_CNT_DEC_CTL */ \
+ 0x08, 0x43, 18, 18, 0x1, /* CUNIT_SSA_REGIONAL_TRUNKGATE_CTL.SSA_CORE_CLK_GATE_EN */ \
+/* end of CUNIT_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define CUNIT_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x08, 0x43, 7, 0, 0x30, /* CUNIT_SSA_REGIONAL_TRUNKGATE_CTL.IDLE_CNT_VAL */ \
+ 0x08, 0x43, 16, 16, 0x1, /* CUNIT_SSA_REGIONAL_TRUNKGATE_CTL.IDLE_CNT_DEC_CTL */ \
+ 0x08, 0x43, 18, 18, 0x1, /* CUNIT_SSA_REGIONAL_TRUNKGATE_CTL.SSA_CORE_CLK_GATE_EN */ \
+/* end of CUNIT_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // CUNIT_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/GCPunit_Config_bios_settings.h b/ChvRefCodePkg/Include/PnP/GCPunit_Config_bios_settings.h new file mode 100644 index 0000000000..d433e6605a --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/GCPunit_Config_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef GCPUNIT_CONFIG_BIOS_SETTINGS_HH
+#define GCPUNIT_CONFIG_BIOS_SETTINGS_HH
+
+#endif // GCPUNIT_CONFIG_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/MODMEM_ADPLL_bios_settings.h b/ChvRefCodePkg/Include/PnP/MODMEM_ADPLL_bios_settings.h new file mode 100644 index 0000000000..ccd5810017 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/MODMEM_ADPLL_bios_settings.h @@ -0,0 +1,19 @@ +/** @file
+ dunit address maps
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef MODMEM_ADPLL_BIOS_SETTINGS_HH
+#define MODMEM_ADPLL_BIOS_SETTINGS_HH
+
+#endif // MODMEM_ADPLL_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/MODMEM_CCC_bios_settings.h b/ChvRefCodePkg/Include/PnP/MODMEM_CCC_bios_settings.h new file mode 100644 index 0000000000..fadafdb373 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/MODMEM_CCC_bios_settings.h @@ -0,0 +1,19 @@ +/** @file
+ dunit address maps
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef MODMEM_CCC_BIOS_SETTINGS_HH
+#define MODMEM_CCC_BIOS_SETTINGS_HH
+
+#endif // MODMEM_CCC_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/MODMEM_DQ_bios_settings.h b/ChvRefCodePkg/Include/PnP/MODMEM_DQ_bios_settings.h new file mode 100644 index 0000000000..822c365dcc --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/MODMEM_DQ_bios_settings.h @@ -0,0 +1,19 @@ +/** @file
+ dunit address maps
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef MODMEM_DQ_BIOS_SETTINGS_HH
+#define MODMEM_DQ_BIOS_SETTINGS_HH
+
+#endif // MODMEM_DQ_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/SB_bios_settings.h b/ChvRefCodePkg/Include/PnP/SB_bios_settings.h new file mode 100644 index 0000000000..24a51786a1 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/SB_bios_settings.h @@ -0,0 +1,42 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef SB_BIOS_SETTINGS_HH
+#define SB_BIOS_SETTINGS_HH
+
+#define SB_VALUEFORPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x0a, 0x60, 31, 24, 0x7f, /* RAIL_CONFIGURATION_AND_STATUS_0.CURRENT_VID */ \
+ 0x0a, 0x61, 31, 24, 0x7f, /* RAIL_CONFIGURATION_AND_STATUS_1.CURRENT_VID */ \
+ 0x0a, 0x64, 31, 24, 0x7f, /* RAIL_CONFIGURATION_AND_STATUS_4.CURRENT_VID */ \
+ 0x0a, 0x65, 31, 24, 0x7f, /* RAIL_CONFIGURATION_AND_STATUS_5.CURRENT_VID */ \
+/* end of SB_VALUEFORPERF_VALUES_PLATFORM_DEFAULT */
+
+#define SB_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x0a, 0x60, 31, 24, 0x7f, /* RAIL_CONFIGURATION_AND_STATUS_0.CURRENT_VID */ \
+ 0x0a, 0x61, 31, 24, 0x7f, /* RAIL_CONFIGURATION_AND_STATUS_1.CURRENT_VID */ \
+ 0x0a, 0x64, 31, 24, 0x7f, /* RAIL_CONFIGURATION_AND_STATUS_4.CURRENT_VID */ \
+ 0x0a, 0x65, 31, 24, 0x7f, /* RAIL_CONFIGURATION_AND_STATUS_5.CURRENT_VID */ \
+/* end of SB_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define SB_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x0a, 0x60, 31, 24, 0x7f, /* RAIL_CONFIGURATION_AND_STATUS_0.CURRENT_VID */ \
+ 0x0a, 0x61, 31, 24, 0x7f, /* RAIL_CONFIGURATION_AND_STATUS_1.CURRENT_VID */ \
+ 0x0a, 0x64, 31, 24, 0x7f, /* RAIL_CONFIGURATION_AND_STATUS_4.CURRENT_VID */ \
+ 0x0a, 0x65, 31, 24, 0x7f, /* RAIL_CONFIGURATION_AND_STATUS_5.CURRENT_VID */ \
+/* end of SB_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // SB_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/SCC_Fabric_bios_settings.h b/ChvRefCodePkg/Include/PnP/SCC_Fabric_bios_settings.h new file mode 100644 index 0000000000..14c62a2436 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/SCC_Fabric_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef SCC_FABRIC_BIOS_SETTINGS_HH
+#define SCC_FABRIC_BIOS_SETTINGS_HH
+
+#endif // SCC_FABRIC_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/Tunit_bios_settings.h b/ChvRefCodePkg/Include/PnP/Tunit_bios_settings.h new file mode 100644 index 0000000000..e225df635b --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/Tunit_bios_settings.h @@ -0,0 +1,129 @@ +/** @file
+ ssa address map
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef TUNIT_BIOS_SETTINGS_HH
+#define TUNIT_BIOS_SETTINGS_HH
+
+#define TUNIT_VALUEFORPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x02, 0x3, 10, 10, 0x1, /* T_CTL.TG_DW_POST_PUSH_LOG */ \
+ 0x02, 0x3, 12, 12, 0x1, /* T_CTL.TG_NDRAMSNP */ \
+ 0x02, 0x3, 16, 16, 0x1, /* T_CTL.ENABLE_IN_ORDER_APIC */ \
+ 0x02, 0x3, 20, 20, 0x1, /* T_CTL.SPLIT_GOIWP_MODE */ \
+ 0x02, 0x4, 4, 1, 0x6, /* T_MISC_CTL.DPTE_CNT */ \
+ 0x02, 0x4, 18, 18, 0x1, /* T_MISC_CTL.DISABLE_IOSF_OUTBOUND_THROTTLE */ \
+ 0x02, 0x5, 0, 0, 0x1, /* T_CLKGATE_CTL.IOSF_SB_MSG_CLK_GATE_EN */ \
+ 0x02, 0x5, 1, 1, 0x1, /* T_CLKGATE_CTL.IOSF_SB_CFG_REG_CLK_GATE_EN */ \
+ 0x02, 0x5, 2, 2, 0x1, /* T_CLKGATE_CTL.TRKR_SB_CLK_GATE_EN */ \
+ 0x02, 0x5, 3, 3, 0x1, /* T_CLKGATE_CTL.TRKR_SB_VALID_CLK_GATE_EN */ \
+ 0x02, 0x5, 4, 4, 0x1, /* T_CLKGATE_CTL.TRKR_SB_VIOL_CLK_GATE_EN */ \
+ 0x02, 0x5, 5, 5, 0x1, /* T_CLKGATE_CTL.TRKR_SB_REQ_CLK_GATE_EN */ \
+ 0x02, 0x5, 6, 6, 0x1, /* T_CLKGATE_CTL.TRKR_SB_SNP_STAT_CLK_GATE_EN */ \
+ 0x02, 0x5, 7, 7, 0x1, /* T_CLKGATE_CTL.TRKR_SB_WRSTAT_CLK_GATE_EN */ \
+ 0x02, 0x5, 8, 8, 0x1, /* T_CLKGATE_CTL.TRKR_SB_B2X_DATSTAT_CLK_GATE_EN */ \
+ 0x02, 0x5, 9, 9, 0x1, /* T_CLKGATE_CTL.TRKR_SB_T2A_REQSTAT_CLK_GATE_EN */ \
+ 0x02, 0x5, 10, 10, 0x1, /* T_CLKGATE_CTL.TRKR_SB_S2C_RESP_CLK_GATE_EN */ \
+ 0x02, 0x5, 11, 11, 0x1, /* T_CLKGATE_CTL.TRKR_SB_OLDST_CLK_GATE_EN */ \
+ 0x02, 0x5, 12, 12, 0x1, /* T_CLKGATE_CTL.TRKR_SB_LLST_CLK_GATE_EN */ \
+ 0x02, 0x5, 13, 13, 0x1, /* T_CLKGATE_CTL.S2C_REQ_SEL_CLK_GATE_EN */ \
+ 0x02, 0x5, 14, 14, 0x1, /* T_CLKGATE_CTL.S2C_REQ_FIFO_CLK_GATE_EN */ \
+ 0x02, 0x5, 15, 15, 0x1, /* T_CLKGATE_CTL.C2APIC_FIFO_CLK_GATE_EN */ \
+ 0x02, 0x5, 16, 16, 0x1, /* T_CLKGATE_CTL.T2A_REQ_SEL_CLK_GATE_EN */ \
+ 0x02, 0x5, 17, 17, 0x1, /* T_CLKGATE_CTL.S2C_RESP_SEL_CLK_GATE_EN */ \
+ 0x02, 0x5, 18, 18, 0x1, /* T_CLKGATE_CTL.X2B_DATSEL_CLK_GATE_EN */ \
+ 0x02, 0x5, 19, 19, 0x1, /* T_CLKGATE_CTL.B2X_DATSEL_CLK_GATE_EN */ \
+ 0x02, 0x5, 20, 20, 0x1, /* T_CLKGATE_CTL.A2TAPIC_CLK_GATE_EN */ \
+ 0x02, 0x5, 21, 21, 0x1, /* T_CLKGATE_CTL.T2A_Q_CLK_GATE_EN */ \
+ 0x02, 0x5, 22, 22, 0x1, /* T_CLKGATE_CTL.A2T_Q_CLK_GATE_EN */ \
+ 0x02, 0x5, 23, 23, 0x1, /* T_CLKGATE_CTL.MON_LOG_CLK_GATE_EN */ \
+ 0x02, 0x5, 24, 24, 0x1, /* T_CLKGATE_CTL.XUNIT_1_CLK_GATE_EN */ \
+ 0x02, 0x5, 25, 25, 0x1, /* T_CLKGATE_CTL.XUNIT_2_CLK_GATE_EN */ \
+ 0x02, 0x5, 26, 26, 0x1, /* T_CLKGATE_CTL.XUNIT_3_CLK_GATE_EN */ \
+ 0x02, 0x5, 27, 27, 0x1, /* T_CLKGATE_CTL.XUNIT_4_CLK_GATE_EN */ \
+/* end of TUNIT_VALUEFORPERF_VALUES_PLATFORM_DEFAULT */
+
+#define TUNIT_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x02, 0x3, 10, 10, 0x1, /* T_CTL.TG_DW_POST_PUSH_LOG */ \
+ 0x02, 0x3, 12, 12, 0x1, /* T_CTL.TG_NDRAMSNP */ \
+ 0x02, 0x3, 16, 16, 0x1, /* T_CTL.ENABLE_IN_ORDER_APIC */ \
+ 0x02, 0x3, 20, 20, 0x1, /* T_CTL.SPLIT_GOIWP_MODE */ \
+ 0x02, 0x4, 0, 0, 0x1, /* T_MISC_CTL.DPTE_EN */ \
+ 0x02, 0x4, 4, 1, 0xa, /* T_MISC_CTL.DPTE_CNT */ \
+ 0x02, 0x4, 18, 18, 0x1, /* T_MISC_CTL.DISABLE_IOSF_OUTBOUND_THROTTLE */ \
+ 0x02, 0x5, 0, 0, 0x1, /* T_CLKGATE_CTL.IOSF_SB_MSG_CLK_GATE_EN */ \
+ 0x02, 0x5, 1, 1, 0x1, /* T_CLKGATE_CTL.IOSF_SB_CFG_REG_CLK_GATE_EN */ \
+ 0x02, 0x5, 2, 2, 0x1, /* T_CLKGATE_CTL.TRKR_SB_CLK_GATE_EN */ \
+ 0x02, 0x5, 3, 3, 0x1, /* T_CLKGATE_CTL.TRKR_SB_VALID_CLK_GATE_EN */ \
+ 0x02, 0x5, 4, 4, 0x1, /* T_CLKGATE_CTL.TRKR_SB_VIOL_CLK_GATE_EN */ \
+ 0x02, 0x5, 5, 5, 0x1, /* T_CLKGATE_CTL.TRKR_SB_REQ_CLK_GATE_EN */ \
+ 0x02, 0x5, 6, 6, 0x1, /* T_CLKGATE_CTL.TRKR_SB_SNP_STAT_CLK_GATE_EN */ \
+ 0x02, 0x5, 7, 7, 0x1, /* T_CLKGATE_CTL.TRKR_SB_WRSTAT_CLK_GATE_EN */ \
+ 0x02, 0x5, 8, 8, 0x1, /* T_CLKGATE_CTL.TRKR_SB_B2X_DATSTAT_CLK_GATE_EN */ \
+ 0x02, 0x5, 9, 9, 0x1, /* T_CLKGATE_CTL.TRKR_SB_T2A_REQSTAT_CLK_GATE_EN */ \
+ 0x02, 0x5, 10, 10, 0x1, /* T_CLKGATE_CTL.TRKR_SB_S2C_RESP_CLK_GATE_EN */ \
+ 0x02, 0x5, 11, 11, 0x1, /* T_CLKGATE_CTL.TRKR_SB_OLDST_CLK_GATE_EN */ \
+ 0x02, 0x5, 12, 12, 0x1, /* T_CLKGATE_CTL.TRKR_SB_LLST_CLK_GATE_EN */ \
+ 0x02, 0x5, 13, 13, 0x1, /* T_CLKGATE_CTL.S2C_REQ_SEL_CLK_GATE_EN */ \
+ 0x02, 0x5, 14, 14, 0x1, /* T_CLKGATE_CTL.S2C_REQ_FIFO_CLK_GATE_EN */ \
+ 0x02, 0x5, 15, 15, 0x1, /* T_CLKGATE_CTL.C2APIC_FIFO_CLK_GATE_EN */ \
+ 0x02, 0x5, 16, 16, 0x1, /* T_CLKGATE_CTL.T2A_REQ_SEL_CLK_GATE_EN */ \
+ 0x02, 0x5, 17, 17, 0x1, /* T_CLKGATE_CTL.S2C_RESP_SEL_CLK_GATE_EN */ \
+ 0x02, 0x5, 18, 18, 0x1, /* T_CLKGATE_CTL.X2B_DATSEL_CLK_GATE_EN */ \
+ 0x02, 0x5, 19, 19, 0x1, /* T_CLKGATE_CTL.B2X_DATSEL_CLK_GATE_EN */ \
+ 0x02, 0x5, 20, 20, 0x1, /* T_CLKGATE_CTL.A2TAPIC_CLK_GATE_EN */ \
+ 0x02, 0x5, 21, 21, 0x1, /* T_CLKGATE_CTL.T2A_Q_CLK_GATE_EN */ \
+ 0x02, 0x5, 22, 22, 0x1, /* T_CLKGATE_CTL.A2T_Q_CLK_GATE_EN */ \
+ 0x02, 0x5, 23, 23, 0x1, /* T_CLKGATE_CTL.MON_LOG_CLK_GATE_EN */ \
+ 0x02, 0x5, 24, 24, 0x1, /* T_CLKGATE_CTL.XUNIT_1_CLK_GATE_EN */ \
+ 0x02, 0x5, 25, 25, 0x1, /* T_CLKGATE_CTL.XUNIT_2_CLK_GATE_EN */ \
+ 0x02, 0x5, 26, 26, 0x1, /* T_CLKGATE_CTL.XUNIT_3_CLK_GATE_EN */ \
+ 0x02, 0x5, 27, 27, 0x1, /* T_CLKGATE_CTL.XUNIT_4_CLK_GATE_EN */ \
+/* end of TUNIT_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define TUNIT_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x02, 0x3, 12, 12, 0x1, /* T_CTL.TG_NDRAMSNP */ \
+ 0x02, 0x5, 0, 0, 0x1, /* T_CLKGATE_CTL.IOSF_SB_MSG_CLK_GATE_EN */ \
+ 0x02, 0x5, 1, 1, 0x1, /* T_CLKGATE_CTL.IOSF_SB_CFG_REG_CLK_GATE_EN */ \
+ 0x02, 0x5, 2, 2, 0x1, /* T_CLKGATE_CTL.TRKR_SB_CLK_GATE_EN */ \
+ 0x02, 0x5, 3, 3, 0x1, /* T_CLKGATE_CTL.TRKR_SB_VALID_CLK_GATE_EN */ \
+ 0x02, 0x5, 4, 4, 0x1, /* T_CLKGATE_CTL.TRKR_SB_VIOL_CLK_GATE_EN */ \
+ 0x02, 0x5, 5, 5, 0x1, /* T_CLKGATE_CTL.TRKR_SB_REQ_CLK_GATE_EN */ \
+ 0x02, 0x5, 6, 6, 0x1, /* T_CLKGATE_CTL.TRKR_SB_SNP_STAT_CLK_GATE_EN */ \
+ 0x02, 0x5, 7, 7, 0x1, /* T_CLKGATE_CTL.TRKR_SB_WRSTAT_CLK_GATE_EN */ \
+ 0x02, 0x5, 8, 8, 0x1, /* T_CLKGATE_CTL.TRKR_SB_B2X_DATSTAT_CLK_GATE_EN */ \
+ 0x02, 0x5, 9, 9, 0x1, /* T_CLKGATE_CTL.TRKR_SB_T2A_REQSTAT_CLK_GATE_EN */ \
+ 0x02, 0x5, 10, 10, 0x1, /* T_CLKGATE_CTL.TRKR_SB_S2C_RESP_CLK_GATE_EN */ \
+ 0x02, 0x5, 11, 11, 0x1, /* T_CLKGATE_CTL.TRKR_SB_OLDST_CLK_GATE_EN */ \
+ 0x02, 0x5, 12, 12, 0x1, /* T_CLKGATE_CTL.TRKR_SB_LLST_CLK_GATE_EN */ \
+ 0x02, 0x5, 13, 13, 0x1, /* T_CLKGATE_CTL.S2C_REQ_SEL_CLK_GATE_EN */ \
+ 0x02, 0x5, 14, 14, 0x1, /* T_CLKGATE_CTL.S2C_REQ_FIFO_CLK_GATE_EN */ \
+ 0x02, 0x5, 15, 15, 0x1, /* T_CLKGATE_CTL.C2APIC_FIFO_CLK_GATE_EN */ \
+ 0x02, 0x5, 16, 16, 0x1, /* T_CLKGATE_CTL.T2A_REQ_SEL_CLK_GATE_EN */ \
+ 0x02, 0x5, 17, 17, 0x1, /* T_CLKGATE_CTL.S2C_RESP_SEL_CLK_GATE_EN */ \
+ 0x02, 0x5, 18, 18, 0x1, /* T_CLKGATE_CTL.X2B_DATSEL_CLK_GATE_EN */ \
+ 0x02, 0x5, 19, 19, 0x1, /* T_CLKGATE_CTL.B2X_DATSEL_CLK_GATE_EN */ \
+ 0x02, 0x5, 20, 20, 0x1, /* T_CLKGATE_CTL.A2TAPIC_CLK_GATE_EN */ \
+ 0x02, 0x5, 21, 21, 0x1, /* T_CLKGATE_CTL.T2A_Q_CLK_GATE_EN */ \
+ 0x02, 0x5, 22, 22, 0x1, /* T_CLKGATE_CTL.A2T_Q_CLK_GATE_EN */ \
+ 0x02, 0x5, 23, 23, 0x1, /* T_CLKGATE_CTL.MON_LOG_CLK_GATE_EN */ \
+ 0x02, 0x5, 24, 24, 0x1, /* T_CLKGATE_CTL.XUNIT_1_CLK_GATE_EN */ \
+ 0x02, 0x5, 25, 25, 0x1, /* T_CLKGATE_CTL.XUNIT_2_CLK_GATE_EN */ \
+ 0x02, 0x5, 26, 26, 0x1, /* T_CLKGATE_CTL.XUNIT_3_CLK_GATE_EN */ \
+ 0x02, 0x5, 27, 27, 0x1, /* T_CLKGATE_CTL.XUNIT_4_CLK_GATE_EN */ \
+/* end of TUNIT_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // TUNIT_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/adf_bios_settings.h b/ChvRefCodePkg/Include/PnP/adf_bios_settings.h new file mode 100644 index 0000000000..db105c55ff --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/adf_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef ADF_BIOS_SETTINGS_HH
+#define ADF_BIOS_SETTINGS_HH
+
+#endif // ADF_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/ahb_dmac_ip_bios_settings.h b/ChvRefCodePkg/Include/PnP/ahb_dmac_ip_bios_settings.h new file mode 100644 index 0000000000..b4f14a9432 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/ahb_dmac_ip_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef AHB_DMAC_IP_BIOS_SETTINGS_HH
+#define AHB_DMAC_IP_BIOS_SETTINGS_HH
+
+#endif // AHB_DMAC_IP_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/apb_hsuart_ip_bios_settings.h b/ChvRefCodePkg/Include/PnP/apb_hsuart_ip_bios_settings.h new file mode 100644 index 0000000000..5b4f486f99 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/apb_hsuart_ip_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef APB_HSUART_IP_BIOS_SETTINGS_HH
+#define APB_HSUART_IP_BIOS_SETTINGS_HH
+
+#endif // APB_HSUART_IP_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/apb_i2c_ip_bios_settings.h b/ChvRefCodePkg/Include/PnP/apb_i2c_ip_bios_settings.h new file mode 100644 index 0000000000..705bb4b7b1 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/apb_i2c_ip_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef APB_I2C_IP_BIOS_SETTINGS_HH
+#define APB_I2C_IP_BIOS_SETTINGS_HH
+
+#endif // APB_I2C_IP_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/apb_pwm_ip_bios_settings.h b/ChvRefCodePkg/Include/PnP/apb_pwm_ip_bios_settings.h new file mode 100644 index 0000000000..67d9380b5f --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/apb_pwm_ip_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef APB_PWM_IP_BIOS_SETTINGS_HH
+#define APB_PWM_IP_BIOS_SETTINGS_HH
+
+#endif // APB_PWM_IP_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/apb_ssp_ip_bios_settings.h b/ChvRefCodePkg/Include/PnP/apb_ssp_ip_bios_settings.h new file mode 100644 index 0000000000..329e68285c --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/apb_ssp_ip_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef APB_SSP_IP_BIOS_SETTINGS_HH
+#define APB_SSP_IP_BIOS_SETTINGS_HH
+
+#endif // APB_SSP_IP_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/ccu_regs_map_bios_settings.h b/ChvRefCodePkg/Include/PnP/ccu_regs_map_bios_settings.h new file mode 100644 index 0000000000..da34f896a6 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/ccu_regs_map_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef CCU_REGS_MAP_BIOS_SETTINGS_HH
+#define CCU_REGS_MAP_BIOS_SETTINGS_HH
+
+#endif // CCU_REGS_MAP_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/display_controller_bios_settings.h b/ChvRefCodePkg/Include/PnP/display_controller_bios_settings.h new file mode 100644 index 0000000000..2bd5e0aa0c --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/display_controller_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef DISPLAY_CONTROLLER_BIOS_SETTINGS_HH
+#define DISPLAY_CONTROLLER_BIOS_SETTINGS_HH
+
+#endif // DISPLAY_CONTROLLER_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/dma_bios_settings.h b/ChvRefCodePkg/Include/PnP/dma_bios_settings.h new file mode 100644 index 0000000000..72987b395c --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/dma_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef DMA_BIOS_SETTINGS_HH
+#define DMA_BIOS_SETTINGS_HH
+
+#endif // DMA_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/dram_cntl_bios_settings.h b/ChvRefCodePkg/Include/PnP/dram_cntl_bios_settings.h new file mode 100644 index 0000000000..2184ef2466 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/dram_cntl_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef DRAM_CNTL_BIOS_SETTINGS_HH
+#define DRAM_CNTL_BIOS_SETTINGS_HH
+
+#endif // DRAM_CNTL_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/dreut_bios_settings.h b/ChvRefCodePkg/Include/PnP/dreut_bios_settings.h new file mode 100644 index 0000000000..2505bcacc7 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/dreut_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef DREUT_BIOS_SETTINGS_HH
+#define DREUT_BIOS_SETTINGS_HH
+
+#endif // DREUT_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/dreut_cadb_bios_settings.h b/ChvRefCodePkg/Include/PnP/dreut_cadb_bios_settings.h new file mode 100644 index 0000000000..f2692ca3d9 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/dreut_cadb_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef DREUT_CADB_BIOS_SETTINGS_HH
+#define DREUT_CADB_BIOS_SETTINGS_HH
+
+#endif // DREUT_CADB_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/drng_bios_settings.h b/ChvRefCodePkg/Include/PnP/drng_bios_settings.h new file mode 100644 index 0000000000..c551c815ba --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/drng_bios_settings.h @@ -0,0 +1,23 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef DRNG_BIOS_SETTINGS_HH
+#define DRNG_BIOS_SETTINGS_HH
+
+#define DRNG_VALUEFORPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x0f, 0x3, 17, 17, 0x1, /* CONFIG.DRBG_DISABLE_CLK_GATING */ \
+/* end of DRNG_VALUEFORPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // DRNG_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/gcfgdev2_bios_settings.h b/ChvRefCodePkg/Include/PnP/gcfgdev2_bios_settings.h new file mode 100644 index 0000000000..29ada0ea31 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/gcfgdev2_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef GCFGDEV2_BIOS_SETTINGS_HH
+#define GCFGDEV2_BIOS_SETTINGS_HH
+
+#endif // GCFGDEV2_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/gcfgdisp_bios_settings.h b/ChvRefCodePkg/Include/PnP/gcfgdisp_bios_settings.h new file mode 100644 index 0000000000..de8b0fa00a --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/gcfgdisp_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef GCFGDISP_BIOS_SETTINGS_HH
+#define GCFGDISP_BIOS_SETTINGS_HH
+
+#endif // GCFGDISP_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/gcfgio_bios_settings.h b/ChvRefCodePkg/Include/PnP/gcfgio_bios_settings.h new file mode 100644 index 0000000000..5f25932b76 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/gcfgio_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef GCFGIO_BIOS_SETTINGS_HH
+#define GCFGIO_BIOS_SETTINGS_HH
+
+#endif // GCFGIO_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/gcfgmmio_bios_settings.h b/ChvRefCodePkg/Include/PnP/gcfgmmio_bios_settings.h new file mode 100644 index 0000000000..bbc7e7f5ce --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/gcfgmmio_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef GCFGMMIO_BIOS_SETTINGS_HH
+#define GCFGMMIO_BIOS_SETTINGS_HH
+
+#endif // GCFGMMIO_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/gdtunit_bios_settings.h b/ChvRefCodePkg/Include/PnP/gdtunit_bios_settings.h new file mode 100644 index 0000000000..e5bd9f340f --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/gdtunit_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef GDTUNIT_BIOS_SETTINGS_HH
+#define GDTUNIT_BIOS_SETTINGS_HH
+
+#endif // GDTUNIT_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/gmbcunit_bios_settings.h b/ChvRefCodePkg/Include/PnP/gmbcunit_bios_settings.h new file mode 100644 index 0000000000..f5340271b8 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/gmbcunit_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef GMBCUNIT_BIOS_SETTINGS_HH
+#define GMBCUNIT_BIOS_SETTINGS_HH
+
+#endif // GMBCUNIT_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/gmm_mmio_bios_settings.h b/ChvRefCodePkg/Include/PnP/gmm_mmio_bios_settings.h new file mode 100644 index 0000000000..c907ac25f4 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/gmm_mmio_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef GMM_MMIO_BIOS_SETTINGS_HH
+#define GMM_MMIO_BIOS_SETTINGS_HH
+
+#endif // GMM_MMIO_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/gmm_pcicfg_bios_settings.h b/ChvRefCodePkg/Include/PnP/gmm_pcicfg_bios_settings.h new file mode 100644 index 0000000000..e9fef94ddc --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/gmm_pcicfg_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef GMM_PCICFG_BIOS_SETTINGS_HH
+#define GMM_PCICFG_BIOS_SETTINGS_HH
+
+#endif // GMM_PCICFG_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/gmm_sbpr_bios_settings.h b/ChvRefCodePkg/Include/PnP/gmm_sbpr_bios_settings.h new file mode 100644 index 0000000000..80264db55c --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/gmm_sbpr_bios_settings.h @@ -0,0 +1,28 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef GMM_SBPR_BIOS_SETTINGS_HH
+#define GMM_SBPR_BIOS_SETTINGS_HH
+
+#define GMM_SBPR_VALUEFORPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xb4, 0xb4, 3, 0, 0xf, /* GMMSLVCTL.MAXOTC */ \
+/* end of GMM_SBPR_VALUEFORPERF_VALUES_PLATFORM_DEFAULT */
+
+#define GMM_SBPR_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xb4, 0xb4, 3, 0, 0x0, /* GMMSLVCTL.MAXOTC */ \
+/* end of GMM_SBPR_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#endif // GMM_SBPR_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/gpmunit_bios_settings.h b/ChvRefCodePkg/Include/PnP/gpmunit_bios_settings.h new file mode 100644 index 0000000000..88b85cde9d --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/gpmunit_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef GPMUNIT_BIOS_SETTINGS_HH
+#define GPMUNIT_BIOS_SETTINGS_HH
+
+#endif // GPMUNIT_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/gunit_sb_top_bios_settings.h b/ChvRefCodePkg/Include/PnP/gunit_sb_top_bios_settings.h new file mode 100644 index 0000000000..4455cc7c7d --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/gunit_sb_top_bios_settings.h @@ -0,0 +1,33 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef GUNIT_SB_TOP_BIOS_SETTINGS_HH
+#define GUNIT_SB_TOP_BIOS_SETTINGS_HH
+
+#define GUNIT_SB_TOP_VALUEFORPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x06, 0x9424, 1, 1, 0x0, /* MISCCPCTL.L1UGTEN4RST */ \
+/* end of GUNIT_SB_TOP_VALUEFORPERF_VALUES_PLATFORM_DEFAULT */
+
+#define GUNIT_SB_TOP_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x06, 0x9424, 1, 1, 0x0, /* MISCCPCTL.L1UGTEN4RST */ \
+/* end of GUNIT_SB_TOP_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define GUNIT_SB_TOP_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x06, 0x9424, 1, 1, 0x0, /* MISCCPCTL.L1UGTEN4RST */ \
+/* end of GUNIT_SB_TOP_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // GUNIT_SB_TOP_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/gunit_sbp_top_bios_settings.h b/ChvRefCodePkg/Include/PnP/gunit_sbp_top_bios_settings.h new file mode 100644 index 0000000000..f6a24f60f6 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/gunit_sbp_top_bios_settings.h @@ -0,0 +1,33 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef GUNIT_SBP_TOP_BIOS_SETTINGS_HH
+#define GUNIT_SBP_TOP_BIOS_SETTINGS_HH
+
+#define GUNIT_SBP_TOP_VALUEFORPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x06, 0x9424, 1, 1, 0x0, /* MISCCPCTL.L1UGTEN4RST */ \
+/* end of GUNIT_SBP_TOP_VALUEFORPERF_VALUES_PLATFORM_DEFAULT */
+
+#define GUNIT_SBP_TOP_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x06, 0x9424, 1, 1, 0x0, /* MISCCPCTL.L1UGTEN4RST */ \
+/* end of GUNIT_SBP_TOP_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define GUNIT_SBP_TOP_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x06, 0x9424, 1, 1, 0x0, /* MISCCPCTL.L1UGTEN4RST */ \
+/* end of GUNIT_SBP_TOP_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // GUNIT_SBP_TOP_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/gwakeunit_cfg_bios_settings.h b/ChvRefCodePkg/Include/PnP/gwakeunit_cfg_bios_settings.h new file mode 100644 index 0000000000..dc7cd029ea --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/gwakeunit_cfg_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef GWAKEUNIT_CFG_BIOS_SETTINGS_HH
+#define GWAKEUNIT_CFG_BIOS_SETTINGS_HH
+
+#endif // GWAKEUNIT_CFG_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/gwakeunit_int_bios_settings.h b/ChvRefCodePkg/Include/PnP/gwakeunit_int_bios_settings.h new file mode 100644 index 0000000000..537970d18d --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/gwakeunit_int_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef GWAKEUNIT_INT_BIOS_SETTINGS_HH
+#define GWAKEUNIT_INT_BIOS_SETTINGS_HH
+
+#endif // GWAKEUNIT_INT_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/hda_regs_bios_settings.h b/ChvRefCodePkg/Include/PnP/hda_regs_bios_settings.h new file mode 100644 index 0000000000..b88d7be8e8 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/hda_regs_bios_settings.h @@ -0,0 +1,38 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef HDA_REGS_BIOS_SETTINGS_HH
+#define HDA_REGS_BIOS_SETTINGS_HH
+
+#define HDA_REGS_VALUEFORPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xa7, 0x43, 0, 0, 0x0, /* TM1.ODCGEN */ \
+ 0xa7, 0x43, 1, 1, 0x0, /* TM1.IDCGEN */ \
+ 0xa7, 0x43, 2, 2, 0x0, /* TM1.MDCGEN */ \
+ 0xa7, 0x43, 4, 4, 0x0, /* TM1.BCSS */ \
+ 0xa7, 0x43, 6, 6, 0x0, /* TM1.ACCD */ \
+ 0xa7, 0x120, 31, 31, 0x1, /* VCICTL.VCIEN */ \
+/* end of HDA_REGS_VALUEFORPERF_VALUES_PLATFORM_DEFAULT */
+
+#define HDA_REGS_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xa7, 0x78, 11, 11, 0x0, /* DEVC.NSNPEN */ \
+/* end of HDA_REGS_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define HDA_REGS_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xa7, 0x120, 31, 31, 0x1, /* VCICTL.VCIEN */ \
+/* end of HDA_REGS_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // HDA_REGS_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/iunit_bios_settings.h b/ChvRefCodePkg/Include/PnP/iunit_bios_settings.h new file mode 100644 index 0000000000..3fe6afc45d --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/iunit_bios_settings.h @@ -0,0 +1,34 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef IUNIT_BIOS_SETTINGS_HH
+#define IUNIT_BIOS_SETTINGS_HH
+
+#define IUNIT_VALUEFORPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x1c, 0x118, 6, 5, 0x2, /* IUNIT_CONTROL.ISPCLK_GATING_DISABLE */ \
+ 0x1c, 0x118, 15, 8, 0xff, /* IUNIT_CONTROL.MID */ \
+/* end of IUNIT_VALUEFORPERF_VALUES_PLATFORM_DEFAULT */
+
+#define IUNIT_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x1c, 0x118, 15, 8, 0x0, /* IUNIT_CONTROL.MID */ \
+/* end of IUNIT_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define IUNIT_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x1c, 0x118, 6, 5, 0x2, /* IUNIT_CONTROL.ISPCLK_GATING_DISABLE */ \
+/* end of IUNIT_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // IUNIT_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/lpeshim_bios_settings.h b/ChvRefCodePkg/Include/PnP/lpeshim_bios_settings.h new file mode 100644 index 0000000000..5499acb95f --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/lpeshim_bios_settings.h @@ -0,0 +1,37 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef LPESHIM_BIOS_SETTINGS_HH
+#define LPESHIM_BIOS_SETTINGS_HH
+
+#define LPESHIM_VALUEFORPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x58, 0x78, 3, 0, 0x7, /* CLKCTL.CLK_DIV */ \
+ 0x58, 0x80, 3, 0, 0x7, /* FR_LAT_REQ.REQUIRED_FREQ */ \
+/* end of LPESHIM_VALUEFORPERF_VALUES_PLATFORM_DEFAULT */
+
+#define LPESHIM_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x58, 0x78, 3, 0, 0x0, /* CLKCTL.CLK_DIV */ \
+ 0x58, 0x80, 6, 4, 0x7, /* FR_LAT_REQ.LATENCY_TOL */ \
+/* end of LPESHIM_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define LPESHIM_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x58, 0x78, 3, 0, 0x4, /* CLKCTL.CLK_DIV */ \
+ 0x58, 0x80, 3, 0, 0x4, /* FR_LAT_REQ.REQUIRED_FREQ */ \
+ 0x58, 0x80, 6, 4, 0x3, /* FR_LAT_REQ.LATENCY_TOL */ \
+/* end of LPESHIM_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // LPESHIM_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/map_IOSF2OCP_CONFIGREG_pci_bios_settings.h b/ChvRefCodePkg/Include/PnP/map_IOSF2OCP_CONFIGREG_pci_bios_settings.h new file mode 100644 index 0000000000..5fc9092475 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/map_IOSF2OCP_CONFIGREG_pci_bios_settings.h @@ -0,0 +1,23 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef MAP_IOSF2OCP_CONFIGREG_PCI_BIOS_SETTINGS_HH
+#define MAP_IOSF2OCP_CONFIGREG_PCI_BIOS_SETTINGS_HH
+
+#define MAP_IOSF2OCP_CONFIGREG_PCI_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x58, 0x84, 1, 0, 0x3, /* PMECTRLSTATUS.POWERSTATE */ \
+/* end of MAP_IOSF2OCP_CONFIGREG_PCI_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#endif // MAP_IOSF2OCP_CONFIGREG_PCI_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/map_IOSF2OCP_CONFIGREG_private_lpe_bios_settings.h b/ChvRefCodePkg/Include/PnP/map_IOSF2OCP_CONFIGREG_private_lpe_bios_settings.h new file mode 100644 index 0000000000..19a54d8291 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/map_IOSF2OCP_CONFIGREG_private_lpe_bios_settings.h @@ -0,0 +1,28 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef MAP_IOSF2OCP_CONFIGREG_PRIVATE_LPE_BIOS_SETTINGS_HH
+#define MAP_IOSF2OCP_CONFIGREG_PRIVATE_LPE_BIOS_SETTINGS_HH
+
+#define MAP_IOSF2OCP_CONFIGREG_PRIVATE_LPE_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x58, 0x68, 7, 4, 0x0, /* OCPCTL.CMDDEPTH */ \
+/* end of MAP_IOSF2OCP_CONFIGREG_PRIVATE_LPE_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define MAP_IOSF2OCP_CONFIGREG_PRIVATE_LPE_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x58, 0x10, 7, 4, 0xF, /* OCPCTL.CMDDEPTH */ \
+/* end of MAP_IOSF2OCP_CONFIGREG_PRIVATE_LPE_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // MAP_IOSF2OCP_CONFIGREG_PRIVATE_LPE_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/map_config_reg_1_0_ahb_private_bios_settings.h b/ChvRefCodePkg/Include/PnP/map_config_reg_1_0_ahb_private_bios_settings.h new file mode 100644 index 0000000000..91486138e3 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/map_config_reg_1_0_ahb_private_bios_settings.h @@ -0,0 +1,29 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef MAP_CONFIG_REG_1_0_AHB_PRIVATE_BIOS_SETTINGS_HH
+#define MAP_CONFIG_REG_1_0_AHB_PRIVATE_BIOS_SETTINGS_HH
+
+#define MAP_CONFIG_REG_1_0_AHB_PRIVATE_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xa0, 0x1f4, 0, 0, 0x1, /* GPIODF0.CR_CLOCK_ENABLE_BASE_CLK_BIT_1 */ \
+ 0xa0, 0x1f4, 1, 1, 0x1, /* GPIODF0.CR_CLOCK_ENABLE_AHB_CLK_BIT_1 */ \
+ 0xa0, 0x220, 0, 0, 0x1, /* PMCTL.IOSF_CLK_GATE_ENABLE */ \
+ 0xa0, 0x220, 1, 1, 0x1, /* PMCTL.AHB_CLK_GATE_EN */ \
+ 0xa0, 0x220, 2, 2, 0x1, /* PMCTL.SIDE_CLK_GATE_ENABLE */ \
+ 0xa0, 0x220, 3, 3, 0x1, /* PMCTL.IOSFPRIM_TRUNK_GATE_ENABLE */ \
+ 0xa0, 0x220, 4, 4, 0x1, /* PMCTL.AHB_TRUNK_GATE_ENABLE */ \
+/* end of MAP_CONFIG_REG_1_0_AHB_PRIVATE_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#endif // MAP_CONFIG_REG_1_0_AHB_PRIVATE_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/pcie0_cfg_pri_sb_pair_bios_settings.h b/ChvRefCodePkg/Include/PnP/pcie0_cfg_pri_sb_pair_bios_settings.h new file mode 100644 index 0000000000..c5c364b9f2 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/pcie0_cfg_pri_sb_pair_bios_settings.h @@ -0,0 +1,59 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PCIE0_CFG_PRI_SB_PAIR_BIOS_SETTINGS_HH
+#define PCIE0_CFG_PRI_SB_PAIR_BIOS_SETTINGS_HH
+
+#define PCIE0_CFG_PRI_SB_PAIR_VALUEFORPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xa4, 0xd4, 4, 4, 0x1, /* MPC2.ASPMCOEN */ \
+/* end of PCIE0_CFG_PRI_SB_PAIR_VALUEFORPERF_VALUES_PLATFORM_DEFAULT */
+
+#define PCIE0_CFG_PRI_SB_PAIR_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xa4, 0x50, 1, 0, 0x3, /* LCTL_LSTS.ASPM */ \
+ 0xa4, 0xd4, 3, 2, 0x3, /* MPC2.ASPMCO */ \
+ 0xa4, 0xe0, 8, 8, 0x1, /* RWC_RPDCGEN_RPPGEN.RPDBCGEN */ \
+ 0xa4, 0xe0, 9, 9, 0x1, /* RWC_RPDCGEN_RPPGEN.RPDLCGEN */ \
+ 0xa4, 0xe0, 10, 10, 0x1, /* RWC_RPDCGEN_RPPGEN.SRDBCGEN */ \
+ 0xa4, 0xe0, 11, 11, 0x1, /* RWC_RPDCGEN_RPPGEN.SRDLCGEN */ \
+ 0xa4, 0xe0, 13, 13, 0x1, /* RWC_RPDCGEN_RPPGEN.PCIELCLKREQEN */ \
+ 0xa4, 0xe0, 15, 15, 0x1, /* RWC_RPDCGEN_RPPGEN.RPSCGEN */ \
+ 0xa4, 0xe0, 16, 16, 0x1, /* RWC_RPDCGEN_RPPGEN.RPPGEN */ \
+ 0xa4, 0xe8, 0, 0, 0x1, /* PWRCTL.RPDTSQPOL */ \
+ 0xa4, 0xe8, 1, 1, 0x1, /* PWRCTL.RPL1SQPOL */ \
+ 0xa4, 0xf4, 8, 8, 0x1, /* PHYCTL_PHYCTL2_PHYCTL3_IOSFSBCS.PXPPLLOFFEN */ \
+ 0xa4, 0x208, 0, 0, 0x1, /* L1SCTL1.L1OE */ \
+ 0xa4, 0x208, 1, 1, 0x1, /* L1SCTL1.L1SE */ \
+/* end of PCIE0_CFG_PRI_SB_PAIR_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define PCIE0_CFG_PRI_SB_PAIR_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xa4, 0x50, 1, 0, 0x3, /* LCTL_LSTS.ASPM */ \
+ 0xa4, 0xd4, 3, 2, 0x3, /* MPC2.ASPMCO */ \
+ 0xa4, 0xe0, 8, 8, 0x1, /* RWC_RPDCGEN_RPPGEN.RPDBCGEN */ \
+ 0xa4, 0xe0, 9, 9, 0x1, /* RWC_RPDCGEN_RPPGEN.RPDLCGEN */ \
+ 0xa4, 0xe0, 10, 10, 0x1, /* RWC_RPDCGEN_RPPGEN.SRDBCGEN */ \
+ 0xa4, 0xe0, 11, 11, 0x1, /* RWC_RPDCGEN_RPPGEN.SRDLCGEN */ \
+ 0xa4, 0xe0, 13, 13, 0x1, /* RWC_RPDCGEN_RPPGEN.PCIELCLKREQEN */ \
+ 0xa4, 0xe0, 15, 15, 0x1, /* RWC_RPDCGEN_RPPGEN.RPSCGEN */ \
+ 0xa4, 0xe0, 16, 16, 0x1, /* RWC_RPDCGEN_RPPGEN.RPPGEN */ \
+ 0xa4, 0xe8, 0, 0, 0x1, /* PWRCTL.RPDTSQPOL */ \
+ 0xa4, 0xe8, 1, 1, 0x1, /* PWRCTL.RPL1SQPOL */ \
+ 0xa4, 0xf4, 8, 8, 0x1, /* PHYCTL_PHYCTL2_PHYCTL3_IOSFSBCS.PXPPLLOFFEN */ \
+ 0xa4, 0x208, 0, 0, 0x1, /* L1SCTL1.L1OE */ \
+ 0xa4, 0x208, 1, 1, 0x1, /* L1SCTL1.L1SE */ \
+/* end of PCIE0_CFG_PRI_SB_PAIR_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // PCIE0_CFG_PRI_SB_PAIR_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/pcie1_cfg_pri_sb_pair_bios_settings.h b/ChvRefCodePkg/Include/PnP/pcie1_cfg_pri_sb_pair_bios_settings.h new file mode 100644 index 0000000000..78b4b67a55 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/pcie1_cfg_pri_sb_pair_bios_settings.h @@ -0,0 +1,59 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PCIE1_CFG_PRI_SB_PAIR_BIOS_SETTINGS_HH
+#define PCIE1_CFG_PRI_SB_PAIR_BIOS_SETTINGS_HH
+
+#define PCIE1_CFG_PRI_SB_PAIR_VALUEFORPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xa4, 0xd4, 4, 4, 0x1, /* MPC2.ASPMCOEN */ \
+/* end of PCIE1_CFG_PRI_SB_PAIR_VALUEFORPERF_VALUES_PLATFORM_DEFAULT */
+
+#define PCIE1_CFG_PRI_SB_PAIR_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xa4, 0x50, 1, 0, 0x3, /* LCTL_LSTS.ASPM */ \
+ 0xa4, 0xd4, 3, 2, 0x3, /* MPC2.ASPMCO */ \
+ 0xa4, 0xe0, 8, 8, 0x1, /* RWC_RPDCGEN_RPPGEN.RPDBCGEN */ \
+ 0xa4, 0xe0, 9, 9, 0x1, /* RWC_RPDCGEN_RPPGEN.RPDLCGEN */ \
+ 0xa4, 0xe0, 10, 10, 0x1, /* RWC_RPDCGEN_RPPGEN.SRDBCGEN */ \
+ 0xa4, 0xe0, 11, 11, 0x1, /* RWC_RPDCGEN_RPPGEN.SRDLCGEN */ \
+ 0xa4, 0xe0, 13, 13, 0x1, /* RWC_RPDCGEN_RPPGEN.PCIELCLKREQEN */ \
+ 0xa4, 0xe0, 15, 15, 0x1, /* RWC_RPDCGEN_RPPGEN.RPSCGEN */ \
+ 0xa4, 0xe0, 16, 16, 0x1, /* RWC_RPDCGEN_RPPGEN.RPPGEN */ \
+ 0xa4, 0xe8, 0, 0, 0x1, /* PWRCTL.RPDTSQPOL */ \
+ 0xa4, 0xe8, 1, 1, 0x1, /* PWRCTL.RPL1SQPOL */ \
+ 0xa4, 0xf4, 8, 8, 0x1, /* PHYCTL_PHYCTL2_PHYCTL3_IOSFSBCS.PXPPLLOFFEN */ \
+ 0xa4, 0x208, 0, 0, 0x1, /* L1SCTL1.L1OE */ \
+ 0xa4, 0x208, 1, 1, 0x1, /* L1SCTL1.L1SE */ \
+/* end of PCIE1_CFG_PRI_SB_PAIR_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define PCIE1_CFG_PRI_SB_PAIR_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xa4, 0x50, 1, 0, 0x3, /* LCTL_LSTS.ASPM */ \
+ 0xa4, 0xd4, 3, 2, 0x3, /* MPC2.ASPMCO */ \
+ 0xa4, 0xe0, 8, 8, 0x1, /* RWC_RPDCGEN_RPPGEN.RPDBCGEN */ \
+ 0xa4, 0xe0, 9, 9, 0x1, /* RWC_RPDCGEN_RPPGEN.RPDLCGEN */ \
+ 0xa4, 0xe0, 10, 10, 0x1, /* RWC_RPDCGEN_RPPGEN.SRDBCGEN */ \
+ 0xa4, 0xe0, 11, 11, 0x1, /* RWC_RPDCGEN_RPPGEN.SRDLCGEN */ \
+ 0xa4, 0xe0, 13, 13, 0x1, /* RWC_RPDCGEN_RPPGEN.PCIELCLKREQEN */ \
+ 0xa4, 0xe0, 15, 15, 0x1, /* RWC_RPDCGEN_RPPGEN.RPSCGEN */ \
+ 0xa4, 0xe0, 16, 16, 0x1, /* RWC_RPDCGEN_RPPGEN.RPPGEN */ \
+ 0xa4, 0xe8, 0, 0, 0x1, /* PWRCTL.RPDTSQPOL */ \
+ 0xa4, 0xe8, 1, 1, 0x1, /* PWRCTL.RPL1SQPOL */ \
+ 0xa4, 0xf4, 8, 8, 0x1, /* PHYCTL_PHYCTL2_PHYCTL3_IOSFSBCS.PXPPLLOFFEN */ \
+ 0xa4, 0x208, 0, 0, 0x1, /* L1SCTL1.L1OE */ \
+ 0xa4, 0x208, 1, 1, 0x1, /* L1SCTL1.L1SE */ \
+/* end of PCIE1_CFG_PRI_SB_PAIR_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // PCIE1_CFG_PRI_SB_PAIR_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/pcie2_cfg_pri_sb_pair_bios_settings.h b/ChvRefCodePkg/Include/PnP/pcie2_cfg_pri_sb_pair_bios_settings.h new file mode 100644 index 0000000000..a26f650470 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/pcie2_cfg_pri_sb_pair_bios_settings.h @@ -0,0 +1,59 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PCIE2_CFG_PRI_SB_PAIR_BIOS_SETTINGS_HH
+#define PCIE2_CFG_PRI_SB_PAIR_BIOS_SETTINGS_HH
+
+#define PCIE2_CFG_PRI_SB_PAIR_VALUEFORPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xa4, 0xd4, 4, 4, 0x1, /* MPC2.ASPMCOEN */ \
+/* end of PCIE2_CFG_PRI_SB_PAIR_VALUEFORPERF_VALUES_PLATFORM_DEFAULT */
+
+#define PCIE2_CFG_PRI_SB_PAIR_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xa4, 0x50, 1, 0, 0x3, /* LCTL_LSTS.ASPM */ \
+ 0xa4, 0xd4, 3, 2, 0x3, /* MPC2.ASPMCO */ \
+ 0xa4, 0xe0, 8, 8, 0x1, /* RWC_RPDCGEN_RPPGEN.RPDBCGEN */ \
+ 0xa4, 0xe0, 9, 9, 0x1, /* RWC_RPDCGEN_RPPGEN.RPDLCGEN */ \
+ 0xa4, 0xe0, 10, 10, 0x1, /* RWC_RPDCGEN_RPPGEN.SRDBCGEN */ \
+ 0xa4, 0xe0, 11, 11, 0x1, /* RWC_RPDCGEN_RPPGEN.SRDLCGEN */ \
+ 0xa4, 0xe0, 13, 13, 0x1, /* RWC_RPDCGEN_RPPGEN.PCIELCLKREQEN */ \
+ 0xa4, 0xe0, 15, 15, 0x1, /* RWC_RPDCGEN_RPPGEN.RPSCGEN */ \
+ 0xa4, 0xe0, 16, 16, 0x1, /* RWC_RPDCGEN_RPPGEN.RPPGEN */ \
+ 0xa4, 0xe8, 0, 0, 0x1, /* PWRCTL.RPDTSQPOL */ \
+ 0xa4, 0xe8, 1, 1, 0x1, /* PWRCTL.RPL1SQPOL */ \
+ 0xa4, 0xf4, 8, 8, 0x1, /* PHYCTL_PHYCTL2_PHYCTL3_IOSFSBCS.PXPPLLOFFEN */ \
+ 0xa4, 0x208, 0, 0, 0x1, /* L1SCTL1.L1OE */ \
+ 0xa4, 0x208, 1, 1, 0x1, /* L1SCTL1.L1SE */ \
+/* end of PCIE2_CFG_PRI_SB_PAIR_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define PCIE2_CFG_PRI_SB_PAIR_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xa4, 0x50, 1, 0, 0x3, /* LCTL_LSTS.ASPM */ \
+ 0xa4, 0xd4, 3, 2, 0x3, /* MPC2.ASPMCO */ \
+ 0xa4, 0xe0, 8, 8, 0x1, /* RWC_RPDCGEN_RPPGEN.RPDBCGEN */ \
+ 0xa4, 0xe0, 9, 9, 0x1, /* RWC_RPDCGEN_RPPGEN.RPDLCGEN */ \
+ 0xa4, 0xe0, 10, 10, 0x1, /* RWC_RPDCGEN_RPPGEN.SRDBCGEN */ \
+ 0xa4, 0xe0, 11, 11, 0x1, /* RWC_RPDCGEN_RPPGEN.SRDLCGEN */ \
+ 0xa4, 0xe0, 13, 13, 0x1, /* RWC_RPDCGEN_RPPGEN.PCIELCLKREQEN */ \
+ 0xa4, 0xe0, 15, 15, 0x1, /* RWC_RPDCGEN_RPPGEN.RPSCGEN */ \
+ 0xa4, 0xe0, 16, 16, 0x1, /* RWC_RPDCGEN_RPPGEN.RPPGEN */ \
+ 0xa4, 0xe8, 0, 0, 0x1, /* PWRCTL.RPDTSQPOL */ \
+ 0xa4, 0xe8, 1, 1, 0x1, /* PWRCTL.RPL1SQPOL */ \
+ 0xa4, 0xf4, 8, 8, 0x1, /* PHYCTL_PHYCTL2_PHYCTL3_IOSFSBCS.PXPPLLOFFEN */ \
+ 0xa4, 0x208, 0, 0, 0x1, /* L1SCTL1.L1OE */ \
+ 0xa4, 0x208, 1, 1, 0x1, /* L1SCTL1.L1SE */ \
+/* end of PCIE2_CFG_PRI_SB_PAIR_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // PCIE2_CFG_PRI_SB_PAIR_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/pcie3_cfg_pri_sb_pair_bios_settings.h b/ChvRefCodePkg/Include/PnP/pcie3_cfg_pri_sb_pair_bios_settings.h new file mode 100644 index 0000000000..817be4ee05 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/pcie3_cfg_pri_sb_pair_bios_settings.h @@ -0,0 +1,59 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PCIE3_CFG_PRI_SB_PAIR_BIOS_SETTINGS_HH
+#define PCIE3_CFG_PRI_SB_PAIR_BIOS_SETTINGS_HH
+
+#define PCIE3_CFG_PRI_SB_PAIR_VALUEFORPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xa4, 0xd4, 4, 4, 0x1, /* MPC2.ASPMCOEN */ \
+/* end of PCIE3_CFG_PRI_SB_PAIR_VALUEFORPERF_VALUES_PLATFORM_DEFAULT */
+
+#define PCIE3_CFG_PRI_SB_PAIR_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xa4, 0x50, 1, 0, 0x3, /* LCTL_LSTS.ASPM */ \
+ 0xa4, 0xd4, 3, 2, 0x3, /* MPC2.ASPMCO */ \
+ 0xa4, 0xe0, 8, 8, 0x1, /* RWC_RPDCGEN_RPPGEN.RPDBCGEN */ \
+ 0xa4, 0xe0, 9, 9, 0x1, /* RWC_RPDCGEN_RPPGEN.RPDLCGEN */ \
+ 0xa4, 0xe0, 10, 10, 0x1, /* RWC_RPDCGEN_RPPGEN.SRDBCGEN */ \
+ 0xa4, 0xe0, 11, 11, 0x1, /* RWC_RPDCGEN_RPPGEN.SRDLCGEN */ \
+ 0xa4, 0xe0, 13, 13, 0x1, /* RWC_RPDCGEN_RPPGEN.PCIELCLKREQEN */ \
+ 0xa4, 0xe0, 15, 15, 0x1, /* RWC_RPDCGEN_RPPGEN.RPSCGEN */ \
+ 0xa4, 0xe0, 16, 16, 0x1, /* RWC_RPDCGEN_RPPGEN.RPPGEN */ \
+ 0xa4, 0xe8, 0, 0, 0x1, /* PWRCTL.RPDTSQPOL */ \
+ 0xa4, 0xe8, 1, 1, 0x1, /* PWRCTL.RPL1SQPOL */ \
+ 0xa4, 0xf4, 8, 8, 0x1, /* PHYCTL_PHYCTL2_PHYCTL3_IOSFSBCS.PXPPLLOFFEN */ \
+ 0xa4, 0x208, 0, 0, 0x1, /* L1SCTL1.L1OE */ \
+ 0xa4, 0x208, 1, 1, 0x1, /* L1SCTL1.L1SE */ \
+/* end of PCIE3_CFG_PRI_SB_PAIR_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define PCIE3_CFG_PRI_SB_PAIR_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xa4, 0x50, 1, 0, 0x3, /* LCTL_LSTS.ASPM */ \
+ 0xa4, 0xd4, 3, 2, 0x3, /* MPC2.ASPMCO */ \
+ 0xa4, 0xe0, 8, 8, 0x1, /* RWC_RPDCGEN_RPPGEN.RPDBCGEN */ \
+ 0xa4, 0xe0, 9, 9, 0x1, /* RWC_RPDCGEN_RPPGEN.RPDLCGEN */ \
+ 0xa4, 0xe0, 10, 10, 0x1, /* RWC_RPDCGEN_RPPGEN.SRDBCGEN */ \
+ 0xa4, 0xe0, 11, 11, 0x1, /* RWC_RPDCGEN_RPPGEN.SRDLCGEN */ \
+ 0xa4, 0xe0, 13, 13, 0x1, /* RWC_RPDCGEN_RPPGEN.PCIELCLKREQEN */ \
+ 0xa4, 0xe0, 15, 15, 0x1, /* RWC_RPDCGEN_RPPGEN.RPSCGEN */ \
+ 0xa4, 0xe0, 16, 16, 0x1, /* RWC_RPDCGEN_RPPGEN.RPPGEN */ \
+ 0xa4, 0xe8, 0, 0, 0x1, /* PWRCTL.RPDTSQPOL */ \
+ 0xa4, 0xe8, 1, 1, 0x1, /* PWRCTL.RPL1SQPOL */ \
+ 0xa4, 0xf4, 8, 8, 0x1, /* PHYCTL_PHYCTL2_PHYCTL3_IOSFSBCS.PXPPLLOFFEN */ \
+ 0xa4, 0x208, 0, 0, 0x1, /* L1SCTL1.L1OE */ \
+ 0xa4, 0x208, 1, 1, 0x1, /* L1SCTL1.L1SE */ \
+/* end of PCIE3_CFG_PRI_SB_PAIR_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // PCIE3_CFG_PRI_SB_PAIR_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/pcie_prvt_cfg_bios_settings.h b/ChvRefCodePkg/Include/PnP/pcie_prvt_cfg_bios_settings.h new file mode 100644 index 0000000000..67fd5af47c --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/pcie_prvt_cfg_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PCIE_PRVT_CFG_BIOS_SETTINGS_HH
+#define PCIE_PRVT_CFG_BIOS_SETTINGS_HH
+
+#endif // PCIE_PRVT_CFG_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/pcu_b0_d31_f0_bios_settings.h b/ChvRefCodePkg/Include/PnP/pcu_b0_d31_f0_bios_settings.h new file mode 100644 index 0000000000..6ef09f6508 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/pcu_b0_d31_f0_bios_settings.h @@ -0,0 +1,56 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PCU_B0_D31_F0_BIOS_SETTINGS_HH
+#define PCU_B0_D31_F0_BIOS_SETTINGS_HH
+
+#define PCU_B0_D31_F0_VALUEFORPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x54, 0x8c, 8, 8, 0x0, /* CGC.CGE */ \
+ 0x54, 0x8c, 9, 9, 0x0, /* CGC.CGD */ \
+ 0x54, 0x90, 26, 24, 0x4, /* SOFTWARE_SEQUENCING_FLASH_CONTROL_STATUS_BIOS.SCF */ \
+ 0x54, 0xfc, 3, 2, 0x2, /* BIOS_CONTROL_REGISTER_BIOS.SRC */ \
+ 0x54, 0x100, 9, 9, 0x1, /* TRUNK_CLOCK_GATING_CONTROL_BIOS.SBCGCDEF */ \
+ 0x54, 0x100, 11, 11, 0x1, /* TRUNK_CLOCK_GATING_CONTROL_BIOS.FCREPDIS */ \
+ 0x54, 0x10e1, 26, 24, 0x4, /* SOFTWARE_SEQUENCING_FLASH_CONTROL_STATUS_SEC.SCF */ \
+ 0x54, 0xe1, 26, 24, 0x4, /* SOFTWARE_SEQUENCING_FLASH_CONTROL_STATUS_GBE.SCF */ \
+/* end of PCU_B0_D31_F0_VALUEFORPERF_VALUES_PLATFORM_DEFAULT */
+
+#define PCU_B0_D31_F0_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x54, 0x1c, 8, 8, 0x0, /* BC.PFE */ \
+ 0x54, 0x84, 2, 2, 0x1, /* LPCC.CLKRUN_EN */ \
+ 0x54, 0x8c, 9, 9, 0x0, /* CGC.CGD */ \
+ 0x54, 0xc0, 0, 0, 0x1, /* ADDITIONAL_FLASH_CONTROL_BIOS.FCDCGE */ \
+ 0x54, 0xc0, 1, 1, 0x1, /* ADDITIONAL_FLASH_CONTROL_BIOS.FMDCGE */ \
+ 0x54, 0xc0, 2, 2, 0x1, /* ADDITIONAL_FLASH_CONTROL_BIOS.FSDCGE */ \
+ 0x54, 0x100, 10, 10, 0x0, /* TRUNK_CLOCK_GATING_CONTROL_BIOS.FCGDIS */ \
+ 0x54, 0x114d, 1, 1, 0x0, /* SEC_FLASH_CONTROL_SEC.SECDRPE */ \
+/* end of PCU_B0_D31_F0_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define PCU_B0_D31_F0_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x54, 0x1c, 8, 8, 0x0, /* BC.PFE */ \
+ 0x54, 0x8c, 8, 8, 0x0, /* CGC.CGE */ \
+ 0x54, 0x8c, 9, 9, 0x0, /* CGC.CGD */ \
+ 0x54, 0x90, 26, 24, 0x4, /* SOFTWARE_SEQUENCING_FLASH_CONTROL_STATUS_BIOS.SCF */ \
+ 0x54, 0xc0, 0, 0, 0x1, /* ADDITIONAL_FLASH_CONTROL_BIOS.FCDCGE */ \
+ 0x54, 0xc0, 1, 1, 0x1, /* ADDITIONAL_FLASH_CONTROL_BIOS.FMDCGE */ \
+ 0x54, 0xc0, 2, 2, 0x1, /* ADDITIONAL_FLASH_CONTROL_BIOS.FSDCGE */ \
+ 0x54, 0x100, 10, 10, 0x0, /* TRUNK_CLOCK_GATING_CONTROL_BIOS.FCGDIS */ \
+ 0x54, 0x10e1, 26, 24, 0x4, /* SOFTWARE_SEQUENCING_FLASH_CONTROL_STATUS_SEC.SCF */ \
+ 0x54, 0xe1, 26, 24, 0x4, /* SOFTWARE_SEQUENCING_FLASH_CONTROL_STATUS_GBE.SCF */ \
+/* end of PCU_B0_D31_F0_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // PCU_B0_D31_F0_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/pcu_b0_d31_f3_bios_settings.h b/ChvRefCodePkg/Include/PnP/pcu_b0_d31_f3_bios_settings.h new file mode 100644 index 0000000000..a71f94164c --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/pcu_b0_d31_f3_bios_settings.h @@ -0,0 +1,40 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PCU_B0_D31_F3_BIOS_SETTINGS_HH
+#define PCU_B0_D31_F3_BIOS_SETTINGS_HH
+
+#define PCU_B0_D31_F3_VALUEFORPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x54, 0x80, 8, 8, 0x1, /* SMB_CONFIG_SMBSM.PHDCGDIS */ \
+ 0x54, 0x80, 10, 10, 0x1, /* SMB_CONFIG_SMBSM.LNDCGDIS */ \
+ 0x54, 0x80, 12, 12, 0x1, /* SMB_CONFIG_SMBSM.TRDCGDIS */ \
+ 0x54, 0x80, 14, 14, 0x1, /* SMB_CONFIG_SMBSM.BBDCGDIS */ \
+ 0x54, 0xfc, 16, 16, 0x1, /* SMB_CONFIG_CGC.TR_CLK_FORCE_REQ */ \
+/* end of PCU_B0_D31_F3_VALUEFORPERF_VALUES_PLATFORM_DEFAULT */
+
+#define PCU_B0_D31_F3_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x54, 0x54, 1, 0, 0x3, /* SMB_CONFIG_PMCSR.PS */ \
+ 0x54, 0xfc, 9, 9, 0x0, /* SMB_CONFIG_CGC.SB_LOCAL_CGD */ \
+ 0x54, 0xfc, 17, 17, 0x0, /* SMB_CONFIG_CGC.FUNC_CLK_CGD */ \
+/* end of PCU_B0_D31_F3_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define PCU_B0_D31_F3_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x54, 0xfc, 9, 9, 0x0, /* SMB_CONFIG_CGC.SB_LOCAL_CGD */ \
+ 0x54, 0xfc, 17, 17, 0x0, /* SMB_CONFIG_CGC.FUNC_CLK_CGD */ \
+/* end of PCU_B0_D31_F3_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // PCU_B0_D31_F3_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/psf0_bios_settings.h b/ChvRefCodePkg/Include/PnP/psf0_bios_settings.h new file mode 100644 index 0000000000..24a7f22cb1 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/psf0_bios_settings.h @@ -0,0 +1,30 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PSF0_BIOS_SETTINGS_HH
+#define PSF0_BIOS_SETTINGS_HH
+
+#define PSF0_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x45, 0xc000, 0, 0, 0x0, /* POWER_OPTIONS.CLKGATE_DISABLE */ \
+ 0x45, 0xc000, 1, 1, 0x1, /* POWER_OPTIONS.DISABLE_NP_TRACK */ \
+/* end of PSF0_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define PSF0_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x45, 0xc000, 0, 0, 0x0, /* POWER_OPTIONS.CLKGATE_DISABLE */ \
+ 0x45, 0xc000, 1, 1, 0x1, /* POWER_OPTIONS.DISABLE_NP_TRACK */ \
+/* end of PSF0_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // PSF0_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/psf1_bios_settings.h b/ChvRefCodePkg/Include/PnP/psf1_bios_settings.h new file mode 100644 index 0000000000..23ff3d70c4 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/psf1_bios_settings.h @@ -0,0 +1,30 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PSF1_BIOS_SETTINGS_HH
+#define PSF1_BIOS_SETTINGS_HH
+
+#define PSF1_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x46, 0xc000, 0, 0, 0x0, /* POWER_OPTIONS.CLKGATE_DISABLE */ \
+ 0x46, 0xc000, 1, 1, 0x1, /* POWER_OPTIONS.DISABLE_NP_TRACK */ \
+/* end of PSF1_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define PSF1_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x46, 0xc000, 0, 0, 0x0, /* POWER_OPTIONS.CLKGATE_DISABLE */ \
+ 0x46, 0xc000, 1, 1, 0x1, /* POWER_OPTIONS.DISABLE_NP_TRACK */ \
+/* end of PSF1_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // PSF1_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/psf2_bios_settings.h b/ChvRefCodePkg/Include/PnP/psf2_bios_settings.h new file mode 100644 index 0000000000..d332b13ba5 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/psf2_bios_settings.h @@ -0,0 +1,30 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PSF2_BIOS_SETTINGS_HH
+#define PSF2_BIOS_SETTINGS_HH
+
+#define PSF2_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x47, 0xc000, 0, 0, 0x0, /* POWER_OPTIONS.CLKGATE_DISABLE */ \
+ 0x47, 0xc000, 1, 1, 0x1, /* POWER_OPTIONS.DISABLE_NP_TRACK */ \
+/* end of PSF2_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define PSF2_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x47, 0xc000, 0, 0, 0x0, /* POWER_OPTIONS.CLKGATE_DISABLE */ \
+ 0x47, 0xc000, 1, 1, 0x1, /* POWER_OPTIONS.DISABLE_NP_TRACK */ \
+/* end of PSF2_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // PSF2_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/psf3_bios_settings.h b/ChvRefCodePkg/Include/PnP/psf3_bios_settings.h new file mode 100644 index 0000000000..f3a0596385 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/psf3_bios_settings.h @@ -0,0 +1,30 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PSF3_BIOS_SETTINGS_HH
+#define PSF3_BIOS_SETTINGS_HH
+
+#define PSF3_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xb5, 0xc000, 0, 0, 0x0, /* POWER_OPTIONS.CLKGATE_DISABLE */ \
+ 0xb5, 0xc000, 1, 1, 0x1, /* POWER_OPTIONS.DISABLE_NP_TRACK */ \
+/* end of PSF3_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define PSF3_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xb5, 0xc000, 0, 0, 0x0, /* POWER_OPTIONS.CLKGATE_DISABLE */ \
+ 0xb5, 0xc000, 1, 1, 0x1, /* POWER_OPTIONS.DISABLE_NP_TRACK */ \
+/* end of PSF3_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // PSF3_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/psf_sata_bios_settings.h b/ChvRefCodePkg/Include/PnP/psf_sata_bios_settings.h new file mode 100644 index 0000000000..3df86f9bb6 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/psf_sata_bios_settings.h @@ -0,0 +1,30 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PSF_SATA_BIOS_SETTINGS_HH
+#define PSF_SATA_BIOS_SETTINGS_HH
+
+#define PSF_SATA_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xa2, 0xc000, 0, 0, 0x0, /* POWER_OPTIONS.CLKGATE_DISABLE */ \
+ 0xa2, 0xc000, 1, 1, 0x1, /* POWER_OPTIONS.DISABLE_NP_TRACK */ \
+/* end of PSF_SATA_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define PSF_SATA_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0xa2, 0xc000, 0, 0, 0x0, /* POWER_OPTIONS.CLKGATE_DISABLE */ \
+ 0xa2, 0xc000, 1, 1, 0x1, /* POWER_OPTIONS.DISABLE_NP_TRACK */ \
+/* end of PSF_SATA_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // PSF_SATA_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/scc_map_IOSF2OCP_CONFIGREG_private_bios_settings.h b/ChvRefCodePkg/Include/PnP/scc_map_IOSF2OCP_CONFIGREG_private_bios_settings.h new file mode 100644 index 0000000000..c8522a4259 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/scc_map_IOSF2OCP_CONFIGREG_private_bios_settings.h @@ -0,0 +1,42 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef SCC_MAP_IOSF2OCP_CONFIGREG_PRIVATE_BIOS_SETTINGS_HH
+#define SCC_MAP_IOSF2OCP_CONFIGREG_PRIVATE_BIOS_SETTINGS_HH
+
+#define SCC_MAP_IOSF2OCP_CONFIGREG_PRIVATE_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x63, 0x243, 0, 0, 0x1, /* PMCTL.IOSFPRIMCLK_GATE_EN */ \
+ 0x63, 0x243, 1, 1, 0x1, /* PMCTL.OCPCLK_GATE_EN */ \
+ 0x63, 0x243, 2, 2, 0x1, /* PMCTL.OCPCLK_TRUNK_GATE_EN */ \
+ 0x63, 0x243, 3, 3, 0x1, /* PMCTL.IOSFSBCLK_GATE_EN */ \
+ 0x63, 0x243, 4, 4, 0x1, /* PMCTL.IOSFPRIM_TRUNK_GATE_EN */ \
+ 0x63, 0x243, 5, 5, 0x1, /* PMCTL.IOSFSB_TRUNK_GATE_EN */ \
+ 0x63, 0x663, 1, 0, 0x1, /* GEN_REGRW1.CR_CLOCK_ENABLE_CLK_XIN */ \
+ 0x63, 0x663, 3, 2, 0x1, /* GEN_REGRW1.CR_CLOCK_ENABLE_CLK_OCP */ \
+/* end of SCC_MAP_IOSF2OCP_CONFIGREG_PRIVATE_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define SCC_MAP_IOSF2OCP_CONFIGREG_PRIVATE_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x63, 0x1e0, 0, 0, 0x1, /* PMCTL.IOSFPRIMCLK_GATE_EN */ \
+ 0x63, 0x1e0, 1, 1, 0x1, /* PMCTL.OCPCLK_GATE_EN */ \
+ 0x63, 0x1e0, 2, 2, 0x1, /* PMCTL.OCPCLK_TRUNK_GATE_EN */ \
+ 0x63, 0x1e0, 3, 3, 0x1, /* PMCTL.IOSFSBCLK_GATE_EN */ \
+ 0x63, 0x1e0, 4, 4, 0x1, /* PMCTL.IOSFPRIM_TRUNK_GATE_EN */ \
+ 0x63, 0x1e0, 5, 5, 0x1, /* PMCTL.IOSFSB_TRUNK_GATE_EN */ \
+ 0x63, 0x600, 1, 0, 0x1, /* GEN_REGRW1.CR_CLOCK_ENABLE_CLK_XIN */ \
+ 0x63, 0x600, 3, 2, 0x1, /* GEN_REGRW1.CR_CLOCK_ENABLE_CLK_OCP */ \
+/* end of SCC_MAP_IOSF2OCP_CONFIGREG_PRIVATE_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // SCC_MAP_IOSF2OCP_CONFIGREG_PRIVATE_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/sdio_bios_settings.h b/ChvRefCodePkg/Include/PnP/sdio_bios_settings.h new file mode 100644 index 0000000000..a515569be7 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/sdio_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef SDIO_BIOS_SETTINGS_HH
+#define SDIO_BIOS_SETTINGS_HH
+
+#endif // SDIO_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/sec_bios_settings.h b/ChvRefCodePkg/Include/PnP/sec_bios_settings.h new file mode 100644 index 0000000000..039a9d19c2 --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/sec_bios_settings.h @@ -0,0 +1,54 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef SEC_BIOS_SETTINGS_HH
+#define SEC_BIOS_SETTINGS_HH
+
+#define SEC_VALUEFORPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x44, 0x88, 0, 0, 0x0, /* CLK_GATE_DIS.SB_CG_DIS */ \
+ 0x44, 0x88, 1, 1, 0x0, /* CLK_GATE_DIS.PRIM_CG_DIS */ \
+ 0x44, 0x88, 2, 2, 0x0, /* CLK_GATE_DIS.PRIM_CLKREQ_DIS */ \
+ 0x44, 0x88, 3, 3, 0x0, /* CLK_GATE_DIS.PRIM_XSM_CLKREQ_DIS */ \
+ 0x44, 0x88, 4, 4, 0x0, /* CLK_GATE_DIS.SAP_CG_DIS */ \
+ 0x44, 0x88, 5, 5, 0x0, /* CLK_GATE_DIS.SAP_IP_CG_DIS */ \
+ 0x44, 0x88, 6, 6, 0x0, /* CLK_GATE_DIS.SAP_CLKIDLE_DIS */ \
+ 0x44, 0x88, 7, 7, 0x0, /* CLK_GATE_DIS.NFC_CG_DIS */ \
+/* end of SEC_VALUEFORPERF_VALUES_PLATFORM_DEFAULT */
+
+#define SEC_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x44, 0x88, 0, 0, 0x0, /* CLK_GATE_DIS.SB_CG_DIS */ \
+ 0x44, 0x88, 1, 1, 0x0, /* CLK_GATE_DIS.PRIM_CG_DIS */ \
+ 0x44, 0x88, 2, 2, 0x0, /* CLK_GATE_DIS.PRIM_CLKREQ_DIS */ \
+ 0x44, 0x88, 3, 3, 0x0, /* CLK_GATE_DIS.PRIM_XSM_CLKREQ_DIS */ \
+ 0x44, 0x88, 4, 4, 0x0, /* CLK_GATE_DIS.SAP_CG_DIS */ \
+ 0x44, 0x88, 5, 5, 0x0, /* CLK_GATE_DIS.SAP_IP_CG_DIS */ \
+ 0x44, 0x88, 6, 6, 0x0, /* CLK_GATE_DIS.SAP_CLKIDLE_DIS */ \
+ 0x44, 0x88, 7, 7, 0x0, /* CLK_GATE_DIS.NFC_CG_DIS */ \
+/* end of SEC_VALUEFORPOWER_VALUES_PLATFORM_DEFAULT */
+
+#define SEC_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT \
+/* MsgPort, MsgRegAddr, MSB, LSB, Value */ \
+ 0x44, 0x88, 0, 0, 0x0, /* CLK_GATE_DIS.SB_CG_DIS */ \
+ 0x44, 0x88, 1, 1, 0x0, /* CLK_GATE_DIS.PRIM_CG_DIS */ \
+ 0x44, 0x88, 2, 2, 0x0, /* CLK_GATE_DIS.PRIM_CLKREQ_DIS */ \
+ 0x44, 0x88, 3, 3, 0x0, /* CLK_GATE_DIS.PRIM_XSM_CLKREQ_DIS */ \
+ 0x44, 0x88, 4, 4, 0x0, /* CLK_GATE_DIS.SAP_CG_DIS */ \
+ 0x44, 0x88, 5, 5, 0x0, /* CLK_GATE_DIS.SAP_IP_CG_DIS */ \
+ 0x44, 0x88, 6, 6, 0x0, /* CLK_GATE_DIS.SAP_CLKIDLE_DIS */ \
+ 0x44, 0x88, 7, 7, 0x0, /* CLK_GATE_DIS.NFC_CG_DIS */ \
+/* end of SEC_VALUEFORPWRPERF_VALUES_PLATFORM_DEFAULT */
+
+#endif // SEC_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/slimbus_bios_settings.h b/ChvRefCodePkg/Include/PnP/slimbus_bios_settings.h new file mode 100644 index 0000000000..c110ec740e --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/slimbus_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef SLIMBUS_BIOS_SETTINGS_HH
+#define SLIMBUS_BIOS_SETTINGS_HH
+
+#endif // SLIMBUS_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/PnP/ssp_bios_settings.h b/ChvRefCodePkg/Include/PnP/ssp_bios_settings.h new file mode 100644 index 0000000000..b12db627eb --- /dev/null +++ b/ChvRefCodePkg/Include/PnP/ssp_bios_settings.h @@ -0,0 +1,18 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef SSP_BIOS_SETTINGS_HH
+#define SSP_BIOS_SETTINGS_HH
+
+#endif // SSP_BIOS_SETTINGS_HH
diff --git a/ChvRefCodePkg/Include/Protocol/BootMaterialProtocol.h b/ChvRefCodePkg/Include/Protocol/BootMaterialProtocol.h new file mode 100644 index 0000000000..542edc21d6 --- /dev/null +++ b/ChvRefCodePkg/Include/Protocol/BootMaterialProtocol.h @@ -0,0 +1,163 @@ +/** @file
+ Ihis protocol is defined to pass the Boot Material and OS Loader RIP to VMM.
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __BOOT_MATERIAL_H__
+#define __BOOT_MATERIAL_H__
+
+#include "MkhiMsgs.h"
+
+#define EFI_BOOT_MATERIAL_PROTOCOL_GUID \
+ {0x1d011a41, 0xfb19, 0x4a03, 0xa5, 0xca, 0xed, 0x33, 0x87, 0x4, 0xa1, 0xd2}
+
+typedef struct _EFI_BOOT_MATERIAL_PROTOCOL EFI_BOOT_MATERIAL_PROTOCOL;
+
+#define BOOT_MATERIAL SL_HI_GET_BOOT_MATERIAL_ACK_DATA
+
+/**
+ The EFI_BOOT_MATERIAL_PROTOCOL GetBootMaterial function call provides the Boot Material recieved from SEC FW
+
+ @param[in] This Indicates the calling context
+ @param[out] BootMaterial Pointer to Boot material recieved from SEC FW
+
+ @retval EFI_SUCCESS Operation completed successfully.
+ @retval EFI_DEVICE_ERROR The command was unsuccessful.
+ The ProtocolCapability variable will not be populated.
+ @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect.
+ The ProtocolCapability variable will not be populated.
+ @retval EFI_BUFFER_TOO_SMALL The ProtocolCapability variable is too small to hold the full response.
+ It will be partially populated (required Size field will be set).
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BOOT_MATERIAL_GET_BOOT_MATERIAL) (
+ IN EFI_BOOT_MATERIAL_PROTOCOL *This,
+ IN OUT BOOT_MATERIAL *BootMaterial,
+ IN OUT UINT32 *GetBootInfoResult
+ );
+
+/**
+ Returns OS loader image handle.
+
+ @param[in] Indicates the calling context.
+ @param[out] OS loader image handle
+
+ @retval EFI_SUCCESS The OS loader was successfully loaded and the image handle is valid.
+ @retval EFI_LOAD_ERROR The OS loader failed to load and the image handle is not valid (set to NULL).
+ @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BOOT_MATERIAL_GET_OSLOADER_IMAGE_HANDLE) (
+ IN EFI_BOOT_MATERIAL_PROTOCOL *This,
+ OUT EFI_HANDLE *OSLoaderImageHandle
+ );
+
+/**
+ The EFI_BOOT_MATERIAL_PROTOCOL Get FingerprintSensor IMR Address.
+
+ @param[in] This Indicates the calling context
+ @param[out] FPSBase FingerprintSensor IMR base address
+ @param[out] FPSSize FingerprintSensor IMR size
+
+ @retval EFI_SUCCESS Operation completed successfully.
+ @retval EFI_DEVICE_ERROR The command was unsuccessful.
+ @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect
+ (e.g. asking for an event log whose format is not supported).
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BOOT_MATERIAL_GET_FPS_ADDR) (
+ IN EFI_BOOT_MATERIAL_PROTOCOL *This,
+ OUT UINT32 *FPSBase,
+ OUT UINT32 *FPSSize
+ );
+
+/**
+ The EFI_BOOT_MATERIAL_PROTOCOL Get SilentLake IMR Address
+
+ @param[in] This Indicates the calling context
+ @param[out] SLBase SilentLake IMR base address
+ @param[out] SLSize SilentLake IMR size
+
+ @retval EFI_SUCCESS Operation completed successfully.
+ @retval EFI_DEVICE_ERROR The command was unsuccessful.
+ @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect
+ (e.g. asking for an event log whose format is not supported).
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BOOT_MATERIAL_GET_SL_ADDR) (
+ IN EFI_BOOT_MATERIAL_PROTOCOL *This,
+ OUT UINT32 *SLBase,
+ OUT UINT32 *SLSize
+ );
+
+struct _EFI_BOOT_MATERIAL_PROTOCOL {
+ EFI_BOOT_MATERIAL_GET_BOOT_MATERIAL GetBootMaterial;
+ EFI_BOOT_MATERIAL_GET_OSLOADER_IMAGE_HANDLE GetOsLoaderHandle;
+ EFI_BOOT_MATERIAL_GET_SL_ADDR GetSilentLakeAddr;
+ EFI_BOOT_MATERIAL_GET_FPS_ADDR GetFingerprintSensorAddr;
+};
+
+extern EFI_GUID gEfiBootMaterialProtocolGuid;
+
+typedef struct _EFI_SILENT_LAKE_PROTOCOL EFI_SILENT_LAKE_PROTOCOL;
+
+/**
+ The EFI_SILENT_LAKE_PROTOCOL Get VMM related Info.
+
+ @param[in] This Indicates the calling context
+
+ @retval EFI_SUCCESS Operation completed successfully.
+ @retval EFI_DEVICE_ERROR The command was unsuccessful.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SILENT_LAKE_GET_VMM_INFO) (
+ IN EFI_SILENT_LAKE_PROTOCOL *This
+ );
+
+/**
+ The EFI_SILENT_LAKE_PROTOCOL Verify VMM.
+
+ @param[in] This Indicates the calling context
+
+ @retval EFI_SUCCESS Operation completed successfully.
+ @retval EFI_DEVICE_ERROR The command was unsuccessful.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SILENT_LAKE_VERIFY_VMM) (
+ IN EFI_SILENT_LAKE_PROTOCOL *This,
+ IN UINT8 *ImageBase,
+ IN UINTN ImageSize
+ );
+
+struct _EFI_SILENT_LAKE_PROTOCOL {
+ EFI_SILENT_LAKE_GET_VMM_INFO GetVmmInfo;
+ EFI_SILENT_LAKE_VERIFY_VMM VerifyVmm;
+ EFI_EVENT StartVmmEvent;
+};
+
+extern EFI_GUID gEfiSilentLakeProtocolGuid;
+extern EFI_GUID gVmmDebugEnableDisableGuid;
+#define VMM_DEBUG_VARIABLE_NAME L"VmmDebugVar"
+
+#endif
diff --git a/ChvRefCodePkg/Include/Protocol/EfiUsbFnIo.h b/ChvRefCodePkg/Include/Protocol/EfiUsbFnIo.h new file mode 100644 index 0000000000..e3107160bb --- /dev/null +++ b/ChvRefCodePkg/Include/Protocol/EfiUsbFnIo.h @@ -0,0 +1,411 @@ +/** @file
+ EFI USB function IO Protocol
+ This protocol supports Usb Function IO API.
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __EFI_USB_FUNC_IO_H__
+#define __EFI_USB_FUNC_IO_H__
+
+#include <IndustryStandard/Usb.h>
+
+#define EFI_USBFN_IO_PROTOCOL_REVISION 0x00010001
+
+typedef struct _EFI_USBFN_IO_PROTOCOL EFI_USBFN_IO_PROTOCOL;
+
+//
+// USB standard descriptors and reqeust
+//
+typedef USB_DEVICE_REQUEST EFI_USB_DEVICE_REQUEST;
+typedef USB_DEVICE_DESCRIPTOR EFI_USB_DEVICE_DESCRIPTOR;
+typedef USB_CONFIG_DESCRIPTOR EFI_USB_CONFIG_DESCRIPTOR;
+typedef USB_INTERFACE_DESCRIPTOR EFI_USB_INTERFACE_DESCRIPTOR;
+typedef USB_ENDPOINT_DESCRIPTOR EFI_USB_ENDPOINT_DESCRIPTOR;
+
+typedef enum _EFI_USBFN_PORT_TYPE {
+ EfiUsbUnknownPort = 0,
+ EfiUsbStandardDownstreamPort,
+ EfiUsbChargingDownstreamPort,
+ EfiUsbDedicatedChargingPort,
+ EfiUsbInvalidDedicatedChargingPort
+} EFI_USBFN_PORT_TYPE;
+
+/**
+ USB_DEVICE_DESCRIPTOR, USB_CONFIG_DESCRIPTOR, USB_INTERFACE_DESCRIPTOR, and
+ USB_ENDPOINT_DESCRIPTOR are already defined
+ in UEFI spec 2.3, as par USB 2.0 spec.
+**/
+
+typedef struct {
+ EFI_USB_INTERFACE_DESCRIPTOR *InterfaceDescriptor;
+ EFI_USB_ENDPOINT_DESCRIPTOR **EndpointDescriptorTable;
+} EFI_USB_INTERFACE_INFO;
+
+typedef struct {
+ EFI_USB_CONFIG_DESCRIPTOR *ConfigDescriptor;
+ EFI_USB_INTERFACE_INFO **InterfaceInfoTable;
+} EFI_USB_CONFIG_INFO;
+
+typedef struct {
+ EFI_USB_DEVICE_DESCRIPTOR *DeviceDescriptor;
+ EFI_USB_CONFIG_INFO **ConfigInfoTable;
+} EFI_USB_DEVICE_INFO;
+
+typedef enum _EFI_USB_ENDPOINT_TYPE {
+ UsbEndpointControl = 0x00,
+ UsbEndpointIsochronous = 0x01,
+ UsbEndpointBulk = 0x02,
+ UsbEndpointInterrupt = 0x03
+} EFI_USB_ENDPOINT_TYPE;
+
+typedef enum _EFI_USBFN_DEVICE_INFO_ID {
+ EfiUsbDeviceInfoUnknown = 0,
+ EfiUsbDeviceInfoSerialNumber,
+ EfiUsbDeviceInfoManufacturerName,
+ EfiUsbDeviceInfoProductName
+} EFI_USBFN_DEVICE_INFO_ID;
+
+typedef enum _EFI_USBFN_ENDPOINT_DIRECTION {
+ EfiUsbEndpointDirectionHostOut = 0,
+ EfiUsbEndpointDirectionHostIn,
+ EfiUsbEndpointDirectionDeviceTx = EfiUsbEndpointDirectionHostIn,
+ EfiUsbEndpointDirectionDeviceRx = EfiUsbEndpointDirectionHostOut
+} EFI_USBFN_ENDPOINT_DIRECTION;
+
+typedef enum _EFI_USBFN_MESSAGE {
+ //
+ // Nothing
+ //
+ EfiUsbMsgNone = 0,
+ //
+ // SETUP packet is received, returned Buffer contains
+ // EFI_USB_DEVICE_REQUEST struct
+ //
+ EfiUsbMsgSetupPacket,
+ //
+ // Indicates that some of the requested data has been received from the
+ // host. It is the responsibility of the class driver to determine if it
+ // needs to wait for any remaining data. Returned Buffer contains
+ // EFI_USBFN_TRANSFER_RESULT struct containing endpoint number, transfer
+ // status and count of bytes received.
+ //
+ EfiUsbMsgEndpointStatusChangedRx,
+ //
+ // Indicates that some of the requested data has been transmitted to the
+ // host. It is the responsibility of the class driver to determine if any
+ // remaining data needs to be resent. Returned Buffer contains
+ // EFI_USBFN_TRANSFER_RESULT struct containing endpoint number, transfer
+ // status and count of bytes sent.
+ //
+ EfiUsbMsgEndpointStatusChangedTx,
+ //
+ // DETACH bus event signaled
+ //
+ EfiUsbMsgBusEventDetach,
+ //
+ // ATTACH bus event signaled
+ //
+ EfiUsbMsgBusEventAttach,
+ //
+ // RESET bus event signaled
+ //
+ EfiUsbMsgBusEventReset,
+ //
+ // SUSPEND bus event signaled
+ //
+ EfiUsbMsgBusEventSuspend,
+ //
+ // RESUME bus event signaled
+ //
+ EfiUsbMsgBusEventResume,
+ //
+ // Bus speed updated, returned buffer indicated bus speed using
+ // following enumeration named EFI_USB_BUS_SPEED
+ //
+ EfiUsbMsgBusEventSpeed
+} EFI_USBFN_MESSAGE;
+
+typedef enum _EFI_USBFN_TRANSFER_STATUS {
+ UsbTransferStatusUnknown = 0,
+ UsbTransferStatusComplete,
+ UsbTransferStatusAborted,
+ UsbTransferStatusActive,
+ UsbTransferStatusNone
+} EFI_USBFN_TRANSFER_STATUS;
+
+typedef struct _EFI_USBFN_TRANSFER_RESULT {
+ UINTN BytesTransferred;
+ EFI_USBFN_TRANSFER_STATUS TransferStatus;
+ UINT8 EndpointIndex;
+ EFI_USBFN_ENDPOINT_DIRECTION Direction;
+ VOID *Buffer;
+} EFI_USBFN_TRANSFER_RESULT;
+
+typedef enum _EFI_USB_BUS_SPEED {
+ UsbBusSpeedUnknown = 0,
+ UsbBusSpeedLow,
+ UsbBusSpeedFull,
+ UsbBusSpeedHigh,
+ UsbBusSpeedSuper,
+ UsbBusSpeedMaximum = UsbBusSpeedSuper
+} EFI_USB_BUS_SPEED;
+
+typedef union _EFI_USBFN_MESSAGE_PAYLOAD {
+ EFI_USB_DEVICE_REQUEST udr;
+ EFI_USBFN_TRANSFER_RESULT utr;
+ EFI_USB_BUS_SPEED ubs;
+} EFI_USBFN_MESSAGE_PAYLOAD;
+
+typedef enum _EFI_USBFN_POLICY_TYPE {
+ EfiUsbPolicyUndefined = 0,
+ EfiUsbPolicyMaxTransactionSize,
+ EfiUsbPolicyZeroLengthTerminationSupport,
+ EfiUsbPolicyZeroLengthTermination
+} EFI_USBFN_POLICY_TYPE;
+
+/**
+ Allocates transfer buffer of the specified size that satisfies
+ controller requirements.
+
+ The AllocateTransferBuffer function allocates a memory region of Size bytes and
+ returns the address of the allocated memory that satisfies underlying
+ controller requirements in the location referenced by Buffer.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER) (
+ IN EFI_USBFN_IO_PROTOCOL *This,
+ IN UINTN Size,
+ OUT VOID **Buffer
+ );
+
+/**
+ Deallocates the memory allocated for the transfer buffer by AllocateTransferBuffer function.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_USBFN_IO_FREE_TRANSFER_BUFFER) (
+ IN EFI_USBFN_IO_PROTOCOL *This,
+ IN VOID *Buffer
+ );
+
+/**
+ Returns information about what type of device was attached.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_USBFN_IO_DETECT_PORT) (
+ IN EFI_USBFN_IO_PROTOCOL *This,
+ OUT EFI_USBFN_PORT_TYPE *PortType
+ );
+
+/**
+ Configure endpoints based on supplied device and configuration descriptors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS) (
+ IN EFI_USBFN_IO_PROTOCOL *This,
+ IN EFI_USB_DEVICE_INFO *DeviceInfo
+ );
+
+/**
+ Returns the maximum packet size of the specified endpoint type for the supplied bus speed.
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE) (
+ IN EFI_USBFN_IO_PROTOCOL *This,
+ IN EFI_USB_ENDPOINT_TYPE EndpointType,
+ IN EFI_USB_BUS_SPEED BusSpeed,
+ OUT UINT16 *MaxPacketSize
+ );
+
+/**
+ Returns the maximum supported transfer size.
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_USBFN_IO_GET_MAXTRANSFER_SIZE) (
+ IN EFI_USBFN_IO_PROTOCOL *This,
+ OUT UINTN *MaxTransferSize
+ );
+
+/**
+ Returns device specific information based on the supplied identifier as a
+ Unicode string.
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_USBFN_IO_GET_DEVICE_INFO) (
+ IN EFI_USBFN_IO_PROTOCOL *This,
+ IN EFI_USBFN_DEVICE_INFO_ID Id,
+ IN OUT UINTN *BufferSize,
+ OUT VOID *Buffer OPTIONAL
+ );
+
+/**
+ Returns vendor-id and product-id of the device.
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID) (
+ IN EFI_USBFN_IO_PROTOCOL *This,
+ OUT UINT16 *Vid,
+ OUT UINT16 *Pid
+ );
+
+/**
+ Aborts transfer on the specified endpoint.
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_USBFN_IO_ABORT_TRANSFER) (
+ IN EFI_USBFN_IO_PROTOCOL *This,
+ IN UINT8 EndpointIndex,
+ IN EFI_USBFN_ENDPOINT_DIRECTION Direction
+ );
+
+/**
+ Returns the stall state on the specified endpoint.
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE) (
+ IN EFI_USBFN_IO_PROTOCOL *This,
+ IN UINT8 EndpointIndex,
+ IN EFI_USBFN_ENDPOINT_DIRECTION Direction,
+ IN OUT BOOLEAN *State
+ );
+
+/**
+ Sets or clears the stall state on the specified endpoint.
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE) (
+ IN EFI_USBFN_IO_PROTOCOL *This,
+ IN UINT8 EndpointIndex,
+ IN EFI_USBFN_ENDPOINT_DIRECTION Direction,
+ IN BOOLEAN State
+ );
+
+/**
+ This function is called repeatedly to receive updates on USB bus states,
+ receive, transmit status changes on endpoints and setup packet on endpoint 0.
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_USBFN_IO_EVENTHANDLER) (
+ IN EFI_USBFN_IO_PROTOCOL *This,
+ OUT EFI_USBFN_MESSAGE *Message,
+ IN OUT UINTN *PayloadSize,
+ OUT EFI_USBFN_MESSAGE_PAYLOAD *Payload
+ );
+
+/**
+ Primary function to handle transfer in either direction based on specified
+ direction and on the specified endpoint.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_USBFN_IO_TRANSFER) (
+ IN EFI_USBFN_IO_PROTOCOL *This,
+ IN UINT8 EndpointIndex,
+ IN EFI_USBFN_ENDPOINT_DIRECTION Direction,
+ IN OUT UINTN *BufferSize,
+ IN OUT VOID *Buffer
+ );
+
+/**
+ This function supplies power to the USB controller if needed,
+ initialize hardware and internal data structures, and then return.
+
+ The port must not be activated by this function.
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_USBFN_IO_START_CONTROLLER) (
+ IN EFI_USBFN_IO_PROTOCOL *This
+ );
+
+/**
+ This function disables the hardware device by resetting the run/stop bit and
+ power off the USB controller if needed.
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_USBFN_IO_STOP_CONTROLLER) (
+ IN EFI_USBFN_IO_PROTOCOL *This
+ );
+
+/**
+ This function sets the configuration policy for the specified non-control endpoint.
+
+ Refer to the description for calling restrictions.
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_USBFN_IO_SET_ENDPOINT_POLICY) (
+ IN EFI_USBFN_IO_PROTOCOL *This,
+ IN UINT8 EndpointIndex,
+ IN EFI_USBFN_ENDPOINT_DIRECTION Direction,
+ IN EFI_USBFN_POLICY_TYPE PolicyType,
+ IN UINTN BufferSize,
+ IN VOID *Buffer
+ );
+
+/**
+ This function retrieves the configuration policy for the specified non-control endpoint.
+
+ There are no associated calling restrictions for this function.
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_USBFN_IO_GET_ENDPOINT_POLICY) (
+ IN EFI_USBFN_IO_PROTOCOL *This,
+ IN UINT8 EndpointIndex,
+ IN EFI_USBFN_ENDPOINT_DIRECTION Direction,
+ IN EFI_USBFN_POLICY_TYPE PolicyType,
+ IN OUT UINTN *BufferSize,
+ IN OUT VOID *Buffer
+ );
+
+struct _EFI_USBFN_IO_PROTOCOL {
+ UINT32 Revision;
+ EFI_USBFN_IO_DETECT_PORT DetectPort;
+ EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS ConfigureEnableEndpoints;
+ EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE GetEndpointMaxPacketSize;
+ EFI_USBFN_IO_GET_DEVICE_INFO GetDeviceInfo;
+ EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID GetVendorIdProductId;
+ EFI_USBFN_IO_ABORT_TRANSFER AbortTransfer;
+ EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE GetEndpointStallState;
+ EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE SetEndpointStallState;
+ EFI_USBFN_IO_EVENTHANDLER EventHandler;
+ EFI_USBFN_IO_TRANSFER Transfer;
+ EFI_USBFN_IO_GET_MAXTRANSFER_SIZE GetMaxTransferSize;
+ EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER AllocateTransferBuffer;
+ EFI_USBFN_IO_FREE_TRANSFER_BUFFER FreeTransferBuffer;
+
+ /// Valid for version EFI_USBFN_IO_PROTOCOL_REVISION2 and above
+ EFI_USBFN_IO_START_CONTROLLER StartController;
+ EFI_USBFN_IO_STOP_CONTROLLER StopController;
+ EFI_USBFN_IO_SET_ENDPOINT_POLICY SetEndpointPolicy;
+ EFI_USBFN_IO_GET_ENDPOINT_POLICY GetEndpointPolicy;
+};
+
+extern EFI_GUID gEfiUsbFnIoProtocolGuid;
+#endif
diff --git a/ChvRefCodePkg/Include/Protocol/PlatformPmicProtocol.h b/ChvRefCodePkg/Include/Protocol/PlatformPmicProtocol.h new file mode 100644 index 0000000000..36c15ad063 --- /dev/null +++ b/ChvRefCodePkg/Include/Protocol/PlatformPmicProtocol.h @@ -0,0 +1,84 @@ +/** @file
+ Header file for Platform PMIC Protocol.
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PLATFORM_PMIC_PROTOCOL_H
+#define _PLATFORM_PMIC_PROTOCOL_H
+
+//#define EFI_PLATFORM_PMIC_PROTOCOL_GUID {0x466cf304, 0x5dc3, 0x4ef5, 0x83, 0x5c, 0xc0, 0xae, 0xcc, 0xbc, 0x2f, 0xde}
+
+typedef struct _EFI_PLATFORM_PMIC_PROTOCOL EFI_PLATFORM_PMIC_PROTOCOL;
+
+extern EFI_GUID gDxePlatformPmicProtocolGuid;
+
+/**
+ @param[in] This Pointer to EFI_PLATFORM_PMIC_PROTOCOL
+ @param[in] Address PMIC register offset address to be read
+ @param[in] Data Data to be written to "Address"
+
+ @retval EFI_SUCCESS Successfully read the value
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PLATFORM_PMIC_PROTOCOL_WRITE) (
+ IN EFI_PLATFORM_PMIC_PROTOCOL *This,
+ IN UINT8 Address,
+ IN UINT8 Data
+ );
+
+/**
+ @param[in] This Pointer to EFI_PLATFORM_PMIC_PROTOCOL
+ @param[in] Address PMIC register offset address to be read
+
+ @retval Data Read value from the "Address"
+
+**/
+typedef
+UINT8
+(EFIAPI *EFI_PLATFORM_PMIC_PROTOCOL_READ) (
+ IN EFI_PLATFORM_PMIC_PROTOCOL *This,
+ IN UINT8 Address
+ );
+
+//
+// Interface structure for the Platform PMIC Protocol
+//
+struct _EFI_PLATFORM_PMIC_PROTOCOL {
+ EFI_PLATFORM_PMIC_PROTOCOL_WRITE PmicWriteByte;
+ EFI_PLATFORM_PMIC_PROTOCOL_READ PmicReadByte;
+};
+
+/**
+ @todo add description
+**/
+UINT8
+EFIAPI
+PmicReadByte (
+ IN EFI_PLATFORM_PMIC_PROTOCOL *This,
+ IN UINT8 Address
+ );
+
+/**
+ @todo add description
+**/
+EFI_STATUS
+EFIAPI
+PmicWriteByte (
+ IN EFI_PLATFORM_PMIC_PROTOCOL *This,
+ IN UINT8 Address,
+ IN UINT8 Data
+ );
+
+#endif
diff --git a/ChvRefCodePkg/Include/Protocol/UsbDeviceModeProtocol.h b/ChvRefCodePkg/Include/Protocol/UsbDeviceModeProtocol.h new file mode 100644 index 0000000000..e76632110f --- /dev/null +++ b/ChvRefCodePkg/Include/Protocol/UsbDeviceModeProtocol.h @@ -0,0 +1,103 @@ +/** @file
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _USB_DEVICE_MODE_PROTOCOL_H_
+#define _USB_DEVICE_MODE_PROTOCOL_H_
+
+#include <Library/UsbDeviceLib.h>
+
+///
+/// UsbDeviceMode Protocol GUID.
+///
+#define EFI_USB_DEVICE_MODE_PROTOCOL_GUID \
+ {0xC9923F7E, 0x1746, 0x4802, { 0x86, 0x2e, 0x1, 0x1c, 0x2c, 0x2d, 0x9d, 0x86 } }
+
+typedef struct _EFI_USB_DEVICE_MODE_PROTOCOL EFI_USB_DEVICE_MODE_PROTOCOL;
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_USB_DEVICE_MODE_INIT_XDCI) (
+ IN EFI_USB_DEVICE_MODE_PROTOCOL *This
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_USB_DEVICE_MODE_CONNECT) (
+ IN EFI_USB_DEVICE_MODE_PROTOCOL *This
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_USB_DEVICE_MODE_DISCONNECT) (
+ IN EFI_USB_DEVICE_MODE_PROTOCOL *This
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_USB_DEVICE_EP_TX_DATA) (
+ IN EFI_USB_DEVICE_MODE_PROTOCOL *This,
+ IN USB_DEVICE_IO_REQ *IoRequest
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_USB_DEVICE_EP_RX_DATA) (
+ IN EFI_USB_DEVICE_MODE_PROTOCOL *This,
+ IN USB_DEVICE_IO_REQ *IoRequest
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_USB_DEVICE_MODE_BIND) (
+ IN EFI_USB_DEVICE_MODE_PROTOCOL *This,
+ IN USB_DEVICE_OBJ *UsbdDevObj
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_USB_DEVICE_MODE_UNBIND) (
+ IN EFI_USB_DEVICE_MODE_PROTOCOL *This
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_USB_DEVICE_MODE_STOP) (
+ IN EFI_USB_DEVICE_MODE_PROTOCOL *This
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_USB_DEVICE_MODE_RUN) (
+ IN EFI_USB_DEVICE_MODE_PROTOCOL *This,
+ IN UINT32 TimeoutMs
+ );
+
+///
+/// Usb Device Mode Protocol Structure.
+///
+struct _EFI_USB_DEVICE_MODE_PROTOCOL {
+ EFI_USB_DEVICE_MODE_INIT_XDCI InitXdci;
+ EFI_USB_DEVICE_MODE_CONNECT Connect;
+ EFI_USB_DEVICE_MODE_DISCONNECT DisConnect;
+ EFI_USB_DEVICE_EP_TX_DATA EpTxData;
+ EFI_USB_DEVICE_EP_RX_DATA EpRxData;
+ EFI_USB_DEVICE_MODE_BIND Bind;
+ EFI_USB_DEVICE_MODE_UNBIND UnBind;
+ EFI_USB_DEVICE_MODE_RUN Run;
+ EFI_USB_DEVICE_MODE_STOP Stop;
+};
+
+extern EFI_GUID gEfiUsbDeviceModeProtocolGuid;
+
+#endif
diff --git a/ChvRefCodePkg/Include/Rsci.h b/ChvRefCodePkg/Include/Rsci.h new file mode 100644 index 0000000000..d9eafa7466 --- /dev/null +++ b/ChvRefCodePkg/Include/Rsci.h @@ -0,0 +1,128 @@ +/** @file
+
+ Copyright (c) 1996 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _RSCI_H
+#define _RSCI_H
+
+//
+// Statements that include other files
+//
+#include <IndustryStandard/Acpi10.h>
+#include <IndustryStandard/Acpi20.h>
+#include <IndustryStandard/Acpi30.h>
+
+//
+// Definitions
+//
+#define EFI_ACPI_OEM_RSCI_REVISION 0x00000000
+#define EFI_ACPI_RSCI_REVISION 1
+#define EFI_ACPI_RESET_SHUTDOWN_COMMUNICATION_INTERFACE_SIGNATURE SIGNATURE_32('R', 'S', 'C', 'I')
+#ifndef EFI_ACPI_OEM_ID
+#define EFI_ACPI_OEM_ID 'I','N','T','E','L',' ' // 6 Bytes long
+#endif
+#define EFI_ACPI_RSCI_OEM_TABLE_ID SIGNATURE_64 ('B','O','O','T','S','R','C',' ') // OEM table id 8 bytes long
+//
+// RSCI structure
+//
+//
+// Ensure proper structure formats
+//
+
+#pragma pack(1)
+
+typedef enum {
+ FBR_NONE = 0,
+ FBR_WATCHDOG_COUNTER_EXCEEDED,
+ FBR_NO_MATCHING_OS,
+
+ FBR_INVALID_OSNIB_CHECKSUM,
+} FALL_BACK_POLICY_REASON;
+
+typedef struct {
+ FALL_BACK_POLICY_REASON FallbackPolicyReason;
+ UINT8 FastbootCombo;
+ UINT8 Reserved[2];
+} EFI_ACPI_RSCI_INDICATORS;
+
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 WakeSrc;
+ UINT8 Resets;
+ UINT8 ResetType;
+ UINT8 ShuntdownSrc;
+ EFI_ACPI_RSCI_INDICATORS Indicators;
+} EFI_ACPI_RESET_SHUTDOWN_COMMUNICATION_INTERFACE;
+
+#pragma pack()
+
+//
+//Android Wake Sources for S4/S5
+//
+typedef enum {
+ WAKE_NOT_APPLICABLE = 0,
+ WAKE_BATTERY_INSERTED,
+ WAKE_USB_CHARGER_INSERTED,
+ WAKE_ACDC_CHARGER_INSERTED,
+ WAKE_POWER_BUTTON_PRESSED,
+ WAKE_RTC_TIMER,
+ WAKE_BATTERY_REACHED_IA_THRESHOLD
+} ANDROID_WAKE_SOURCE;
+
+//
+//Android Reset Sources
+//
+typedef enum {
+ RESET_NOT_APPLICABLE = 0,
+ RESET_OS_INITIATED,
+ RESET_FORCED,
+ RESET_FW_UPDATE,
+ RESET_KERNEL_WATCHDOG,
+ RESET_SECURITY_WATCHDOG,
+ RESET_SECURITY_INITIATED,
+ RESET_PMC_WATCHDOG,
+ RESET_EC_WATCHDOG,
+ RESET_PLATFORM_WATCHDOG,
+} ANDROID_RESET_SOURCE;
+
+typedef enum {
+ NOT_APPLICABLE_RESET = 0,
+ WARM_RESET = 1,
+ COLD_RESET = 2,
+ GLOBAL_RESET = 7,
+}ANDROID_RESET_TYPE;
+
+//
+//Android Shutdown sources
+//
+typedef enum {
+ SHTDWN_NOT_APPLICABLE = 0,
+ SHTDWN_POWER_BUTTON_OVERRIDE,
+ SHTDWN_BATTERY_REMOVAL,
+ SHTDWN_VCRIT,
+ SHTDWN_THERMTRIP,
+ SHTDWN_PMICTEMP,
+ SHTDWN_SYSTEMP,
+ SHTDWN_BATTEMP,
+ SHTDWN_SYSUVP,
+ SHTDWN_SYSOVP,
+ SHTDWN_SECURITY_WATCHDOG,
+ SHTDWN_SECURITY_INITIATED,
+ SHTDWN_PMC_WATCHDOG,
+ SHTDWN_EC_WATCHDOG,
+ SHTDWN_PLATFORM_WATCHDOG,
+ SHTDWN_KERNEL_WATCHDOG
+}ANDROID_SHUTDOWN_SOURCE;
+
+#define EFI_OS_INDICATIONS_OS_INITIATED_RESET 0x00000040
+#endif
|