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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2016-10-31 15:43:49 +0000 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2016-11-02 16:22:48 +0000 |
| commit | 756a514aa469c35e1a21c034a513630b7f02ecff (patch) | |
| tree | 724b4ec60a9db9a6d7301963c7719e5377e1cb50 /Conf | |
| parent | a8f37449c7e355e6402e3876c9db9e11d875164f (diff) | |
| download | edk2-platforms-756a514aa469c35e1a21c034a513630b7f02ecff.tar.xz | |
ArmPkg/CpuDxe: set DmaBufferAlignment according to CWG
The DmaBufferAlignment currently defaults to 4, which is dangerously
small and may result in lost data on platforms that perform non-coherent
DMA. So instead, take the CWG value from the cache info registers.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Conf')
0 files changed, 0 insertions, 0 deletions