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| author | Ruiyu Ni <ruiyu.ni@intel.com> | 2017-06-02 15:45:42 +0800 |
|---|---|---|
| committer | Guo Mang <mang.guo@intel.com> | 2017-07-12 11:24:53 +0800 |
| commit | 4134492635d78454857bca32ce16efb7aa846840 (patch) | |
| tree | a9b1aeeb4aab176febcd979c0633471149e6a991 /Core | |
| parent | 898dfba71965d11c350e349828ebddddb9090353 (diff) | |
| download | edk2-platforms-4134492635d78454857bca32ce16efb7aa846840.tar.xz | |
MdeModulePkg/Xhci: Correct the indention of comments
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
(cherry picked from commit b0b626ea2f16faca9f864599384fd184a89e0195)
Diffstat (limited to 'Core')
| -rw-r--r-- | Core/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/Core/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/Core/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c index 2ad5ffd396..078e9e5e30 100644 --- a/Core/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c +++ b/Core/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c @@ -1369,10 +1369,10 @@ XhciDelAllAsyncIntTransfers ( EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
- //
- // Device doesn't finish the IntTransfer until real data comes
- // So the TRB should be removed as well.
- //
+ //
+ // Device doesn't finish the IntTransfer until real data comes
+ // So the TRB should be removed as well.
+ //
Status = XhcDequeueTrbFromEndpoint (Xhc, Urb);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhciDelAllAsyncIntTransfers: XhcDequeueTrbFromEndpoint failed\n"));
|