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authorMaurice Ma <maurice.ma@intel.com>2015-03-31 01:06:23 +0000
committermauricema <mauricema@Edk2>2015-03-31 01:06:23 +0000
commitfce4ecd92cf137d479c0dc97461bec3512e9c98d (patch)
tree58c77cce1adb54af4e94ec196c0db9448a09154b /CorebootModulePkg/CbSupportPei
parent14df6e059c9115108c9fcbbceac2ae4c6fc7ee94 (diff)
downloadedk2-platforms-fce4ecd92cf137d479c0dc97461bec3512e9c98d.tar.xz
Pkg-Module: CorebootModulePkg
Initial coreboot UEFI payload code check in. It provides UEFI services on top of coreboot that allows UEFI OS boot. CorebootModulePkg is the source code package of coreboot support modules that will be used to parse the coreboot tables and report memory/io resources. It supports the following features: - Support Unified Extensible Firmware Interface (UEFI) specification 2.4. - Support Platform Initialization(PI) specification 1.3. - Support execution as a coreboot payload. - Support USB 3.0 - Support SATA/ATA devices. - Support EFI aware OS boot. The following features are not supported currently and have not been validated: - GCC Tool Chains - SMM Execution Environment - Security Boot It was tested on a Intel Bay Trail CRB platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17084 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'CorebootModulePkg/CbSupportPei')
-rw-r--r--CorebootModulePkg/CbSupportPei/CbSupportPei.c380
-rw-r--r--CorebootModulePkg/CbSupportPei/CbSupportPei.h40
-rw-r--r--CorebootModulePkg/CbSupportPei/CbSupportPei.inf72
3 files changed, 492 insertions, 0 deletions
diff --git a/CorebootModulePkg/CbSupportPei/CbSupportPei.c b/CorebootModulePkg/CbSupportPei/CbSupportPei.c
new file mode 100644
index 0000000000..d51553dbc6
--- /dev/null
+++ b/CorebootModulePkg/CbSupportPei/CbSupportPei.c
@@ -0,0 +1,380 @@
+/** @file
+ This PEIM will parse coreboot table in memory and report resource information into pei core.
+ This file contains the main entrypoint of the PEIM.
+
+Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include "CbSupportPei.h"
+
+EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
+ { EfiACPIReclaimMemory, 0x008 },
+ { EfiACPIMemoryNVS, 0x004 },
+ { EfiReservedMemoryType, 0x004 },
+ { EfiRuntimeServicesData, 0x080 },
+ { EfiRuntimeServicesCode, 0x080 },
+ { EfiMaxMemoryType, 0 }
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gEfiPeiMasterBootModePpiGuid,
+ NULL
+ }
+};
+
+/**
+ Create memory mapped io resource hob.
+
+ @param MmioBase Base address of the memory mapped io range
+ @param MmioSize Length of the memory mapped io range
+
+**/
+VOID
+BuildMemoryMappedIoRangeHob (
+ EFI_PHYSICAL_ADDRESS MmioBase,
+ UINT64 MmioSize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED),
+ MmioBase,
+ MmioSize
+ );
+
+ BuildMemoryAllocationHob (
+ MmioBase,
+ MmioSize,
+ EfiMemoryMappedIO
+ );
+}
+
+/**
+ Check the integrity of firmware volume header
+
+ @param[in] FwVolHeader A pointer to a firmware volume header
+
+ @retval TRUE The firmware volume is consistent
+ @retval FALSE The firmware volume has corrupted.
+
+**/
+STATIC
+BOOLEAN
+IsFvHeaderValid (
+ IN EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader
+ )
+{
+ UINT16 Checksum;
+
+ // Skip nv storage fv
+ if (CompareMem (&FwVolHeader->FileSystemGuid, &gEfiFirmwareFileSystem2Guid, sizeof(EFI_GUID)) != 0 ) {
+ return FALSE;
+ }
+
+ if ( (FwVolHeader->Revision != EFI_FVH_REVISION) ||
+ (FwVolHeader->Signature != EFI_FVH_SIGNATURE) ||
+ (FwVolHeader->FvLength == ((UINTN) -1)) ||
+ ((FwVolHeader->HeaderLength & 0x01 ) !=0) ) {
+ return FALSE;
+ }
+
+ Checksum = CalculateCheckSum16 ((UINT16 *) FwVolHeader, FwVolHeader->HeaderLength);
+ if (Checksum != 0) {
+ DEBUG (( DEBUG_ERROR,
+ "ERROR - Invalid Firmware Volume Header Checksum, change 0x%04x to 0x%04x\r\n",
+ FwVolHeader->Checksum,
+ (UINT16)( Checksum + FwVolHeader->Checksum )));
+ return FALSE;
+ }
+
+ return TRUE;
+}
+
+/**
+ Install FvInfo PPI and create fv hobs for remained fvs
+
+**/
+VOID
+CbPeiReportRemainedFvs (
+ VOID
+ )
+{
+ UINT8* TempPtr;
+ UINT8* EndPtr;
+
+ TempPtr = (UINT8* )(UINTN) PcdGet32 (PcdPayloadFdMemBase);
+ EndPtr = (UINT8* )(UINTN) (PcdGet32 (PcdPayloadFdMemBase) + PcdGet32 (PcdPayloadFdMemSize));
+
+ for (;TempPtr < EndPtr;) {
+ if (IsFvHeaderValid ((EFI_FIRMWARE_VOLUME_HEADER* )TempPtr)) {
+ if (TempPtr != (UINT8* )(UINTN) PcdGet32 (PcdPayloadFdMemBase)) {
+ // Skip the PEI FV
+ DEBUG((EFI_D_ERROR, "Found one valid fv : 0x%x.\n", TempPtr, ((EFI_FIRMWARE_VOLUME_HEADER* )TempPtr)->FvLength));
+
+ PeiServicesInstallFvInfoPpi (
+ NULL,
+ (VOID *) (UINTN) TempPtr,
+ (UINT32) (UINTN) ((EFI_FIRMWARE_VOLUME_HEADER* )TempPtr)->FvLength,
+ NULL,
+ NULL
+ );
+ BuildFvHob ((EFI_PHYSICAL_ADDRESS)(UINTN) TempPtr, ((EFI_FIRMWARE_VOLUME_HEADER* )TempPtr)->FvLength);
+ }
+ }
+ TempPtr += ((EFI_FIRMWARE_VOLUME_HEADER* )TempPtr)->FvLength;
+ }
+}
+
+/**
+ This is the entrypoint of PEIM
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS if it completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+CbPeiEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ UINT64 LowMemorySize, HighMemorySize;
+ UINT64 PeiMemSize = SIZE_64MB; // 64 MB
+ EFI_PHYSICAL_ADDRESS PeiMemBase = 0;
+ UINT32 RegEax;
+ UINT8 PhysicalAddressBits;
+ VOID* pCbHeader;
+ VOID* pAcpiTable;
+ UINT32 AcpiTableSize;
+ VOID* pSmbiosTable;
+ UINT32 SmbiosTableSize;
+ SYSTEM_TABLE_INFO* pSystemTableInfo;
+ FRAME_BUFFER_INFO FbInfo;
+ FRAME_BUFFER_INFO* pFbInfo;
+ ACPI_BOARD_INFO* pAcpiBoardInfo;
+ UINTN PmCtrlRegBase, PmTimerRegBase, ResetRegAddress, ResetValue;
+
+ LowMemorySize = 0;
+ HighMemorySize = 0;
+
+ Status = CbParseMemoryInfo (&LowMemorySize, &HighMemorySize);
+ if (EFI_ERROR(Status))
+ return Status;
+
+ DEBUG((EFI_D_ERROR, "LowMemorySize: 0x%x.\n", LowMemorySize));
+ DEBUG((EFI_D_ERROR, "HighMemorySize: 0x%x.\n", HighMemorySize));
+
+ ASSERT (LowMemorySize > 0);
+
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ (
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_TESTED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
+ ),
+ (EFI_PHYSICAL_ADDRESS)(0),
+ (UINT64)(0xA0000)
+ );
+
+
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_RESERVED,
+ (
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_TESTED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
+ ),
+ (EFI_PHYSICAL_ADDRESS)(0xA0000),
+ (UINT64)(0x60000)
+ );
+
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ (
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_TESTED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
+ ),
+ (EFI_PHYSICAL_ADDRESS)(0x100000),
+ (UINT64) (LowMemorySize - 0x100000)
+ );
+
+ if (HighMemorySize > 0) {
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ (
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
+ ),
+ (EFI_PHYSICAL_ADDRESS)(0x100000000),
+ HighMemorySize
+ );
+ }
+
+ //
+ // Should be 64k aligned
+ //
+ PeiMemBase = (LowMemorySize - PeiMemSize) & (~(BASE_64KB - 1));
+
+ DEBUG((EFI_D_ERROR, "PeiMemBase: 0x%x.\n", PeiMemBase));
+ DEBUG((EFI_D_ERROR, "PeiMemSize: 0x%x.\n", PeiMemSize));
+
+ Status = PeiServicesInstallPeiMemory (
+ PeiMemBase,
+ PeiMemSize
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Set cache on the physical memory
+ //
+ MtrrSetMemoryAttribute (BASE_1MB, LowMemorySize - BASE_1MB, CacheWriteBack);
+ MtrrSetMemoryAttribute (0, 0xA0000, CacheWriteBack);
+
+ //
+ // Create Memory Type Information HOB
+ //
+ BuildGuidDataHob (
+ &gEfiMemoryTypeInformationGuid,
+ mDefaultMemoryTypeInformation,
+ sizeof(mDefaultMemoryTypeInformation)
+ );
+
+ //
+ // Create Fv hob
+ //
+ CbPeiReportRemainedFvs ();
+
+ BuildMemoryAllocationHob (
+ PcdGet32 (PcdPayloadFdMemBase),
+ PcdGet32 (PcdPayloadFdMemSize),
+ EfiBootServicesData
+ );
+
+ //
+ // Build CPU memory space and IO space hob
+ //
+ AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
+ if (RegEax >= 0x80000008) {
+ AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
+ PhysicalAddressBits = (UINT8) RegEax;
+ } else {
+ PhysicalAddressBits = 36;
+ }
+ //
+ // Create a CPU hand-off information
+ //
+ BuildCpuHob (PhysicalAddressBits, 16);
+
+ //
+ // Report Local APIC range
+ //
+ BuildMemoryMappedIoRangeHob (0xFEC80000, SIZE_512KB);
+
+ //
+ // Boot mode
+ //
+ Status = PeiServicesSetBootMode (BOOT_WITH_FULL_CONFIGURATION);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PeiServicesInstallPpi (mPpiBootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Set pcd to save the upper coreboot header in case the dxecore will
+ // erase 0~4k memory
+ //
+ pCbHeader = NULL;
+ if ((CbParseGetCbHeader (1, &pCbHeader) == RETURN_SUCCESS)
+ && ((UINTN)pCbHeader > BASE_4KB)) {
+ DEBUG((EFI_D_ERROR, "Actual Coreboot header: 0x%x.\n", (UINTN)pCbHeader));
+ PcdSet32 (PcdCbHeaderPointer, (UINT32)(UINTN)pCbHeader);
+ }
+
+ //
+ // Create guid hob for system tables like acpi table and smbios table
+ //
+ pAcpiTable = NULL;
+ AcpiTableSize = 0;
+ pSmbiosTable = NULL;
+ SmbiosTableSize = 0;
+ Status = CbParseAcpiTable (&pAcpiTable, &AcpiTableSize);
+ if (EFI_ERROR (Status)) {
+ // ACPI table is oblidgible
+ DEBUG ((EFI_D_ERROR, "Failed to find the required acpi table\n"));
+ ASSERT (FALSE);
+ }
+ CbParseSmbiosTable (&pSmbiosTable, &SmbiosTableSize);
+
+ pSystemTableInfo = NULL;
+ pSystemTableInfo = BuildGuidHob (&gUefiSystemTableInfoGuid, sizeof (SYSTEM_TABLE_INFO));
+ ASSERT (pSystemTableInfo != NULL);
+ pSystemTableInfo->AcpiTableBase = (UINT64) (UINTN)pAcpiTable;
+ pSystemTableInfo->AcpiTableSize = AcpiTableSize;
+ pSystemTableInfo->SmbiosTableBase = (UINT64) (UINTN)pSmbiosTable;
+ pSystemTableInfo->SmbiosTableSize = SmbiosTableSize;
+ DEBUG ((EFI_D_ERROR, "Detected Acpi Table at 0x%x, length 0x%x\n", (UINTN)pSystemTableInfo->AcpiTableBase, pSystemTableInfo->AcpiTableSize));
+ DEBUG ((EFI_D_ERROR, "Detected Smbios Table at 0x%x, length 0x%x\n", (UINTN)pSystemTableInfo->SmbiosTableBase, pSystemTableInfo->SmbiosTableSize));
+ DEBUG ((EFI_D_ERROR, "Create system table info guid hob\n"));
+
+ //
+ // Create guid hob for acpi board information
+ //
+ Status = CbParseFadtInfo (&PmCtrlRegBase, &PmTimerRegBase, &ResetRegAddress, &ResetValue);
+ ASSERT_EFI_ERROR (Status);
+ pAcpiBoardInfo = NULL;
+ pAcpiBoardInfo = BuildGuidHob (&gUefiAcpiBoardInfoGuid, sizeof (ACPI_BOARD_INFO));
+ ASSERT (pAcpiBoardInfo != NULL);
+ pAcpiBoardInfo->PmCtrlRegBase = (UINT64)PmCtrlRegBase;
+ pAcpiBoardInfo->PmTimerRegBase = (UINT64)PmTimerRegBase;
+ pAcpiBoardInfo->ResetRegAddress = (UINT64)ResetRegAddress;
+ pAcpiBoardInfo->ResetValue = (UINT8)ResetValue;
+ DEBUG ((EFI_D_ERROR, "Create acpi board info guid hob\n"));
+
+ //
+ // Create guid hob for frame buffer information
+ //
+ ZeroMem (&FbInfo, sizeof (FRAME_BUFFER_INFO));
+ Status = CbParseFbInfo (&FbInfo);
+ if (!EFI_ERROR (Status)) {
+ pFbInfo = BuildGuidHob (&gUefiFrameBufferInfoGuid, sizeof (FRAME_BUFFER_INFO));
+ ASSERT (pSystemTableInfo != NULL);
+ CopyMem (pFbInfo, &FbInfo, sizeof (FRAME_BUFFER_INFO));
+ DEBUG ((EFI_D_ERROR, "Create frame buffer info guid hob\n"));
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/CorebootModulePkg/CbSupportPei/CbSupportPei.h b/CorebootModulePkg/CbSupportPei/CbSupportPei.h
new file mode 100644
index 0000000000..544838523b
--- /dev/null
+++ b/CorebootModulePkg/CbSupportPei/CbSupportPei.h
@@ -0,0 +1,40 @@
+/** @file
+ The header file of Coreboot Support PEIM.
+
+Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#ifndef __PEI_COREBOOT_SUPPORT_H__
+#define __PEI_COREBOOT_SUPPORT_H__
+
+#include <PiPei.h>
+
+#include <Library/PeimEntryPoint.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/CbParseLib.h>
+#include <Library/MtrrLib.h>
+
+#include <Guid/SmramMemoryReserve.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Guid/FirmwareFileSystem2.h>
+#include <Guid/FrameBufferInfoGuid.h>
+#include <Guid/SystemTableInfoGuid.h>
+#include <Guid/AcpiBoardInfoGuid.h>
+
+#include <Ppi/MasterBootMode.h>
+
+#endif
diff --git a/CorebootModulePkg/CbSupportPei/CbSupportPei.inf b/CorebootModulePkg/CbSupportPei/CbSupportPei.inf
new file mode 100644
index 0000000000..9328151554
--- /dev/null
+++ b/CorebootModulePkg/CbSupportPei/CbSupportPei.inf
@@ -0,0 +1,72 @@
+## @file
+# Coreboot Support PEI Module
+#
+# Parses coreboot table in memory and report resource information into pei core. It will install
+# the memory as required.
+#
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = CbSupportPeim
+ FILE_GUID = 352C6AF8-315B-4bd6-B04F-31D4ED1EBE57
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ ENTRY_POINT = CbPeiEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources]
+ CbSupportPei.c
+ CbSupportPei.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelFrameworkPkg/IntelFrameworkPkg.dec
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
+ CorebootModulePkg/CorebootModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ PeimEntryPoint
+ PeiServicesLib
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ HobLib
+ PcdLib
+ CbParseLib
+ MtrrLib
+
+[Guids]
+ gEfiSmmPeiSmramMemoryReserveGuid
+ gEfiMemoryTypeInformationGuid
+ gEfiFirmwareFileSystem2Guid
+ gUefiSystemTableInfoGuid
+ gUefiFrameBufferInfoGuid
+ gUefiAcpiBoardInfoGuid
+
+[Ppis]
+ gEfiPeiMasterBootModePpiGuid
+
+[Pcd]
+ gUefiCorebootModulePkgTokenSpaceGuid.PcdPayloadFdMemBase
+ gUefiCorebootModulePkgTokenSpaceGuid.PcdPayloadFdMemSize
+ gUefiCorebootModulePkgTokenSpaceGuid.PcdCbHeaderPointer
+
+[Depex]
+ TRUE \ No newline at end of file