diff options
| author | klu2 <klu2@6f19259b-4bc3-4df7-8a09-765794883524> | 2007-12-21 08:48:38 +0000 |
|---|---|---|
| committer | klu2 <klu2@6f19259b-4bc3-4df7-8a09-765794883524> | 2007-12-21 08:48:38 +0000 |
| commit | ca162103dae16dd48474f8dfc7a8951c997c89bc (patch) | |
| tree | 4bf0dbf4127b7cf9bde9f59b4d760cf29f6ac446 /DuetPkg/DxeIpl/Ia32 | |
| parent | a09aa7e27a6206bb91ebf5035753472ff6bcb280 (diff) | |
| download | edk2-platforms-ca162103dae16dd48474f8dfc7a8951c997c89bc.tar.xz | |
Initialize DuetPkg ...
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@4416 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'DuetPkg/DxeIpl/Ia32')
| -rw-r--r-- | DuetPkg/DxeIpl/Ia32/CpuIoAccess.asm | 62 | ||||
| -rw-r--r-- | DuetPkg/DxeIpl/Ia32/EnterDxeCore.asm | 64 | ||||
| -rw-r--r-- | DuetPkg/DxeIpl/Ia32/Paging.c | 172 | ||||
| -rw-r--r-- | DuetPkg/DxeIpl/Ia32/VirtualMemory.h | 88 |
4 files changed, 386 insertions, 0 deletions
diff --git a/DuetPkg/DxeIpl/Ia32/CpuIoAccess.asm b/DuetPkg/DxeIpl/Ia32/CpuIoAccess.asm new file mode 100644 index 0000000000..00a80ef75b --- /dev/null +++ b/DuetPkg/DxeIpl/Ia32/CpuIoAccess.asm @@ -0,0 +1,62 @@ + title CpuIoAccess.asm
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation
+; All rights reserved. This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+; CpuIoAccess.asm
+;
+; Abstract:
+; CPU IO Abstraction
+;
+;------------------------------------------------------------------------------
+
+ .686
+ .MODEL FLAT,C
+ .CODE
+
+
+UINT8 TYPEDEF BYTE
+UINT16 TYPEDEF WORD
+UINT32 TYPEDEF DWORD
+UINT64 TYPEDEF QWORD
+UINTN TYPEDEF UINT32
+
+
+
+;------------------------------------------------------------------------------
+; UINT8
+; CpuIoRead8 (
+; IN UINT16 Port
+; )
+;------------------------------------------------------------------------------
+CpuIoRead8 PROC PUBLIC Port:UINT16
+ mov dx, Port
+ in al, dx
+ ret
+CpuIoRead8 ENDP
+
+
+;------------------------------------------------------------------------------
+; VOID
+; CpuIoWrite8 (
+; IN UINT16 Port,
+; IN UINT32 Data
+; )
+;------------------------------------------------------------------------------
+CpuIoWrite8 PROC PUBLIC Port:UINT16, Data:UINT32
+ mov eax, Data
+ mov dx, Port
+ out dx, al
+ ret
+CpuIoWrite8 ENDP
+
+
+END
\ No newline at end of file diff --git a/DuetPkg/DxeIpl/Ia32/EnterDxeCore.asm b/DuetPkg/DxeIpl/Ia32/EnterDxeCore.asm new file mode 100644 index 0000000000..0689a824c3 --- /dev/null +++ b/DuetPkg/DxeIpl/Ia32/EnterDxeCore.asm @@ -0,0 +1,64 @@ + TITLE EnterDxeCore.asm: Assembly code for the entering DxeCore
+;------------------------------------------------------------------------------
+;*
+;* Copyright 2006, Intel Corporation
+;* All rights reserved. This program and the accompanying materials
+;* are licensed and made available under the terms and conditions of the BSD License
+;* which accompanies this distribution. The full text of the license may be found at
+;* http://opensource.org/licenses/bsd-license.php
+;*
+;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;*
+;* EnterDxeCore.asm
+;*
+;* Abstract:
+;*
+;------------------------------------------------------------------------------
+
+.686p
+.model flat
+
+.code
+.stack
+.MMX
+.XMM
+
+;
+; VOID
+; EnterDxeMain (
+; IN VOID *StackTop,
+; IN VOID *DxeCoreEntryPoint,
+; IN VOID *Hob,
+; IN VOID *PageTable
+; )
+;
+EnterDxeMain PROC C \
+ StackTop:DWORD, \
+ DxeCoreEntryPoint:DWORD, \
+ Hob:DWORD, \
+ PageTable:DWORD
+
+ mov eax, PageTable
+; mov cr3, eax ; load page table
+; mov eax, cr4
+; bts eax, 4 ; enable CR4.PSE
+; mov cr4, eax
+; mov eax, cr0
+; bts eax, 31 ; enable CR0.PG
+; mov cr0, eax
+ mov ecx, DxeCoreEntryPoint
+ mov eax, StackTop
+ mov esp, eax
+ mov edx, Hob
+ push edx
+ push 0
+ jmp ecx
+
+; should never get here
+ jmp $
+ ret
+
+EnterDxeMain ENDP
+
+END
diff --git a/DuetPkg/DxeIpl/Ia32/Paging.c b/DuetPkg/DxeIpl/Ia32/Paging.c new file mode 100644 index 0000000000..dbc43a3080 --- /dev/null +++ b/DuetPkg/DxeIpl/Ia32/Paging.c @@ -0,0 +1,172 @@ +/*++
+
+Copyright (c) 2006 - 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+ Paging.c
+
+Abstract:
+
+Revision History:
+
+--*/
+
+#include "DxeIpl.h"
+#include "HobGeneration.h"
+#include "VirtualMemory.h"
+#include "Debug.h"
+
+#define EFI_PAGE_SIZE_4K 0x1000
+#define EFI_PAGE_SIZE_4M 0x400000
+
+//
+// Create 4G 4M-page table
+// PDE (31:22) : 1024 entries
+//
+#define EFI_MAX_ENTRY_NUM 1024
+
+#define EFI_PDE_ENTRY_NUM EFI_MAX_ENTRY_NUM
+
+#define EFI_PDE_PAGE_NUM 1
+
+#define EFI_PAGE_NUMBER_4M (EFI_PDE_PAGE_NUM)
+
+//
+// Create 4M 4K-page table
+// PTE (21:12) : 1024 entries
+//
+#define EFI_PTE_ENTRY_NUM EFI_MAX_ENTRY_NUM
+#define EFI_PTE_PAGE_NUM 1
+
+#define EFI_PAGE_NUMBER_4K (EFI_PTE_PAGE_NUM)
+
+#define EFI_PAGE_NUMBER (EFI_PAGE_NUMBER_4M + EFI_PAGE_NUMBER_4K)
+
+VOID
+EnableNullPointerProtection (
+ UINT8 *PageTable
+ )
+{
+ IA32_PAGE_TABLE_ENTRY_4K *PageTableEntry4KB;
+
+ PageTableEntry4KB = (IA32_PAGE_TABLE_ENTRY_4K *)((UINTN)PageTable + EFI_PAGE_NUMBER_4M * EFI_PAGE_SIZE_4K);
+
+ //
+ // Fill in the Page Table entries
+ // Mark 0~4K as not present
+ //
+ PageTableEntry4KB->Bits.Present = 0;
+
+ return ;
+}
+
+VOID
+Ia32Create4KPageTables (
+ UINT8 *PageTable
+ )
+{
+ UINT64 PageAddress;
+ UINTN PTEIndex;
+ IA32_PAGE_DIRECTORY_ENTRY_4K *PageDirectoryEntry4KB;
+ IA32_PAGE_TABLE_ENTRY_4K *PageTableEntry4KB;
+
+ PageAddress = 0;
+
+ //
+ // Page Table structure 2 level 4K.
+ //
+ // Page Table 4K : PageDirectoryEntry4K : bits 31-22
+ // PageTableEntry : bits 21-12
+ //
+
+ PageTableEntry4KB = (IA32_PAGE_TABLE_ENTRY_4K *)((UINTN)PageTable + EFI_PAGE_NUMBER_4M * EFI_PAGE_SIZE_4K);
+ PageDirectoryEntry4KB = (IA32_PAGE_DIRECTORY_ENTRY_4K *)((UINTN)PageTable);
+
+ PageDirectoryEntry4KB->Uint32 = (UINT32)(UINTN)PageTableEntry4KB;
+ PageDirectoryEntry4KB->Bits.ReadWrite = 0;
+ PageDirectoryEntry4KB->Bits.Present = 1;
+ PageDirectoryEntry4KB->Bits.MustBeZero = 1;
+
+ for (PTEIndex = 0; PTEIndex < EFI_PTE_ENTRY_NUM; PTEIndex++, PageTableEntry4KB++) {
+ //
+ // Fill in the Page Table entries
+ //
+ PageTableEntry4KB->Uint32 = (UINT32)PageAddress;
+ PageTableEntry4KB->Bits.ReadWrite = 1;
+ PageTableEntry4KB->Bits.Present = 1;
+
+ PageAddress += EFI_PAGE_SIZE_4K;
+ }
+
+ return ;
+}
+
+VOID
+Ia32Create4MPageTables (
+ UINT8 *PageTable
+ )
+{
+ UINT32 PageAddress;
+ UINT8 *TempPageTable;
+ UINTN PDEIndex;
+ IA32_PAGE_TABLE_ENTRY_4M *PageDirectoryEntry4MB;
+
+ TempPageTable = PageTable;
+
+ PageAddress = 0;
+
+ //
+ // Page Table structure 1 level 4MB.
+ //
+ // Page Table 4MB : PageDirectoryEntry4M : bits 31-22
+ //
+
+ PageDirectoryEntry4MB = (IA32_PAGE_TABLE_ENTRY_4M *)TempPageTable;
+
+ for (PDEIndex = 0; PDEIndex < EFI_PDE_ENTRY_NUM; PDEIndex++, PageDirectoryEntry4MB++) {
+ //
+ // Fill in the Page Directory entries
+ //
+ PageDirectoryEntry4MB->Uint32 = (UINT32)PageAddress;
+ PageDirectoryEntry4MB->Bits.ReadWrite = 1;
+ PageDirectoryEntry4MB->Bits.Present = 1;
+ PageDirectoryEntry4MB->Bits.MustBe1 = 1;
+
+ PageAddress += EFI_PAGE_SIZE_4M;
+ }
+
+ return ;
+}
+
+VOID *
+PreparePageTable (
+ VOID *PageNumberTop,
+ UINT8 SizeOfMemorySpace
+ )
+/*++
+Description:
+ Generate pagetable below PageNumberTop,
+ and return the bottom address of pagetable for putting other things later.
+--*/
+{
+ VOID *PageNumberBase;
+
+ PageNumberBase = (VOID *)((UINTN)PageNumberTop - EFI_PAGE_NUMBER * EFI_PAGE_SIZE_4K);
+ ZeroMem (PageNumberBase, EFI_PAGE_NUMBER * EFI_PAGE_SIZE_4K);
+
+ Ia32Create4MPageTables (PageNumberBase);
+ Ia32Create4KPageTables (PageNumberBase);
+ //
+ // Not enable NULL Pointer Protection if using INTX call
+ //
+// EnableNullPointerProtection (PageNumberBase);
+
+ return PageNumberBase;
+}
diff --git a/DuetPkg/DxeIpl/Ia32/VirtualMemory.h b/DuetPkg/DxeIpl/Ia32/VirtualMemory.h new file mode 100644 index 0000000000..04eab8f206 --- /dev/null +++ b/DuetPkg/DxeIpl/Ia32/VirtualMemory.h @@ -0,0 +1,88 @@ +/*++
+
+Copyright (c) 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+ VirtualMemory.h
+
+Abstract:
+
+Revision History:
+
+--*/
+
+#ifndef _VIRTUAL_MEMORY_H_
+#define _VIRTUAL_MEMORY_H_
+
+#pragma pack(1)
+
+//
+// Page Directory Entry 4K
+//
+typedef union {
+ struct {
+ UINT32 Present:1; // 0 = Not present in memory, 1 = Present in memory
+ UINT32 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
+ UINT32 UserSupervisor:1; // 0 = Supervisor, 1=User
+ UINT32 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
+ UINT32 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
+ UINT32 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
+ UINT32 MustBeZero:3; // Must Be Zero
+ UINT32 Available:3; // Available for use by system software
+ UINT32 PageTableBaseAddress:20; // Page Table Base Address
+ } Bits;
+ UINT32 Uint32;
+} IA32_PAGE_DIRECTORY_ENTRY_4K;
+
+//
+// Page Table Entry 4K
+//
+typedef union {
+ struct {
+ UINT32 Present:1; // 0 = Not present in memory, 1 = Present in memory
+ UINT32 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
+ UINT32 UserSupervisor:1; // 0 = Supervisor, 1=User
+ UINT32 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
+ UINT32 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
+ UINT32 Accessed:1; // 0 = Not accessed (cleared by software), 1 = Accessed (set by CPU)
+ UINT32 Dirty:1; // 0 = Not written to (cleared by software), 1 = Written to (set by CPU)
+ UINT32 PAT:1; // 0 = Disable PAT, 1 = Enable PAT
+ UINT32 Global:1; // Ignored
+ UINT32 Available:3; // Available for use by system software
+ UINT32 PageTableBaseAddress:20; // Page Table Base Address
+ } Bits;
+ UINT32 Uint32;
+} IA32_PAGE_TABLE_ENTRY_4K;
+
+//
+// Page Table Entry 4M
+//
+typedef union {
+ struct {
+ UINT32 Present:1; // 0 = Not present in memory, 1 = Present in memory
+ UINT32 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
+ UINT32 UserSupervisor:1; // 0 = Supervisor, 1=User
+ UINT32 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
+ UINT32 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
+ UINT32 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
+ UINT32 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
+ UINT32 MustBe1:1; // Must be 1
+ UINT32 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
+ UINT32 Available:3; // Available for use by system software
+ UINT32 PAT:1; //
+ UINT32 MustBeZero:9; // Must be zero;
+ UINT32 PageTableBaseAddress:10; // Page Table Base Address
+ } Bits;
+ UINT32 Uint32;
+} IA32_PAGE_TABLE_ENTRY_4M;
+
+#pragma pack()
+
+#endif
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