diff options
| author | qwang12 <qwang12@6f19259b-4bc3-4df7-8a09-765794883524> | 2007-06-28 07:00:39 +0000 |
|---|---|---|
| committer | qwang12 <qwang12@6f19259b-4bc3-4df7-8a09-765794883524> | 2007-06-28 07:00:39 +0000 |
| commit | 3eb9473ea9a949badfe06ae61d2d3fcfa53651c7 (patch) | |
| tree | e9d8c368dbb1e58794b2c00acefe4bbad270f8c4 /EdkCompatibilityPkg/Foundation/Include | |
| parent | 30d4a0c7ec19938196b1308006b990e0945150da (diff) | |
| download | edk2-platforms-3eb9473ea9a949badfe06ae61d2d3fcfa53651c7.tar.xz | |
Add in the 1st version of ECP.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@2832 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'EdkCompatibilityPkg/Foundation/Include')
59 files changed, 12832 insertions, 0 deletions
diff --git a/EdkCompatibilityPkg/Foundation/Include/Ebc/EfiBind.h b/EdkCompatibilityPkg/Foundation/Include/Ebc/EfiBind.h new file mode 100644 index 0000000000..930d589d0f --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/Ebc/EfiBind.h @@ -0,0 +1,129 @@ +/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ EfiBind.h
+
+Abstract:
+
+ Processor or compiler specific defines and types for EBC.
+
+--*/
+
+#ifndef _EFI_BIND_H_
+#define _EFI_BIND_H_
+
+#define EFI_DRIVER_ENTRY_POINT(InitFunction)
+#define EFI_APPLICATION_ENTRY_POINT EFI_DRIVER_ENTRY_POINT
+
+//
+// Disable warning that make it impossible to compile at /W3
+// This only works for Intel EBC Compiler tools
+//
+
+//
+// Disabling argument of type "TYPE **" is incompatible with parameter of type "void **"
+//
+#pragma warning ( disable : 167 )
+
+//
+// Disabling pointless comparison of unsigned integer with zero
+//
+#pragma warning ( disable : 186 )
+
+//
+// Disabling enumerated type mixed with another type
+//
+#pragma warning ( disable : 188 )
+
+//
+// Native integer types
+//
+typedef char int8_t;
+typedef unsigned char uint8_t;
+
+typedef short int16_t;
+typedef unsigned short uint16_t;
+
+typedef int int32_t;
+typedef unsigned int uint32_t;
+
+typedef __int64 int64_t;
+typedef unsigned __int64 uint64_t;
+
+//
+// "long" type scales to the processor native size with EBC compiler
+//
+typedef long intn_t;
+typedef unsigned long uintn_t;
+
+//
+// Scalable macro to set the most significant bit in a natural number
+//
+#define EFI_MAX_BIT ((UINTN)0x01 << ((sizeof (char *) * 8) - 1))
+#define MAX_2_BITS (EFI_MAX_BIT | (EFI_MAX_BIT >> 1))
+
+//
+// Maximum legal EBC address
+//
+#define EFI_MAX_ADDRESS (UINTN)~0
+
+//
+// Bad pointer value to use in check builds.
+// if you see this value you are using uninitialized or free'ed data
+//
+#define EFI_BAD_POINTER (UINTN)0xAFAFAFAFAFAFAFAF
+#define EFI_BAD_POINTER_AS_BYTE (UINTN)0xAF
+
+//
+// _break() is an EBC compiler intrinsic function
+//
+extern
+uint64_t
+_break (
+ unsigned char BreakCode
+ );
+
+//
+// Macro to inject a break point in the code to assist debugging.
+//
+#define EFI_BREAKPOINT() _break ( 3 )
+#define EFI_DEADLOOP() while (TRUE)
+
+//
+// Memory Fence forces serialization, and is needed to support out of order
+// memory transactions. The Memory Fence is mainly used to make sure IO
+// transactions complete in a deterministic sequence, and to syncronize locks
+// an other MP code. Currently no memory fencing is required.
+//
+#define MEMORY_FENCE()
+
+//
+// Some compilers don't support the forward reference construct:
+// typedef struct XXXXX. The forward reference is required for
+// ANSI compatibility.
+//
+// The following macro provide a workaround for such cases.
+//
+
+
+#ifdef EFI_NO_INTERFACE_DECL
+ #define EFI_FORWARD_DECLARATION(x)
+#else
+ #define EFI_FORWARD_DECLARATION(x) typedef struct _##x x
+#endif
+
+
+#define _EFIAPI
+
+#endif // ifndef _EFI_BIND_H_
+
diff --git a/EdkCompatibilityPkg/Foundation/Include/Ebc/EfiPeOptionalHeader.h b/EdkCompatibilityPkg/Foundation/Include/Ebc/EfiPeOptionalHeader.h new file mode 100644 index 0000000000..0dd66c2789 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/Ebc/EfiPeOptionalHeader.h @@ -0,0 +1,46 @@ +/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ EfiPeOptionalHeader.h
+
+Abstract:
+ Defines the optional header in the PE image per the PE specification. This
+ file must be included only from within EfiImage.h since
+ EFI_IMAGE_DATA_DIRECTORY and EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES are defined
+ there.
+
+--*/
+
+#ifndef _EFI_PE_OPTIONAL_HEADER_H_
+#define _EFI_PE_OPTIONAL_HEADER_H_
+
+//
+// This is just to make sure you can cross compile with the EBC compiiler.
+// It does not make sense to have a PE loader coded in EBC. You need to
+// understand the basic
+//
+#define EFI_IMAGE_MACHINE_TYPE (EFI_IMAGE_MACHINE_EBC)
+
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_EBC)
+
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
+
+//
+// BUGBUG: Is this the correct magic for EBC?
+//
+#define EFI_IMAGE_NT_OPTIONAL_HDR_MAGIC EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC
+
+typedef EFI_IMAGE_OPTIONAL_HEADER32 EFI_IMAGE_OPTIONAL_HEADER;
+typedef EFI_IMAGE_NT_HEADERS32 EFI_IMAGE_NT_HEADERS;
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/Ebc/TianoBind.h b/EdkCompatibilityPkg/Foundation/Include/Ebc/TianoBind.h new file mode 100644 index 0000000000..027d2478af --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/Ebc/TianoBind.h @@ -0,0 +1,30 @@ +/*++
+
+Copyright (c) 2004, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ TianoBind.h
+
+Abstract:
+
+ Tiano's Processor or Compiler specific defines and types for EBC
+ besides EfiBind.h.
+
+--*/
+
+#ifndef _TIANO_BIND_H_
+#define _TIANO_BIND_H_
+
+#include "EfiBind.h"
+
+#define EFI_DXE_ENTRY_POINT(InitFunction)
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/EfiCommon.h b/EdkCompatibilityPkg/Foundation/Include/EfiCommon.h new file mode 100644 index 0000000000..305bfeaf8a --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/EfiCommon.h @@ -0,0 +1,53 @@ +/*++
+
+Copyright (c) 2004, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ EfiCommon.h
+
+Abstract:
+
+--*/
+
+#ifndef _EFI_COMMON_H_
+#define _EFI_COMMON_H_
+
+#include "EfiBind.h"
+#include "EfiTypes.h"
+#include "EfiStdArg.h"
+#include "EfiError.h"
+
+//
+// Define macros for including Protocols and Guids.
+//
+#define EFI_STRINGIZE(a) #a
+#define EFI_PROTOCOL_DEFINITION(a) EFI_STRINGIZE (Protocol/a/a.h)
+#define EFI_GUID_DEFINITION(a) EFI_STRINGIZE (Guid/a/a.h)
+
+//
+// These should be used to include protocols. If they are followed,
+// intelligent build tools can be created to check dependencies at build
+// time.
+//
+#define EFI_PROTOCOL_PRODUCER(a) EFI_PROTOCOL_DEFINITION (a)
+#define EFI_PROTOCOL_CONSUMER(a) EFI_PROTOCOL_DEFINITION (a)
+#define EFI_PROTOCOL_DEPENDENCY(a) EFI_PROTOCOL_DEFINITION (a)
+
+//
+// Mechanism to associate a short and long ascii string with a GUID.
+// For normal builds the strings are not included. A build utility
+// can be constructed to extract the strings and build a table. It may
+// be possible to add a build opption to automatically generate a GUID
+// string table for a GUID to string utility build.
+//
+#define EFI_GUID_STRING(guidpointer, shortstring, longstring)
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/EfiDebug.h b/EdkCompatibilityPkg/Foundation/Include/EfiDebug.h new file mode 100644 index 0000000000..452fd028c0 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/EfiDebug.h @@ -0,0 +1,170 @@ +/*++
+
+Copyright (c) 2004, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ EfiDebug.h
+
+Abstract:
+
+ EFI Debug macros. The work needs tobe done in library. The Debug
+ macros them selves are standard for all files, including the core.
+
+ There needs to be code linked in that produces the following macros:
+
+ EfiDebugAssert(file, linenumber, assertion string) - worker function for
+ ASSERT. filename and line number of where this ASSERT() is located
+ is passed in along with the stringized version of the assertion.
+
+ EfiDebugPrint - Worker function for debug print
+
+ _DEBUG_SET_MEM(address, length, value) - Set memory at address to value
+ for legnth bytes. This macro is used to initialzed uninitialized memory
+ or memory that is free'ed, so it will not be used by mistake.
+
+--*/
+
+#ifndef _EFI_DEBUG_H_
+#define _EFI_DEBUG_H_
+
+#ifdef EFI_DEBUG
+
+ VOID
+ EfiDebugAssert (
+ IN CHAR8 *FileName,
+ IN INTN LineNumber,
+ IN CHAR8 *Description
+ );
+
+ VOID
+ EfiDebugPrint (
+ IN UINTN ErrorLevel,
+ IN CHAR8 *Format,
+ ...
+ );
+
+ VOID
+ EfiDebugVPrint (
+ IN UINTN ErrorLevel,
+ IN CHAR8 *Format,
+ IN VA_LIST Marker
+ );
+
+ //
+ // Define macros for the above functions so we can make them go away
+ // in non-debug builds.
+ //
+ #define EFI_DEBUG_VPRINT(ErrorLevel, Format, Marker) \
+ EfiDebugVPrint(ErrorLevel, Format, Marker)
+
+ #define EFI_DEBUG_ASSERT(FileName, LineNumber, Description) \
+ EfiDebugAssert (FileName, LineNumber, Description)
+
+ #define _DEBUG_ASSERT(assertion) \
+ EfiDebugAssert (__FILE__, __LINE__, #assertion)
+
+ #define _DEBUG(arg) DebugPrint arg
+
+ //
+ // Define ASSERT() macro, if assertion is FALSE trigger the ASSERT
+ //
+ #define ASSERT(assertion) if(!(assertion)) \
+ _DEBUG_ASSERT(assertion)
+
+ #define ASSERT_LOCKED(l) if(!(l)->Lock) _DEBUG_ASSERT(l not locked)
+
+ //
+ // DEBUG((DebugLevel, "format string", ...)) - if DebugLevel is active do
+ // the a debug print.
+ //
+ #define DEBUG(arg) EfiDebugPrint arg
+
+ #define DEBUG_CODE(code) code
+
+ #define CR(record, TYPE, field, signature) \
+ _CR(record, TYPE, field)->Signature != signature ? \
+ (TYPE *) (_DEBUG_ASSERT("CR has Bad Signature"), record) : \
+ _CR(record, TYPE, field)
+
+ #define _DEBUG_SET_MEM(address, length, data) EfiCommonLibSetMem(address, length, data)
+
+ //
+ // Generate an ASSERT if the protocol specified by GUID is already installed on Handle.
+ // If Handle is NULL, then an ASSERT is generated if the protocol specified by GUID
+ // is present anywhere in the handle database
+ //
+ #define ASSERT_PROTOCOL_ALREADY_INSTALLED(Handle, Guid) \
+ DEBUG_CODE ( { \
+ VOID *Instance; \
+ if (Handle == NULL) { \
+ ASSERT(EFI_ERROR(gBS->LocateProtocol (Guid, NULL, &Instance))); \
+ } else { \
+ ASSERT(EFI_ERROR(gBS->HandleProtocol (Handle, Guid, &Instance))); \
+ } } )
+
+#else
+ #define ASSERT(a)
+ #define ASSERT_LOCKED(l)
+ #define DEBUG(arg)
+ #define DEBUG_CODE(code)
+ #define CR(Record, TYPE, Field, Signature) \
+ _CR(Record, TYPE, Field)
+ #define _DEBUG_SET_MEM(address, length, data)
+ #define EFI_DEBUG_VPRINT(ErrorLevel, Format, Marker)
+ #define EFI_DEBUG_ASSERT(FileName, LineNumber, Description)
+ #define ASSERT_PROTOCOL_ALREADY_INSTALLED(Handle, Guid)
+#endif
+
+//
+// Generate an ASSERT if Status is an error code
+//
+//#define ASSERT_EFI_ERROR(status) ASSERT(!EFI_ERROR(status))
+#define ASSERT_EFI_ERROR(status) if (EFI_ERROR(status)) \
+ DEBUG_CODE ( { \
+ DEBUG((EFI_D_ERROR, "\nASSERT!Status = 0x%x Info :",status)); \
+ ASSERT(!EFI_ERROR(status)); \
+ } )
+
+#ifdef EFI_DEBUG_CLEAR_MEMORY
+ #define DEBUG_SET_MEMORY(address,length) \
+ _DEBUG_SET_MEM(address, length, EFI_BAD_POINTER_AS_BYTE)
+#else
+ #define DEBUG_SET_MEMORY(address,length)
+#endif
+
+#define EFI_D_INIT 0x00000001 // Initialization style messages
+#define EFI_D_WARN 0x00000002 // Warnings
+#define EFI_D_LOAD 0x00000004 // Load events
+#define EFI_D_FS 0x00000008 // EFI File system
+#define EFI_D_POOL 0x00000010 // Alloc & Free's
+#define EFI_D_PAGE 0x00000020 // Alloc & Free's
+#define EFI_D_INFO 0x00000040 // Verbose
+#define EFI_D_VARIABLE 0x00000100 // Variable
+#define EFI_D_BM 0x00000400 // Boot Manager (BDS)
+#define EFI_D_BLKIO 0x00001000 // BlkIo Driver
+#define EFI_D_NET 0x00004000 // SNI Driver
+#define EFI_D_UNDI 0x00010000 // UNDI Driver
+#define EFI_D_LOADFILE 0x00020000 // UNDI Driver
+#define EFI_D_EVENT 0x00080000 // Event messages
+
+#define EFI_D_ERROR 0x80000000 // Error
+
+#define EFI_D_GENERIC (EFI_D_ERROR | EFI_D_INIT | EFI_D_WARN | EFI_D_INFO | \
+ EFI_D_BLKIO | EFI_D_NET | EFI_D_UNDI )
+
+#define EFI_D_INTRINSIC ( EFI_D_EVENT | EFI_D_POOL | EFI_D_PAGE | \
+ EFI_D_BM | EFI_D_LOAD | EFI_D_VARIABLE )
+
+#define EFI_D_RESERVED (EFI_D_GENERIC | EFI_D_INTRINSIC)
+
+#define EFI_DBUG_MASK (EFI_D_ERROR)
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/EfiDepex.h b/EdkCompatibilityPkg/Foundation/Include/EfiDepex.h new file mode 100644 index 0000000000..62a77848d1 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/EfiDepex.h @@ -0,0 +1,54 @@ +/*++
+
+Copyright (c) 2004, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+ EfiDepex.h
+
+Abstract:
+ This include file is only used in *.DXS files. Do not use this
+ include file in normal DXE code.
+
+ Depex - Dependency Expresion
+
+ The BNF grammar is thus:
+ <depex> ::= before GUID
+ | after GUID
+ | SOR <bool>
+ | <bool>
+ <bool> ::= <bool> and <term>
+ | <bool> or <term>
+ | <term>
+ <term> ::= not <factor>
+ | <factor>
+ <factor> ::= <bool>
+ | <boolval>
+ | <depinst>
+ | <termval>
+ <boolval> ::= true
+ | false
+ <depinst> ::= push GUID
+ <termval> ::= end
+
+--*/
+
+#ifndef _EFI_DEPEX_H_
+#define _EFI_DEPEX_H_
+
+#include "Tiano.h"
+
+//
+// The Depex grammer needs the string "TRUE" and "FALSE" we must
+// undo any pre-processor redefinitions
+//
+#undef TRUE
+#undef FALSE
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/EfiFlashMap.h b/EdkCompatibilityPkg/Foundation/Include/EfiFlashMap.h new file mode 100644 index 0000000000..9b0af35dd4 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/EfiFlashMap.h @@ -0,0 +1,128 @@ +/*++
+
+Copyright (c) 2004 - 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ EfiFlashMap.h
+
+Abstract:
+
+ Defines for the EFI Flash Map functionality
+
+--*/
+
+#ifndef _EFI_FLASHMAP_H_
+#define _EFI_FLASHMAP_H_
+
+#include "PeiHob.h"
+
+//
+// Definition for flash map GUIDed HOBs
+//
+typedef UINT32 EFI_FLASH_AREA_ATTRIBUTES;
+
+#define EFI_FLASH_AREA_FV 0x0001
+#define EFI_FLASH_AREA_SUBFV 0x0002
+#define EFI_FLASH_AREA_MEMMAPPED_FV 0x0004
+#define EFI_FLASH_AREA_REQUIRED 0x0008
+#define EFI_FLASH_AREA_CORRUPT 0x0010
+
+typedef UINT8 EFI_FLASH_AREA_TYPE;
+
+#define EFI_FLASH_AREA_RECOVERY_BIOS 0x0 // Recovery code
+#define EFI_FLASH_AREA_MAIN_BIOS 0x1 // Regular BIOS code
+#define EFI_FLASH_AREA_PAL_B 0x2 // PAL-B
+#define EFI_FLASH_AREA_RESERVED_03 0x3 // Reserved for backwards compatibility
+#define EFI_FLASH_AREA_RESERVED_04 0x4 // Reserved for backwards compatibility
+#define EFI_FLASH_AREA_DMI_FRU 0x5 // DMI FRU information
+#define EFI_FLASH_AREA_OEM_BINARY 0x6 // OEM Binary Code/data
+#define EFI_FLASH_AREA_RESERVED_07 0x7 // Reserved for backwards compatibility
+#define EFI_FLASH_AREA_RESERVED_08 0x8 // Reserved for backwards compatibility
+#define EFI_FLASH_AREA_RESERVED_09 0x9 // Reserved for backwards compatibility
+#define EFI_FLASH_AREA_RESERVED_0A 0x0a // Reserved for backwards compatibility
+#define EFI_FLASH_AREA_EFI_VARIABLES 0x0b // EFI variables
+#define EFI_FLASH_AREA_MCA_LOG 0x0c // MCA error log
+#define EFI_FLASH_AREA_SMBIOS_LOG 0x0d // SMBIOS error log
+#define EFI_FLASH_AREA_FTW_BACKUP 0x0e // A backup block during FTW operations
+#define EFI_FLASH_AREA_FTW_STATE 0x0f // State information during FTW operations
+#define EFI_FLASH_AREA_UNUSED 0x0fd // Not used
+#define EFI_FLASH_AREA_GUID_DEFINED 0x0fe // Usage defined by a GUID
+#pragma pack(1)
+//
+// An individual sub-area Entry.
+// A single flash area may consist of more than one sub-area.
+//
+typedef struct {
+ EFI_FLASH_AREA_ATTRIBUTES Attributes;
+ UINT32 Reserved;
+ EFI_PHYSICAL_ADDRESS Base;
+ EFI_PHYSICAL_ADDRESS Length;
+ EFI_GUID FileSystem;
+} EFI_FLASH_SUBAREA_ENTRY;
+
+typedef struct {
+ UINT8 Reserved[3];
+ EFI_FLASH_AREA_TYPE AreaType;
+ EFI_GUID AreaTypeGuid;
+ UINT32 NumEntries;
+ EFI_FLASH_SUBAREA_ENTRY Entries[1];
+} EFI_FLASH_MAP_ENTRY_DATA;
+
+typedef struct {
+ UINT8 Reserved[3];
+ EFI_FLASH_AREA_TYPE AreaType;
+ EFI_GUID AreaTypeGuid;
+ UINT32 NumberOfEntries;
+ EFI_FLASH_SUBAREA_ENTRY Entries[1];
+ //
+ // Extended Hob data.
+ //
+ // VolumeId and FilePath indicating a unique file.
+ //
+ UINT32 VolumeId;
+ CHAR16 FilePath[256];
+ UINT32 ActuralSize;
+ UINT32 Offset;
+} EFI_FLASH_MAP_FS_ENTRY_DATA;
+
+typedef struct {
+ EFI_HOB_GENERIC_HEADER Header;
+ EFI_GUID Name;
+ UINT8 Reserved[3];
+ EFI_FLASH_AREA_TYPE AreaType;
+ EFI_GUID AreaTypeGuid;
+ UINT32 NumEntries;
+ EFI_FLASH_SUBAREA_ENTRY Entries[1];
+} EFI_HOB_FLASH_MAP_ENTRY_TYPE;
+
+//
+// Internal definitions
+//
+typedef struct {
+ UINT8 Reserved[3];
+ EFI_FLASH_AREA_TYPE AreaType;
+ EFI_GUID AreaTypeGuid;
+ UINT32 NumberOfEntries;
+ EFI_FLASH_SUBAREA_ENTRY SubAreaData;
+} EFI_FLASH_AREA_HOB_DATA;
+
+typedef struct {
+ UINTN Base;
+ UINTN Length;
+ EFI_FLASH_AREA_ATTRIBUTES Attributes;
+ EFI_FLASH_AREA_TYPE AreaType;
+ UINT8 Reserved[3];
+ EFI_GUID AreaTypeGuid;
+} EFI_FLASH_AREA_DATA;
+
+#pragma pack()
+
+#endif // #ifndef _EFI_FLASHMAP_H_
diff --git a/EdkCompatibilityPkg/Foundation/Include/EfiPci.h b/EdkCompatibilityPkg/Foundation/Include/EfiPci.h new file mode 100644 index 0000000000..32014095e7 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/EfiPci.h @@ -0,0 +1,64 @@ +/*++
+
+Copyright (c) 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ EfiPci.h
+
+Abstract:
+ Support for EFI PCI specification.
+
+Revision History
+
+--*/
+
+#ifndef _EFI_PCI_H_
+#define _EFI_PCI_H_
+
+//#include "pci22.h"
+//#include "pci23.h"
+//#include "pci30.h"
+
+#pragma pack(push, 1)
+
+typedef struct {
+ UINT8 Register;
+ UINT8 Function;
+ UINT8 Device;
+ UINT8 Bus;
+ UINT8 Reserved[4];
+} DEFIO_PCI_ADDR;
+
+#define EFI_ROOT_BRIDGE_LIST 'eprb'
+#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1
+
+typedef struct {
+ UINT16 Signature; // 0xaa55
+ UINT16 InitializationSize;
+ UINT32 EfiSignature; // 0x0EF1
+ UINT16 EfiSubsystem;
+ UINT16 EfiMachineType;
+ UINT16 CompressionType;
+ UINT8 Reserved[8];
+ UINT16 EfiImageHeaderOffset;
+ UINT16 PcirOffset;
+} EFI_PCI_EXPANSION_ROM_HEADER;
+
+typedef union {
+ UINT8 *Raw;
+ PCI_EXPANSION_ROM_HEADER *Generic;
+ EFI_PCI_EXPANSION_ROM_HEADER *Efi;
+ EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;
+} EFI_PCI_ROM_HEADER;
+
+#pragma pack(pop)
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/EfiPerf.h b/EdkCompatibilityPkg/Foundation/Include/EfiPerf.h new file mode 100644 index 0000000000..55c743f7a7 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/EfiPerf.h @@ -0,0 +1,158 @@ +/*++
+
+Copyright (c) 2004, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ EfiPerf.h
+
+Abstract:
+ EfiPerf.h provides performance primitive for the DXE and Shell phase
+
+
+--*/
+
+#ifndef _EFI_PERF_H_
+#define _EFI_PERF_H_
+
+#include EFI_PROTOCOL_DEFINITION (Performance)
+
+EFI_STATUS
+InitializePerformanceInfrastructure (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable,
+ IN UINT64 Ticker
+ )
+/*++
+
+Routine Description:
+
+ TODO: Add function description
+
+Arguments:
+
+ ImageHandle - TODO: add argument description
+ SystemTable - TODO: add argument description
+ Ticker - TODO: add argument description
+
+Returns:
+
+ TODO: add return values
+
+--*/
+;
+
+EFI_STATUS
+EndMeasure (
+ IN EFI_HANDLE Handle,
+ IN UINT16 *Token,
+ IN UINT16 *Host,
+ IN UINT64 Ticker
+ )
+/*++
+
+Routine Description:
+
+ TODO: Add function description
+
+Arguments:
+
+ Handle - TODO: add argument description
+ Token - TODO: add argument description
+ Host - TODO: add argument description
+ Ticker - TODO: add argument description
+
+Returns:
+
+ TODO: add return values
+
+--*/
+;
+
+EFI_STATUS
+StartMeasure (
+ IN EFI_HANDLE Handle,
+ IN UINT16 *Token,
+ IN UINT16 *Host,
+ IN UINT64 Ticker
+ )
+/*++
+
+Routine Description:
+
+ TODO: Add function description
+
+Arguments:
+
+ Handle - TODO: add argument description
+ Token - TODO: add argument description
+ Host - TODO: add argument description
+ Ticker - TODO: add argument description
+
+Returns:
+
+ TODO: add return values
+
+--*/
+;
+
+EFI_STATUS
+UpdateMeasure (
+ IN EFI_HANDLE Handle,
+ IN UINT16 *Token,
+ IN UINT16 *Host,
+ IN EFI_HANDLE HandleNew,
+ IN UINT16 *TokenNew,
+ IN UINT16 *HostNew
+ )
+/*++
+
+Routine Description:
+
+ TODO: Add function description
+
+Arguments:
+
+ Handle - TODO: add argument description
+ Token - TODO: add argument description
+ Host - TODO: add argument description
+ HandleNew - TODO: add argument description
+ TokenNew - TODO: add argument description
+ HostNew - TODO: add argument description
+
+Returns:
+
+ TODO: add return values
+
+--*/
+;
+
+#ifdef EFI_DXE_PERFORMANCE
+#define PERF_ENABLE(handle, table, ticker) InitializePerformanceInfrastructure (handle, table, ticker)
+#define PERF_START(handle, token, host, ticker) StartMeasure (handle, token, host, ticker)
+#define PERF_END(handle, token, host, ticker) EndMeasure (handle, token, host, ticker)
+#define PERF_UPDATE(handle, token, host, handlenew, tokennew, hostnew) \
+ UpdateMeasure (handle, \
+ token, \
+ host, \
+ handlenew, \
+ tokennew, \
+ hostnew \
+ )
+#define PERF_CODE(code) code
+#else
+#define PERF_ENABLE(handle, table, ticker)
+#define PERF_START(handle, token, host, ticker)
+#define PERF_END(handle, token, host, ticker)
+#define PERF_UPDATE(handle, token, host, handlenew, tokennew, hostnew)
+#define PERF_CODE(code)
+#endif
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/EfiPxe.h b/EdkCompatibilityPkg/Foundation/Include/EfiPxe.h new file mode 100644 index 0000000000..0ff2252469 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/EfiPxe.h @@ -0,0 +1,1816 @@ +/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module name:
+
+ EfiPxe.h
+
+32/64-bit PXE specification:
+
+ alpha-4, 99-Dec-17
+
+Abstract:
+
+ This header file contains all of the PXE type definitions,
+ structure prototypes, global variables and constants that
+ are needed for porting PXE to EFI.
+--*/
+
+#ifndef _EFIPXE_H
+#define _EFIPXE_H
+
+#pragma pack(1)
+
+#define PXE_INTEL_ORDER 1 // Intel order
+// #define PXE_NETWORK_ORDER 1 // network order
+//
+#define PXE_UINT64_SUPPORT 1 // UINT64 supported
+// #define PXE_NO_UINT64_SUPPORT 1 // UINT64 not supported
+//
+#define PXE_BUSTYPE(a, b, c, d) \
+ ( \
+ (((UINT32) (d) & 0xFF) << 24) | (((UINT32) (c) & 0xFF) << 16) | (((UINT32) (b) & 0xFF) << 8) | \
+ ((UINT32) (a) & 0xFF) \
+ )
+
+//
+// UNDI ROM ID and devive ID signature
+//
+#define PXE_BUSTYPE_PXE PXE_BUSTYPE ('!', 'P', 'X', 'E')
+
+//
+// BUS ROM ID signatures
+//
+#define PXE_BUSTYPE_PCI PXE_BUSTYPE ('P', 'C', 'I', 'R')
+#define PXE_BUSTYPE_PC_CARD PXE_BUSTYPE ('P', 'C', 'C', 'R')
+#define PXE_BUSTYPE_USB PXE_BUSTYPE ('U', 'S', 'B', 'R')
+#define PXE_BUSTYPE_1394 PXE_BUSTYPE ('1', '3', '9', '4')
+
+#define PXE_SWAP_UINT16(n) ((((UINT16) (n) & 0x00FF) << 8) | (((UINT16) (n) & 0xFF00) >> 8))
+
+#define PXE_SWAP_UINT32(n) \
+((((UINT32)(n) & 0x000000FF) << 24) | \
+(((UINT32)(n) & 0x0000FF00) << 8) | \
+(((UINT32)(n) & 0x00FF0000) >> 8) | \
+(((UINT32)(n) & 0xFF000000) >> 24))
+
+#if PXE_UINT64_SUPPORT != 0
+#define PXE_SWAP_UINT64(n) \
+((((UINT64)(n) & 0x00000000000000FF) << 56) | \
+(((UINT64)(n) & 0x000000000000FF00) << 40) | \
+(((UINT64)(n) & 0x0000000000FF0000) << 24) | \
+(((UINT64)(n) & 0x00000000FF000000) << 8) | \
+(((UINT64)(n) & 0x000000FF00000000) >> 8) | \
+(((UINT64)(n) & 0x0000FF0000000000) >> 24) | \
+(((UINT64)(n) & 0x00FF000000000000) >> 40) | \
+(((UINT64)(n) & 0xFF00000000000000) >> 56))
+#endif // PXE_UINT64_SUPPORT
+#if PXE_NO_UINT64_SUPPORT != 0
+#define PXE_SWAP_UINT64(n) { \
+ UINT32 tmp; \
+ tmp = (PXE_UINT64) (n)[1]; \
+ (UINT64) (n)[1] = PXE_SWAP_UINT32 ((UINT64) (n)[0]); \
+ (UINT64) (n)[0] = tmp; \
+ }
+#endif // PXE_NO_UINT64_SUPPORT
+#define PXE_CPBSIZE_NOT_USED 0 // zero
+#define PXE_DBSIZE_NOT_USED 0 // zero
+#define PXE_CPBADDR_NOT_USED (PXE_UINT64) 0 // zero
+#define PXE_DBADDR_NOT_USED (PXE_UINT64) 0 // zero
+#define PXE_CONST const
+
+#define PXE_VOLATILE volatile
+
+#if PXE_UINT64_SUPPORT != 0
+//
+// typedef unsigned long PXE_UINT64;
+//
+typedef UINT64 PXE_UINT64;
+#endif // PXE_UINT64_SUPPORT
+#if PXE_NO_UINT64_SUPPORT != 0
+typedef PXE_UINT32 PXE_UINT64[2];
+#endif // PXE_NO_UINT64_SUPPORT
+#define PXE_FALSE 0 // zero
+#define PXE_TRUE (!PXE_FALSE)
+
+typedef UINT16 PXE_OPCODE;
+
+//
+// Return UNDI operational state.
+//
+#define PXE_OPCODE_GET_STATE 0x0000
+
+//
+// Change UNDI operational state from Stopped to Started.
+//
+#define PXE_OPCODE_START 0x0001
+
+//
+// Change UNDI operational state from Started to Stopped.
+//
+#define PXE_OPCODE_STOP 0x0002
+
+//
+// Get UNDI initialization information.
+//
+#define PXE_OPCODE_GET_INIT_INFO 0x0003
+
+//
+// Get NIC configuration information.
+//
+#define PXE_OPCODE_GET_CONFIG_INFO 0x0004
+
+//
+// Changed UNDI operational state from Started to Initialized.
+//
+#define PXE_OPCODE_INITIALIZE 0x0005
+
+//
+// Re-initialize the NIC H/W.
+//
+#define PXE_OPCODE_RESET 0x0006
+
+//
+// Change the UNDI operational state from Initialized to Started.
+//
+#define PXE_OPCODE_SHUTDOWN 0x0007
+
+//
+// Read & change state of external interrupt enables.
+//
+#define PXE_OPCODE_INTERRUPT_ENABLES 0x0008
+
+//
+// Read & change state of packet receive filters.
+//
+#define PXE_OPCODE_RECEIVE_FILTERS 0x0009
+
+//
+// Read & change station MAC address.
+//
+#define PXE_OPCODE_STATION_ADDRESS 0x000A
+
+//
+// Read traffic statistics.
+//
+#define PXE_OPCODE_STATISTICS 0x000B
+
+//
+// Convert multicast IP address to multicast MAC address.
+//
+#define PXE_OPCODE_MCAST_IP_TO_MAC 0x000C
+
+//
+// Read or change non-volatile storage on the NIC.
+//
+#define PXE_OPCODE_NVDATA 0x000D
+
+//
+// Get & clear interrupt status.
+//
+#define PXE_OPCODE_GET_STATUS 0x000E
+
+//
+// Fill media header in packet for transmit.
+//
+#define PXE_OPCODE_FILL_HEADER 0x000F
+
+//
+// Transmit packet(s).
+//
+#define PXE_OPCODE_TRANSMIT 0x0010
+
+//
+// Receive packet.
+//
+#define PXE_OPCODE_RECEIVE 0x0011
+
+//
+// last valid opcode:
+//
+#define PXE_OPCODE_VALID_MAX 0x0011
+
+//
+// Last valid PXE UNDI OpCode number.
+//
+#define PXE_OPCODE_LAST_VALID 0x0011
+
+typedef UINT16 PXE_OPFLAGS;
+
+#define PXE_OPFLAGS_NOT_USED 0x0000
+
+//
+// //////////////////////////////////////
+// UNDI Get State
+//
+// No OpFlags
+
+////////////////////////////////////////
+// UNDI Start
+//
+// No OpFlags
+
+////////////////////////////////////////
+// UNDI Stop
+//
+// No OpFlags
+
+////////////////////////////////////////
+// UNDI Get Init Info
+//
+// No Opflags
+
+////////////////////////////////////////
+// UNDI Get Config Info
+//
+// No Opflags
+
+////////////////////////////////////////
+// UNDI Initialize
+//
+#define PXE_OPFLAGS_INITIALIZE_CABLE_DETECT_MASK 0x0001
+#define PXE_OPFLAGS_INITIALIZE_DETECT_CABLE 0x0000
+#define PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE 0x0001
+
+//
+// //////////////////////////////////////
+// UNDI Reset
+//
+#define PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS 0x0001
+#define PXE_OPFLAGS_RESET_DISABLE_FILTERS 0x0002
+
+//
+// //////////////////////////////////////
+// UNDI Shutdown
+//
+// No OpFlags
+
+////////////////////////////////////////
+// UNDI Interrupt Enables
+//
+//
+// Select whether to enable or disable external interrupt signals.
+// Setting both enable and disable will return PXE_STATCODE_INVALID_OPFLAGS.
+//
+#define PXE_OPFLAGS_INTERRUPT_OPMASK 0xC000
+#define PXE_OPFLAGS_INTERRUPT_ENABLE 0x8000
+#define PXE_OPFLAGS_INTERRUPT_DISABLE 0x4000
+#define PXE_OPFLAGS_INTERRUPT_READ 0x0000
+
+//
+// Enable receive interrupts. An external interrupt will be generated
+// after a complete non-error packet has been received.
+//
+#define PXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001
+
+//
+// Enable transmit interrupts. An external interrupt will be generated
+// after a complete non-error packet has been transmitted.
+//
+#define PXE_OPFLAGS_INTERRUPT_TRANSMIT 0x0002
+
+//
+// Enable command interrupts. An external interrupt will be generated
+// when command execution stops.
+//
+#define PXE_OPFLAGS_INTERRUPT_COMMAND 0x0004
+
+//
+// Generate software interrupt. Setting this bit generates an external
+// interrupt, if it is supported by the hardware.
+//
+#define PXE_OPFLAGS_INTERRUPT_SOFTWARE 0x0008
+
+//
+// //////////////////////////////////////
+// UNDI Receive Filters
+//
+//
+// Select whether to enable or disable receive filters.
+// Setting both enable and disable will return PXE_STATCODE_INVALID_OPCODE.
+//
+#define PXE_OPFLAGS_RECEIVE_FILTER_OPMASK 0xC000
+#define PXE_OPFLAGS_RECEIVE_FILTER_ENABLE 0x8000
+#define PXE_OPFLAGS_RECEIVE_FILTER_DISABLE 0x4000
+#define PXE_OPFLAGS_RECEIVE_FILTER_READ 0x0000
+
+//
+// To reset the contents of the multicast MAC address filter list,
+// set this OpFlag:
+//
+#define PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST 0x2000
+
+//
+// Enable unicast packet receiving. Packets sent to the current station
+// MAC address will be received.
+//
+#define PXE_OPFLAGS_RECEIVE_FILTER_UNICAST 0x0001
+
+//
+// Enable broadcast packet receiving. Packets sent to the broadcast
+// MAC address will be received.
+//
+#define PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST 0x0002
+
+//
+// Enable filtered multicast packet receiving. Packets sent to any
+// of the multicast MAC addresses in the multicast MAC address filter
+// list will be received. If the filter list is empty, no multicast
+//
+#define PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
+
+//
+// Enable promiscuous packet receiving. All packets will be received.
+//
+#define PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008
+
+//
+// Enable promiscuous multicast packet receiving. All multicast
+// packets will be received.
+//
+#define PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010
+
+//
+// //////////////////////////////////////
+// UNDI Station Address
+//
+#define PXE_OPFLAGS_STATION_ADDRESS_READ 0x0000
+#define PXE_OPFLAGS_STATION_ADDRESS_WRITE 0x0000
+#define PXE_OPFLAGS_STATION_ADDRESS_RESET 0x0001
+
+//
+// //////////////////////////////////////
+// UNDI Statistics
+//
+#define PXE_OPFLAGS_STATISTICS_READ 0x0000
+#define PXE_OPFLAGS_STATISTICS_RESET 0x0001
+
+//
+// //////////////////////////////////////
+// UNDI MCast IP to MAC
+//
+//
+// Identify the type of IP address in the CPB.
+//
+#define PXE_OPFLAGS_MCAST_IP_TO_MAC_OPMASK 0x0003
+#define PXE_OPFLAGS_MCAST_IPV4_TO_MAC 0x0000
+#define PXE_OPFLAGS_MCAST_IPV6_TO_MAC 0x0001
+
+//
+// //////////////////////////////////////
+// UNDI NvData
+//
+//
+// Select the type of non-volatile data operation.
+//
+#define PXE_OPFLAGS_NVDATA_OPMASK 0x0001
+#define PXE_OPFLAGS_NVDATA_READ 0x0000
+#define PXE_OPFLAGS_NVDATA_WRITE 0x0001
+
+//
+// //////////////////////////////////////
+// UNDI Get Status
+//
+//
+// Return current interrupt status. This will also clear any interrupts
+// that are currently set. This can be used in a polling routine. The
+// interrupt flags are still set and cleared even when the interrupts
+// are disabled.
+//
+#define PXE_OPFLAGS_GET_INTERRUPT_STATUS 0x0001
+
+//
+// Return list of transmitted buffers for recycling. Transmit buffers
+// must not be changed or unallocated until they have recycled. After
+// issuing a transmit command, wait for a transmit complete interrupt.
+// When a transmit complete interrupt is received, read the transmitted
+// buffers. Do not plan on getting one buffer per interrupt. Some
+// NICs and UNDIs may transmit multiple buffers per interrupt.
+//
+#define PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS 0x0002
+
+//
+// //////////////////////////////////////
+// UNDI Fill Header
+//
+#define PXE_OPFLAGS_FILL_HEADER_OPMASK 0x0001
+#define PXE_OPFLAGS_FILL_HEADER_FRAGMENTED 0x0001
+#define PXE_OPFLAGS_FILL_HEADER_WHOLE 0x0000
+
+//
+// //////////////////////////////////////
+// UNDI Transmit
+//
+//
+// S/W UNDI only. Return after the packet has been transmitted. A
+// transmit complete interrupt will still be generated and the transmit
+// buffer will have to be recycled.
+//
+#define PXE_OPFLAGS_SWUNDI_TRANSMIT_OPMASK 0x0001
+#define PXE_OPFLAGS_TRANSMIT_BLOCK 0x0001
+#define PXE_OPFLAGS_TRANSMIT_DONT_BLOCK 0x0000
+
+//
+//
+//
+#define PXE_OPFLAGS_TRANSMIT_OPMASK 0x0002
+#define PXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002
+#define PXE_OPFLAGS_TRANSMIT_WHOLE 0x0000
+
+//
+// //////////////////////////////////////
+// UNDI Receive
+//
+// No OpFlags
+//
+typedef UINT16 PXE_STATFLAGS;
+
+#define PXE_STATFLAGS_INITIALIZE 0x0000
+
+//
+// //////////////////////////////////////
+// Common StatFlags that can be returned by all commands.
+//
+//
+// The COMMAND_COMPLETE and COMMAND_FAILED status flags must be
+// implemented by all UNDIs. COMMAND_QUEUED is only needed by UNDIs
+// that support command queuing.
+//
+#define PXE_STATFLAGS_STATUS_MASK 0xC000
+#define PXE_STATFLAGS_COMMAND_COMPLETE 0xC000
+#define PXE_STATFLAGS_COMMAND_FAILED 0x8000
+#define PXE_STATFLAGS_COMMAND_QUEUED 0x4000
+//
+// #define PXE_STATFLAGS_INITIALIZE 0x0000
+//
+#define PXE_STATFLAGS_DB_WRITE_TRUNCATED 0x2000
+
+//
+// //////////////////////////////////////
+// UNDI Get State
+//
+#define PXE_STATFLAGS_GET_STATE_MASK 0x0003
+#define PXE_STATFLAGS_GET_STATE_INITIALIZED 0x0002
+#define PXE_STATFLAGS_GET_STATE_STARTED 0x0001
+#define PXE_STATFLAGS_GET_STATE_STOPPED 0x0000
+
+//
+// //////////////////////////////////////
+// UNDI Start
+//
+// No additional StatFlags
+
+////////////////////////////////////////
+// UNDI Get Init Info
+//
+#define PXE_STATFLAGS_CABLE_DETECT_MASK 0x0001
+#define PXE_STATFLAGS_CABLE_DETECT_NOT_SUPPORTED 0x0000
+#define PXE_STATFLAGS_CABLE_DETECT_SUPPORTED 0x0001
+
+//
+// //////////////////////////////////////
+// UNDI Initialize
+//
+#define PXE_STATFLAGS_INITIALIZED_NO_MEDIA 0x0001
+
+//
+// //////////////////////////////////////
+// UNDI Reset
+//
+#define PXE_STATFLAGS_RESET_NO_MEDIA 0x0001
+
+//
+// //////////////////////////////////////
+// UNDI Shutdown
+//
+// No additional StatFlags
+
+////////////////////////////////////////
+// UNDI Interrupt Enables
+//
+//
+// If set, receive interrupts are enabled.
+//
+#define PXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001
+
+//
+// If set, transmit interrupts are enabled.
+//
+#define PXE_STATFLAGS_INTERRUPT_TRANSMIT 0x0002
+
+//
+// If set, command interrupts are enabled.
+//
+#define PXE_STATFLAGS_INTERRUPT_COMMAND 0x0004
+
+//
+// //////////////////////////////////////
+// UNDI Receive Filters
+//
+//
+// If set, unicast packets will be received.
+//
+#define PXE_STATFLAGS_RECEIVE_FILTER_UNICAST 0x0001
+
+//
+// If set, broadcast packets will be received.
+//
+#define PXE_STATFLAGS_RECEIVE_FILTER_BROADCAST 0x0002
+
+//
+// If set, multicast packets that match up with the multicast address
+// filter list will be received.
+//
+#define PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
+
+//
+// If set, all packets will be received.
+//
+#define PXE_STATFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008
+
+//
+// If set, all multicast packets will be received.
+//
+#define PXE_STATFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010
+
+//
+// //////////////////////////////////////
+// UNDI Station Address
+//
+// No additional StatFlags
+
+////////////////////////////////////////
+// UNDI Statistics
+//
+// No additional StatFlags
+
+////////////////////////////////////////
+// UNDI MCast IP to MAC
+//
+// No additional StatFlags
+
+////////////////////////////////////////
+// UNDI NvData
+//
+// No additional StatFlags
+
+
+////////////////////////////////////////
+// UNDI Get Status
+//
+//
+// Use to determine if an interrupt has occurred.
+//
+#define PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK 0x000F
+#define PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS 0x0000
+
+//
+// If set, at least one receive interrupt occurred.
+//
+#define PXE_STATFLAGS_GET_STATUS_RECEIVE 0x0001
+
+//
+// If set, at least one transmit interrupt occurred.
+//
+#define PXE_STATFLAGS_GET_STATUS_TRANSMIT 0x0002
+
+//
+// If set, at least one command interrupt occurred.
+//
+#define PXE_STATFLAGS_GET_STATUS_COMMAND 0x0004
+
+//
+// If set, at least one software interrupt occurred.
+//
+#define PXE_STATFLAGS_GET_STATUS_SOFTWARE 0x0008
+
+//
+// This flag is set if the transmitted buffer queue is empty. This flag
+// will be set if all transmitted buffer addresses get written into the DB.
+//
+#define PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY 0x0010
+
+//
+// This flag is set if no transmitted buffer addresses were written
+// into the DB. (This could be because DBsize was too small.)
+//
+#define PXE_STATFLAGS_GET_STATUS_NO_TXBUFS_WRITTEN 0x0020
+
+//
+// //////////////////////////////////////
+// UNDI Fill Header
+//
+// No additional StatFlags
+
+////////////////////////////////////////
+// UNDI Transmit
+//
+// No additional StatFlags.
+
+////////////////////////////////////////
+// UNDI Receive
+//
+// No additional StatFlags.
+//
+typedef UINT16 PXE_STATCODE;
+
+#define PXE_STATCODE_INITIALIZE 0x0000
+
+//
+// //////////////////////////////////////
+// Common StatCodes returned by all UNDI commands, UNDI protocol functions
+// and BC protocol functions.
+//
+#define PXE_STATCODE_SUCCESS 0x0000
+
+#define PXE_STATCODE_INVALID_CDB 0x0001
+#define PXE_STATCODE_INVALID_CPB 0x0002
+#define PXE_STATCODE_BUSY 0x0003
+#define PXE_STATCODE_QUEUE_FULL 0x0004
+#define PXE_STATCODE_ALREADY_STARTED 0x0005
+#define PXE_STATCODE_NOT_STARTED 0x0006
+#define PXE_STATCODE_NOT_SHUTDOWN 0x0007
+#define PXE_STATCODE_ALREADY_INITIALIZED 0x0008
+#define PXE_STATCODE_NOT_INITIALIZED 0x0009
+#define PXE_STATCODE_DEVICE_FAILURE 0x000A
+#define PXE_STATCODE_NVDATA_FAILURE 0x000B
+#define PXE_STATCODE_UNSUPPORTED 0x000C
+#define PXE_STATCODE_BUFFER_FULL 0x000D
+#define PXE_STATCODE_INVALID_PARAMETER 0x000E
+#define PXE_STATCODE_INVALID_UNDI 0x000F
+#define PXE_STATCODE_IPV4_NOT_SUPPORTED 0x0010
+#define PXE_STATCODE_IPV6_NOT_SUPPORTED 0x0011
+#define PXE_STATCODE_NOT_ENOUGH_MEMORY 0x0012
+#define PXE_STATCODE_NO_DATA 0x0013
+
+typedef UINT16 PXE_IFNUM;
+
+//
+// This interface number must be passed to the S/W UNDI Start command.
+//
+#define PXE_IFNUM_START 0x0000
+
+//
+// This interface number is returned by the S/W UNDI Get State and
+// Start commands if information in the CDB, CPB or DB is invalid.
+//
+#define PXE_IFNUM_INVALID 0x0000
+
+typedef UINT16 PXE_CONTROL;
+
+//
+// Setting this flag directs the UNDI to queue this command for later
+// execution if the UNDI is busy and it supports command queuing.
+// If queuing is not supported, a PXE_STATCODE_INVALID_CONTROL error
+// is returned. If the queue is full, a PXE_STATCODE_CDB_QUEUE_FULL
+// error is returned.
+//
+#define PXE_CONTROL_QUEUE_IF_BUSY 0x0002
+
+//
+// These two bit values are used to determine if there are more UNDI
+// CDB structures following this one. If the link bit is set, there
+// must be a CDB structure following this one. Execution will start
+// on the next CDB structure as soon as this one completes successfully.
+// If an error is generated by this command, execution will stop.
+//
+#define PXE_CONTROL_LINK 0x0001
+#define PXE_CONTROL_LAST_CDB_IN_LIST 0x0000
+
+typedef UINT8 PXE_FRAME_TYPE;
+
+#define PXE_FRAME_TYPE_NONE 0x00
+#define PXE_FRAME_TYPE_UNICAST 0x01
+#define PXE_FRAME_TYPE_BROADCAST 0x02
+#define PXE_FRAME_TYPE_MULTICAST 0x03
+#define PXE_FRAME_TYPE_PROMISCUOUS 0x04
+
+typedef UINT32 PXE_IPV4;
+
+typedef UINT32 PXE_IPV6[4];
+#define PXE_MAC_LENGTH 32
+
+typedef UINT8 PXE_MAC_ADDR[PXE_MAC_LENGTH];
+
+typedef UINT8 PXE_IFTYPE;
+typedef UINT16 PXE_MEDIA_PROTOCOL;
+
+//
+// This information is from the ARP section of RFC 1700.
+//
+// 1 Ethernet (10Mb) [JBP]
+// 2 Experimental Ethernet (3Mb) [JBP]
+// 3 Amateur Radio AX.25 [PXK]
+// 4 Proteon ProNET Token Ring [JBP]
+// 5 Chaos [GXP]
+// 6 IEEE 802 Networks [JBP]
+// 7 ARCNET [JBP]
+// 8 Hyperchannel [JBP]
+// 9 Lanstar [TU]
+// 10 Autonet Short Address [MXB1]
+// 11 LocalTalk [JKR1]
+// 12 LocalNet (IBM* PCNet or SYTEK* LocalNET) [JXM]
+// 13 Ultra link [RXD2]
+// 14 SMDS [GXC1]
+// 15 Frame Relay [AGM]
+// 16 Asynchronous Transmission Mode (ATM) [JXB2]
+// 17 HDLC [JBP]
+// 18 Fibre Channel [Yakov Rekhter]
+// 19 Asynchronous Transmission Mode (ATM) [Mark Laubach]
+// 20 Serial Line [JBP]
+// 21 Asynchronous Transmission Mode (ATM) [MXB1]
+//
+// * Other names and brands may be claimed as the property of others.
+//
+#define PXE_IFTYPE_ETHERNET 0x01
+#define PXE_IFTYPE_TOKENRING 0x04
+#define PXE_IFTYPE_FIBRE_CHANNEL 0x12
+
+typedef struct s_pxe_hw_undi {
+ UINT32 Signature; // PXE_ROMID_SIGNATURE
+ UINT8 Len; // sizeof(PXE_HW_UNDI)
+ UINT8 Fudge; // makes 8-bit cksum equal zero
+ UINT8 Rev; // PXE_ROMID_REV
+ UINT8 IFcnt; // physical connector count
+ UINT8 MajorVer; // PXE_ROMID_MAJORVER
+ UINT8 MinorVer; // PXE_ROMID_MINORVER
+ UINT16 reserved; // zero, not used
+ UINT32 Implementation; // implementation flags
+ // reserved // vendor use
+ // UINT32 Status; // status port
+ // UINT32 Command; // command port
+ // UINT64 CDBaddr; // CDB address port
+ //
+} PXE_HW_UNDI;
+
+//
+// Status port bit definitions
+//
+//
+// UNDI operation state
+//
+#define PXE_HWSTAT_STATE_MASK 0xC0000000
+#define PXE_HWSTAT_BUSY 0xC0000000
+#define PXE_HWSTAT_INITIALIZED 0x80000000
+#define PXE_HWSTAT_STARTED 0x40000000
+#define PXE_HWSTAT_STOPPED 0x00000000
+
+//
+// If set, last command failed
+//
+#define PXE_HWSTAT_COMMAND_FAILED 0x20000000
+
+//
+// If set, identifies enabled receive filters
+//
+#define PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED 0x00001000
+#define PXE_HWSTAT_PROMISCUOUS_RX_ENABLED 0x00000800
+#define PXE_HWSTAT_BROADCAST_RX_ENABLED 0x00000400
+#define PXE_HWSTAT_MULTICAST_RX_ENABLED 0x00000200
+#define PXE_HWSTAT_UNICAST_RX_ENABLED 0x00000100
+
+//
+// If set, identifies enabled external interrupts
+//
+#define PXE_HWSTAT_SOFTWARE_INT_ENABLED 0x00000080
+#define PXE_HWSTAT_TX_COMPLETE_INT_ENABLED 0x00000040
+#define PXE_HWSTAT_PACKET_RX_INT_ENABLED 0x00000020
+#define PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED 0x00000010
+
+//
+// If set, identifies pending interrupts
+//
+#define PXE_HWSTAT_SOFTWARE_INT_PENDING 0x00000008
+#define PXE_HWSTAT_TX_COMPLETE_INT_PENDING 0x00000004
+#define PXE_HWSTAT_PACKET_RX_INT_PENDING 0x00000002
+#define PXE_HWSTAT_CMD_COMPLETE_INT_PENDING 0x00000001
+
+//
+// Command port definitions
+//
+//
+// If set, CDB identified in CDBaddr port is given to UNDI.
+// If not set, other bits in this word will be processed.
+//
+#define PXE_HWCMD_ISSUE_COMMAND 0x80000000
+#define PXE_HWCMD_INTS_AND_FILTS 0x00000000
+
+//
+// Use these to enable/disable receive filters.
+//
+#define PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE 0x00001000
+#define PXE_HWCMD_PROMISCUOUS_RX_ENABLE 0x00000800
+#define PXE_HWCMD_BROADCAST_RX_ENABLE 0x00000400
+#define PXE_HWCMD_MULTICAST_RX_ENABLE 0x00000200
+#define PXE_HWCMD_UNICAST_RX_ENABLE 0x00000100
+
+//
+// Use these to enable/disable external interrupts
+//
+#define PXE_HWCMD_SOFTWARE_INT_ENABLE 0x00000080
+#define PXE_HWCMD_TX_COMPLETE_INT_ENABLE 0x00000040
+#define PXE_HWCMD_PACKET_RX_INT_ENABLE 0x00000020
+#define PXE_HWCMD_CMD_COMPLETE_INT_ENABLE 0x00000010
+
+//
+// Use these to clear pending external interrupts
+//
+#define PXE_HWCMD_CLEAR_SOFTWARE_INT 0x00000008
+#define PXE_HWCMD_CLEAR_TX_COMPLETE_INT 0x00000004
+#define PXE_HWCMD_CLEAR_PACKET_RX_INT 0x00000002
+#define PXE_HWCMD_CLEAR_CMD_COMPLETE_INT 0x00000001
+
+typedef struct s_pxe_sw_undi {
+ UINT32 Signature; // PXE_ROMID_SIGNATURE
+ UINT8 Len; // sizeof(PXE_SW_UNDI)
+ UINT8 Fudge; // makes 8-bit cksum zero
+ UINT8 Rev; // PXE_ROMID_REV
+ UINT8 IFcnt; // physical connector count
+ UINT8 MajorVer; // PXE_ROMID_MAJORVER
+ UINT8 MinorVer; // PXE_ROMID_MINORVER
+ UINT16 reserved1; // zero, not used
+ UINT32 Implementation; // Implementation flags
+ UINT64 EntryPoint; // API entry point
+ UINT8 reserved2[3]; // zero, not used
+ UINT8 BusCnt; // number of bustypes supported
+ UINT32 BusType[1]; // list of supported bustypes
+} PXE_SW_UNDI;
+
+typedef union u_pxe_undi {
+ PXE_HW_UNDI hw;
+ PXE_SW_UNDI sw;
+} PXE_UNDI;
+
+//
+// Signature of !PXE structure
+//
+#define PXE_ROMID_SIGNATURE PXE_BUSTYPE ('!', 'P', 'X', 'E')
+
+//
+// !PXE structure format revision
+//
+#define PXE_ROMID_REV 0x02
+
+//
+// UNDI command interface revision. These are the values that get sent
+// in option 94 (Client Network Interface Identifier) in the DHCP Discover
+// and PXE Boot Server Request packets.
+//
+#define PXE_ROMID_MAJORVER 0x03
+#define PXE_ROMID_MINORVER 0x00
+#define PXE_ROMID_MINORVER_31 0x10
+
+//
+// Implementation flags
+//
+#define PXE_ROMID_IMP_HW_UNDI 0x80000000
+#define PXE_ROMID_IMP_SW_VIRT_ADDR 0x40000000
+#define PXE_ROMID_IMP_64BIT_DEVICE 0x00010000
+#define PXE_ROMID_IMP_FRAG_SUPPORTED 0x00008000
+#define PXE_ROMID_IMP_CMD_LINK_SUPPORTED 0x00004000
+#define PXE_ROMID_IMP_CMD_QUEUE_SUPPORTED 0x00002000
+#define PXE_ROMID_IMP_MULTI_FRAME_SUPPORTED 0x00001000
+#define PXE_ROMID_IMP_NVDATA_SUPPORT_MASK 0x00000C00
+#define PXE_ROMID_IMP_NVDATA_BULK_WRITABLE 0x00000C00
+#define PXE_ROMID_IMP_NVDATA_SPARSE_WRITABLE 0x00000800
+#define PXE_ROMID_IMP_NVDATA_READ_ONLY 0x00000400
+#define PXE_ROMID_IMP_NVDATA_NOT_AVAILABLE 0x00000000
+#define PXE_ROMID_IMP_STATISTICS_SUPPORTED 0x00000200
+#define PXE_ROMID_IMP_STATION_ADDR_SETTABLE 0x00000100
+#define PXE_ROMID_IMP_PROMISCUOUS_MULTICAST_RX_SUPPORTED 0x00000080
+#define PXE_ROMID_IMP_PROMISCUOUS_RX_SUPPORTED 0x00000040
+#define PXE_ROMID_IMP_BROADCAST_RX_SUPPORTED 0x00000020
+#define PXE_ROMID_IMP_FILTERED_MULTICAST_RX_SUPPORTED 0x00000010
+#define PXE_ROMID_IMP_SOFTWARE_INT_SUPPORTED 0x00000008
+#define PXE_ROMID_IMP_TX_COMPLETE_INT_SUPPORTED 0x00000004
+#define PXE_ROMID_IMP_PACKET_RX_INT_SUPPORTED 0x00000002
+#define PXE_ROMID_IMP_CMD_COMPLETE_INT_SUPPORTED 0x00000001
+
+typedef struct s_pxe_cdb {
+ PXE_OPCODE OpCode;
+ PXE_OPFLAGS OpFlags;
+ UINT16 CPBsize;
+ UINT16 DBsize;
+ UINT64 CPBaddr;
+ UINT64 DBaddr;
+ PXE_STATCODE StatCode;
+ PXE_STATFLAGS StatFlags;
+ UINT16 IFnum;
+ PXE_CONTROL Control;
+} PXE_CDB;
+
+typedef union u_pxe_ip_addr {
+ PXE_IPV6 IPv6;
+ PXE_IPV4 IPv4;
+} PXE_IP_ADDR;
+
+typedef union pxe_device {
+ //
+ // PCI and PC Card NICs are both identified using bus, device
+ // and function numbers. For PC Card, this may require PC
+ // Card services to be loaded in the BIOS or preboot
+ // environment.
+ //
+ struct {
+ //
+ // See S/W UNDI ROMID structure definition for PCI and
+ // PCC BusType definitions.
+ //
+ UINT32 BusType;
+
+ //
+ // Bus, device & function numbers that locate this device.
+ //
+ UINT16 Bus;
+ UINT8 Device;
+ UINT8 Function;
+ }
+ PCI, PCC;
+
+ //
+ // %%TBD - More information is needed about enumerating
+ // USB and 1394 devices.
+ //
+ struct {
+ UINT32 BusType;
+ UINT32 tdb;
+ }
+ USB, _1394;
+} PXE_DEVICE;
+
+//
+// cpb and db definitions
+//
+#define MAX_PCI_CONFIG_LEN 64 // # of dwords
+#define MAX_EEPROM_LEN 128 // #of dwords
+#define MAX_XMIT_BUFFERS 32 // recycling Q length for xmit_done
+#define MAX_MCAST_ADDRESS_CNT 8
+
+typedef struct s_pxe_cpb_start {
+ //
+ // PXE_VOID Delay(UINTN microseconds);
+ //
+ // UNDI will never request a delay smaller than 10 microseconds
+ // and will always request delays in increments of 10 microseconds.
+ // The Delay() CallBack routine must delay between n and n + 10
+ // microseconds before returning control to the UNDI.
+ //
+ // This field cannot be set to zero.
+ //
+ UINT64 Delay;
+
+ //
+ // PXE_VOID Block(UINT32 enable);
+ //
+ // UNDI may need to block multi-threaded/multi-processor access to
+ // critical code sections when programming or accessing the network
+ // device. To this end, a blocking service is needed by the UNDI.
+ // When UNDI needs a block, it will call Block() passing a non-zero
+ // value. When UNDI no longer needs a block, it will call Block()
+ // with a zero value. When called, if the Block() is already enabled,
+ // do not return control to the UNDI until the previous Block() is
+ // disabled.
+ //
+ // This field cannot be set to zero.
+ //
+ UINT64 Block;
+
+ //
+ // PXE_VOID Virt2Phys(UINT64 virtual, UINT64 physical_ptr);
+ //
+ // UNDI will pass the virtual address of a buffer and the virtual
+ // address of a 64-bit physical buffer. Convert the virtual address
+ // to a physical address and write the result to the physical address
+ // buffer. If virtual and physical addresses are the same, just
+ // copy the virtual address to the physical address buffer.
+ //
+ // This field can be set to zero if virtual and physical addresses
+ // are equal.
+ //
+ UINT64 Virt2Phys;
+ //
+ // PXE_VOID Mem_IO(UINT8 read_write, UINT8 len, UINT64 port,
+ // UINT64 buf_addr);
+ //
+ // UNDI will read or write the device io space using this call back
+ // function. It passes the number of bytes as the len parameter and it
+ // will be either 1,2,4 or 8.
+ //
+ // This field can not be set to zero.
+ //
+ UINT64 Mem_IO;
+} PXE_CPB_START;
+
+typedef struct s_pxe_cpb_start_31 {
+ //
+ // PXE_VOID Delay(UINT64 UnqId, UINTN microseconds);
+ //
+ // UNDI will never request a delay smaller than 10 microseconds
+ // and will always request delays in increments of 10 microseconds.
+ // The Delay() CallBack routine must delay between n and n + 10
+ // microseconds before returning control to the UNDI.
+ //
+ // This field cannot be set to zero.
+ //
+ UINT64 Delay;
+
+ //
+ // PXE_VOID Block(UINT64 unq_id, UINT32 enable);
+ //
+ // UNDI may need to block multi-threaded/multi-processor access to
+ // critical code sections when programming or accessing the network
+ // device. To this end, a blocking service is needed by the UNDI.
+ // When UNDI needs a block, it will call Block() passing a non-zero
+ // value. When UNDI no longer needs a block, it will call Block()
+ // with a zero value. When called, if the Block() is already enabled,
+ // do not return control to the UNDI until the previous Block() is
+ // disabled.
+ //
+ // This field cannot be set to zero.
+ //
+ UINT64 Block;
+
+ //
+ // PXE_VOID Virt2Phys(UINT64 UnqId, UINT64 virtual, UINT64 physical_ptr);
+ //
+ // UNDI will pass the virtual address of a buffer and the virtual
+ // address of a 64-bit physical buffer. Convert the virtual address
+ // to a physical address and write the result to the physical address
+ // buffer. If virtual and physical addresses are the same, just
+ // copy the virtual address to the physical address buffer.
+ //
+ // This field can be set to zero if virtual and physical addresses
+ // are equal.
+ //
+ UINT64 Virt2Phys;
+ //
+ // PXE_VOID Mem_IO(UINT64 UnqId, UINT8 read_write, UINT8 len, UINT64 port,
+ // UINT64 buf_addr);
+ //
+ // UNDI will read or write the device io space using this call back
+ // function. It passes the number of bytes as the len parameter and it
+ // will be either 1,2,4 or 8.
+ //
+ // This field can not be set to zero.
+ //
+ UINT64 Mem_IO;
+ //
+ // PXE_VOID Map_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
+ // UINT32 Direction, UINT64 mapped_addr);
+ //
+ // UNDI will pass the virtual address of a buffer, direction of the data
+ // flow from/to the mapped buffer (the constants are defined below)
+ // and a place holder (pointer) for the mapped address.
+ // This call will Map the given address to a physical DMA address and write
+ // the result to the mapped_addr pointer. If there is no need to
+ // map the given address to a lower address (i.e. the given address is
+ // associated with a physical address that is already compatible to be
+ // used with the DMA, it converts the given virtual address to it's
+ // physical address and write that in the mapped address pointer.
+ //
+ // This field can be set to zero if there is no mapping service available
+ //
+ UINT64 Map_Mem;
+
+ //
+ // PXE_VOID UnMap_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
+ // UINT32 Direction, UINT64 mapped_addr);
+ //
+ // UNDI will pass the virtual and mapped addresses of a buffer
+ // This call will un map the given address
+ //
+ // This field can be set to zero if there is no unmapping service available
+ //
+ UINT64 UnMap_Mem;
+
+ //
+ // PXE_VOID Sync_Mem(UINT64 unq_id, UINT64 virtual,
+ // UINT32 size, UINT32 Direction, UINT64 mapped_addr);
+ //
+ // UNDI will pass the virtual and mapped addresses of a buffer
+ // This call will synchronize the contents of both the virtual and mapped
+ // buffers for the given Direction.
+ //
+ // This field can be set to zero if there is no service available
+ //
+ UINT64 Sync_Mem;
+
+ //
+ // protocol driver can provide anything for this Unique_ID, UNDI remembers
+ // that as just a 64bit value assocaited to the interface specified by
+ // the ifnum and gives it back as a parameter to all the call-back routines
+ // when calling for that interface!
+ //
+ UINT64 Unique_ID;
+ //
+} PXE_CPB_START_31;
+
+#define TO_AND_FROM_DEVICE 0
+#define FROM_DEVICE 1
+#define TO_DEVICE 2
+
+#define PXE_DELAY_MILLISECOND 1000
+#define PXE_DELAY_SECOND 1000000
+#define PXE_IO_READ 0
+#define PXE_IO_WRITE 1
+#define PXE_MEM_READ 2
+#define PXE_MEM_WRITE 4
+
+typedef struct s_pxe_db_get_init_info {
+ //
+ // Minimum length of locked memory buffer that must be given to
+ // the Initialize command. Giving UNDI more memory will generally
+ // give better performance.
+ //
+ // If MemoryRequired is zero, the UNDI does not need and will not
+ // use system memory to receive and transmit packets.
+ //
+ UINT32 MemoryRequired;
+
+ //
+ // Maximum frame data length for Tx/Rx excluding the media header.
+ //
+ UINT32 FrameDataLen;
+
+ //
+ // Supported link speeds are in units of mega bits. Common ethernet
+ // values are 10, 100 and 1000. Unused LinkSpeeds[] entries are zero
+ // filled.
+ //
+ UINT32 LinkSpeeds[4];
+
+ //
+ // Number of non-volatile storage items.
+ //
+ UINT32 NvCount;
+
+ //
+ // Width of non-volatile storage item in bytes. 0, 1, 2 or 4
+ //
+ UINT16 NvWidth;
+
+ //
+ // Media header length. This is the typical media header length for
+ // this UNDI. This information is needed when allocating receive
+ // and transmit buffers.
+ //
+ UINT16 MediaHeaderLen;
+
+ //
+ // Number of bytes in the NIC hardware (MAC) address.
+ //
+ UINT16 HWaddrLen;
+
+ //
+ // Maximum number of multicast MAC addresses in the multicast
+ // MAC address filter list.
+ //
+ UINT16 MCastFilterCnt;
+
+ //
+ // Default number and size of transmit and receive buffers that will
+ // be allocated by the UNDI. If MemoryRequired is non-zero, this
+ // allocation will come out of the memory buffer given to the Initialize
+ // command. If MemoryRequired is zero, this allocation will come out of
+ // memory on the NIC.
+ //
+ UINT16 TxBufCnt;
+ UINT16 TxBufSize;
+ UINT16 RxBufCnt;
+ UINT16 RxBufSize;
+
+ //
+ // Hardware interface types defined in the Assigned Numbers RFC
+ // and used in DHCP and ARP packets.
+ // See the PXE_IFTYPE typedef and PXE_IFTYPE_xxx macros.
+ //
+ UINT8 IFtype;
+
+ //
+ // Supported duplex. See PXE_DUPLEX_xxxxx #defines below.
+ //
+ UINT8 Duplex;
+
+ //
+ // Supported loopback options. See PXE_LOOPBACK_xxxxx #defines below.
+ //
+ UINT8 LoopBack;
+} PXE_DB_GET_INIT_INFO;
+
+#define PXE_MAX_TXRX_UNIT_ETHER 1500
+
+#define PXE_HWADDR_LEN_ETHER 0x0006
+#define PXE_MAC_HEADER_LEN_ETHER 0x000E
+
+#define PXE_DUPLEX_ENABLE_FULL_SUPPORTED 1
+#define PXE_DUPLEX_FORCE_FULL_SUPPORTED 2
+
+#define PXE_LOOPBACK_INTERNAL_SUPPORTED 1
+#define PXE_LOOPBACK_EXTERNAL_SUPPORTED 2
+
+typedef struct s_pxe_pci_config_info {
+ //
+ // This is the flag field for the PXE_DB_GET_CONFIG_INFO union.
+ // For PCI bus devices, this field is set to PXE_BUSTYPE_PCI.
+ //
+ UINT32 BusType;
+
+ //
+ // This identifies the PCI network device that this UNDI interface
+ // is bound to.
+ //
+ UINT16 Bus;
+ UINT8 Device;
+ UINT8 Function;
+
+ //
+ // This is a copy of the PCI configuration space for this
+ // network device.
+ //
+ union {
+ UINT8 Byte[256];
+ UINT16 Word[128];
+ UINT32 Dword[64];
+ } Config;
+} PXE_PCI_CONFIG_INFO;
+
+typedef struct s_pxe_pcc_config_info {
+ //
+ // This is the flag field for the PXE_DB_GET_CONFIG_INFO union.
+ // For PCC bus devices, this field is set to PXE_BUSTYPE_PCC.
+ //
+ UINT32 BusType;
+
+ //
+ // This identifies the PCC network device that this UNDI interface
+ // is bound to.
+ //
+ UINT16 Bus;
+ UINT8 Device;
+ UINT8 Function;
+
+ //
+ // This is a copy of the PCC configuration space for this
+ // network device.
+ //
+ union {
+ UINT8 Byte[256];
+ UINT16 Word[128];
+ UINT32 Dword[64];
+ } Config;
+} PXE_PCC_CONFIG_INFO;
+
+typedef struct s_pxe_usb_config_info {
+ UINT32 BusType;
+ //
+ // %%TBD What should we return here...
+ //
+} PXE_USB_CONFIG_INFO;
+
+typedef struct s_pxe_1394_config_info {
+ UINT32 BusType;
+ //
+ // %%TBD What should we return here...
+ //
+} PXE_1394_CONFIG_INFO;
+
+typedef union u_pxe_db_get_config_info {
+ PXE_PCI_CONFIG_INFO pci;
+ PXE_PCC_CONFIG_INFO pcc;
+ PXE_USB_CONFIG_INFO usb;
+ PXE_1394_CONFIG_INFO _1394;
+} PXE_DB_GET_CONFIG_INFO;
+
+typedef struct s_pxe_cpb_initialize {
+ //
+ // Address of first (lowest) byte of the memory buffer. This buffer must
+ // be in contiguous physical memory and cannot be swapped out. The UNDI
+ // will be using this for transmit and receive buffering.
+ //
+ UINT64 MemoryAddr;
+
+ //
+ // MemoryLength must be greater than or equal to MemoryRequired
+ // returned by the Get Init Info command.
+ //
+ UINT32 MemoryLength;
+
+ //
+ // Desired link speed in Mbit/sec. Common ethernet values are 10, 100
+ // and 1000. Setting a value of zero will auto-detect and/or use the
+ // default link speed (operation depends on UNDI/NIC functionality).
+ //
+ UINT32 LinkSpeed;
+
+ //
+ // Suggested number and size of receive and transmit buffers to
+ // allocate. If MemoryAddr and MemoryLength are non-zero, this
+ // allocation comes out of the supplied memory buffer. If MemoryAddr
+ // and MemoryLength are zero, this allocation comes out of memory
+ // on the NIC.
+ //
+ // If these fields are set to zero, the UNDI will allocate buffer
+ // counts and sizes as it sees fit.
+ //
+ UINT16 TxBufCnt;
+ UINT16 TxBufSize;
+ UINT16 RxBufCnt;
+ UINT16 RxBufSize;
+
+ //
+ // The following configuration parameters are optional and must be zero
+ // to use the default values.
+ //
+ UINT8 Duplex;
+
+ UINT8 LoopBack;
+} PXE_CPB_INITIALIZE;
+
+#define PXE_DUPLEX_DEFAULT 0x00
+#define PXE_FORCE_FULL_DUPLEX 0x01
+#define PXE_ENABLE_FULL_DUPLEX 0x02
+#define PXE_FORCE_HALF_DUPLEX 0x04
+#define PXE_DISABLE_FULL_DUPLEX 0x08
+
+#define LOOPBACK_NORMAL 0
+#define LOOPBACK_INTERNAL 1
+#define LOOPBACK_EXTERNAL 2
+
+typedef struct s_pxe_db_initialize {
+ //
+ // Actual amount of memory used from the supplied memory buffer. This
+ // may be less that the amount of memory suppllied and may be zero if
+ // the UNDI and network device do not use external memory buffers.
+ //
+ // Memory used by the UNDI and network device is allocated from the
+ // lowest memory buffer address.
+ //
+ UINT32 MemoryUsed;
+
+ //
+ // Actual number and size of receive and transmit buffers that were
+ // allocated.
+ //
+ UINT16 TxBufCnt;
+ UINT16 TxBufSize;
+ UINT16 RxBufCnt;
+ UINT16 RxBufSize;
+} PXE_DB_INITIALIZE;
+
+typedef struct s_pxe_cpb_receive_filters {
+ //
+ // List of multicast MAC addresses. This list, if present, will
+ // replace the existing multicast MAC address filter list.
+ //
+ PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];
+} PXE_CPB_RECEIVE_FILTERS;
+
+typedef struct s_pxe_db_receive_filters {
+ //
+ // Filtered multicast MAC address list.
+ //
+ PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];
+} PXE_DB_RECEIVE_FILTERS;
+
+typedef struct s_pxe_cpb_station_address {
+ //
+ // If supplied and supported, the current station MAC address
+ // will be changed.
+ //
+ PXE_MAC_ADDR StationAddr;
+} PXE_CPB_STATION_ADDRESS;
+
+typedef struct s_pxe_dpb_station_address {
+ //
+ // Current station MAC address.
+ //
+ PXE_MAC_ADDR StationAddr;
+
+ //
+ // Station broadcast MAC address.
+ //
+ PXE_MAC_ADDR BroadcastAddr;
+
+ //
+ // Permanent station MAC address.
+ //
+ PXE_MAC_ADDR PermanentAddr;
+} PXE_DB_STATION_ADDRESS;
+
+typedef struct s_pxe_db_statistics {
+ //
+ // Bit field identifying what statistic data is collected by the
+ // UNDI/NIC.
+ // If bit 0x00 is set, Data[0x00] is collected.
+ // If bit 0x01 is set, Data[0x01] is collected.
+ // If bit 0x20 is set, Data[0x20] is collected.
+ // If bit 0x21 is set, Data[0x21] is collected.
+ // Etc.
+ //
+ UINT64 Supported;
+
+ //
+ // Statistic data.
+ //
+ UINT64 Data[64];
+} PXE_DB_STATISTICS;
+
+//
+// Total number of frames received. Includes frames with errors and
+// dropped frames.
+//
+#define PXE_STATISTICS_RX_TOTAL_FRAMES 0x00
+
+//
+// Number of valid frames received and copied into receive buffers.
+//
+#define PXE_STATISTICS_RX_GOOD_FRAMES 0x01
+
+//
+// Number of frames below the minimum length for the media.
+// This would be <64 for ethernet.
+//
+#define PXE_STATISTICS_RX_UNDERSIZE_FRAMES 0x02
+
+//
+// Number of frames longer than the maxminum length for the
+// media. This would be >1500 for ethernet.
+//
+#define PXE_STATISTICS_RX_OVERSIZE_FRAMES 0x03
+
+//
+// Valid frames that were dropped because receive buffers were full.
+//
+#define PXE_STATISTICS_RX_DROPPED_FRAMES 0x04
+
+//
+// Number of valid unicast frames received and not dropped.
+//
+#define PXE_STATISTICS_RX_UNICAST_FRAMES 0x05
+
+//
+// Number of valid broadcast frames received and not dropped.
+//
+#define PXE_STATISTICS_RX_BROADCAST_FRAMES 0x06
+
+//
+// Number of valid mutlicast frames received and not dropped.
+//
+#define PXE_STATISTICS_RX_MULTICAST_FRAMES 0x07
+
+//
+// Number of frames w/ CRC or alignment errors.
+//
+#define PXE_STATISTICS_RX_CRC_ERROR_FRAMES 0x08
+
+//
+// Total number of bytes received. Includes frames with errors
+// and dropped frames.
+//
+#define PXE_STATISTICS_RX_TOTAL_BYTES 0x09
+
+//
+// Transmit statistics.
+//
+#define PXE_STATISTICS_TX_TOTAL_FRAMES 0x0A
+#define PXE_STATISTICS_TX_GOOD_FRAMES 0x0B
+#define PXE_STATISTICS_TX_UNDERSIZE_FRAMES 0x0C
+#define PXE_STATISTICS_TX_OVERSIZE_FRAMES 0x0D
+#define PXE_STATISTICS_TX_DROPPED_FRAMES 0x0E
+#define PXE_STATISTICS_TX_UNICAST_FRAMES 0x0F
+#define PXE_STATISTICS_TX_BROADCAST_FRAMES 0x10
+#define PXE_STATISTICS_TX_MULTICAST_FRAMES 0x11
+#define PXE_STATISTICS_TX_CRC_ERROR_FRAMES 0x12
+#define PXE_STATISTICS_TX_TOTAL_BYTES 0x13
+
+//
+// Number of collisions detection on this subnet.
+//
+#define PXE_STATISTICS_COLLISIONS 0x14
+
+//
+// Number of frames destined for unsupported protocol.
+//
+#define PXE_STATISTICS_UNSUPPORTED_PROTOCOL 0x15
+
+typedef struct s_pxe_cpb_mcast_ip_to_mac {
+ //
+ // Multicast IP address to be converted to multicast MAC address.
+ //
+ PXE_IP_ADDR IP;
+} PXE_CPB_MCAST_IP_TO_MAC;
+
+typedef struct s_pxe_db_mcast_ip_to_mac {
+ //
+ // Multicast MAC address.
+ //
+ PXE_MAC_ADDR MAC;
+} PXE_DB_MCAST_IP_TO_MAC;
+
+typedef struct s_pxe_cpb_nvdata_sparse {
+ //
+ // NvData item list. Only items in this list will be updated.
+ //
+ struct {
+ //
+ // Non-volatile storage address to be changed.
+ //
+ UINT32 Addr;
+
+ //
+ // Data item to write into above storage address.
+ //
+ union {
+ UINT8 Byte;
+ UINT16 Word;
+ UINT32 Dword;
+ } Data;
+ } Item[MAX_EEPROM_LEN];
+}
+PXE_CPB_NVDATA_SPARSE;
+
+//
+// When using bulk update, the size of the CPB structure must be
+// the same size as the non-volatile NIC storage.
+//
+typedef union u_pxe_cpb_nvdata_bulk {
+ //
+ // Array of byte-wide data items.
+ //
+ UINT8 Byte[MAX_EEPROM_LEN << 2];
+
+ //
+ // Array of word-wide data items.
+ //
+ UINT16 Word[MAX_EEPROM_LEN << 1];
+
+ //
+ // Array of dword-wide data items.
+ //
+ UINT32 Dword[MAX_EEPROM_LEN];
+} PXE_CPB_NVDATA_BULK;
+
+typedef struct s_pxe_db_nvdata {
+ //
+ // Arrays of data items from non-volatile storage.
+ //
+ union {
+ //
+ // Array of byte-wide data items.
+ //
+ UINT8 Byte[MAX_EEPROM_LEN << 2];
+
+ //
+ // Array of word-wide data items.
+ //
+ UINT16 Word[MAX_EEPROM_LEN << 1];
+
+ //
+ // Array of dword-wide data items.
+ //
+ UINT32 Dword[MAX_EEPROM_LEN];
+ } Data;
+} PXE_DB_NVDATA;
+
+typedef struct s_pxe_db_get_status {
+ //
+ // Length of next receive frame (header + data). If this is zero,
+ // there is no next receive frame available.
+ //
+ UINT32 RxFrameLen;
+
+ //
+ // Reserved, set to zero.
+ //
+ UINT32 reserved;
+
+ //
+ // Addresses of transmitted buffers that need to be recycled.
+ //
+ UINT64 TxBuffer[MAX_XMIT_BUFFERS];
+} PXE_DB_GET_STATUS;
+
+typedef struct s_pxe_cpb_fill_header {
+ //
+ // Source and destination MAC addresses. These will be copied into
+ // the media header without doing byte swapping.
+ //
+ PXE_MAC_ADDR SrcAddr;
+ PXE_MAC_ADDR DestAddr;
+
+ //
+ // Address of first byte of media header. The first byte of packet data
+ // follows the last byte of the media header.
+ //
+ UINT64 MediaHeader;
+
+ //
+ // Length of packet data in bytes (not including the media header).
+ //
+ UINT32 PacketLen;
+
+ //
+ // Protocol type. This will be copied into the media header without
+ // doing byte swapping. Protocol type numbers can be obtained from
+ // the Assigned Numbers RFC 1700.
+ //
+ UINT16 Protocol;
+
+ //
+ // Length of the media header in bytes.
+ //
+ UINT16 MediaHeaderLen;
+} PXE_CPB_FILL_HEADER;
+
+#define PXE_PROTOCOL_ETHERNET_IP 0x0800
+#define PXE_PROTOCOL_ETHERNET_ARP 0x0806
+#define MAX_XMIT_FRAGMENTS 16
+
+typedef struct s_pxe_cpb_fill_header_fragmented {
+ //
+ // Source and destination MAC addresses. These will be copied into
+ // the media header without doing byte swapping.
+ //
+ PXE_MAC_ADDR SrcAddr;
+ PXE_MAC_ADDR DestAddr;
+
+ //
+ // Length of packet data in bytes (not including the media header).
+ //
+ UINT32 PacketLen;
+
+ //
+ // Protocol type. This will be copied into the media header without
+ // doing byte swapping. Protocol type numbers can be obtained from
+ // the Assigned Numbers RFC 1700.
+ //
+ PXE_MEDIA_PROTOCOL Protocol;
+
+ //
+ // Length of the media header in bytes.
+ //
+ UINT16 MediaHeaderLen;
+
+ //
+ // Number of packet fragment descriptors.
+ //
+ UINT16 FragCnt;
+
+ //
+ // Reserved, must be set to zero.
+ //
+ UINT16 reserved;
+
+ //
+ // Array of packet fragment descriptors. The first byte of the media
+ // header is the first byte of the first fragment.
+ //
+ struct {
+ //
+ // Address of this packet fragment.
+ //
+ UINT64 FragAddr;
+
+ //
+ // Length of this packet fragment.
+ //
+ UINT32 FragLen;
+
+ //
+ // Reserved, must be set to zero.
+ //
+ UINT32 reserved;
+ } FragDesc[MAX_XMIT_FRAGMENTS];
+}
+PXE_CPB_FILL_HEADER_FRAGMENTED;
+
+typedef struct s_pxe_cpb_transmit {
+ //
+ // Address of first byte of frame buffer. This is also the first byte
+ // of the media header.
+ //
+ UINT64 FrameAddr;
+
+ //
+ // Length of the data portion of the frame buffer in bytes. Do not
+ // include the length of the media header.
+ //
+ UINT32 DataLen;
+
+ //
+ // Length of the media header in bytes.
+ //
+ UINT16 MediaheaderLen;
+
+ //
+ // Reserved, must be zero.
+ //
+ UINT16 reserved;
+} PXE_CPB_TRANSMIT;
+
+typedef struct s_pxe_cpb_transmit_fragments {
+ //
+ // Length of packet data in bytes (not including the media header).
+ //
+ UINT32 FrameLen;
+
+ //
+ // Length of the media header in bytes.
+ //
+ UINT16 MediaheaderLen;
+
+ //
+ // Number of packet fragment descriptors.
+ //
+ UINT16 FragCnt;
+
+ //
+ // Array of frame fragment descriptors. The first byte of the first
+ // fragment is also the first byte of the media header.
+ //
+ struct {
+ //
+ // Address of this frame fragment.
+ //
+ UINT64 FragAddr;
+
+ //
+ // Length of this frame fragment.
+ //
+ UINT32 FragLen;
+
+ //
+ // Reserved, must be set to zero.
+ //
+ UINT32 reserved;
+ } FragDesc[MAX_XMIT_FRAGMENTS];
+}
+PXE_CPB_TRANSMIT_FRAGMENTS;
+
+typedef struct s_pxe_cpb_receive {
+ //
+ // Address of first byte of receive buffer. This is also the first byte
+ // of the frame header.
+ //
+ UINT64 BufferAddr;
+
+ //
+ // Length of receive buffer. This must be large enough to hold the
+ // received frame (media header + data). If the length of smaller than
+ // the received frame, data will be lost.
+ //
+ UINT32 BufferLen;
+
+ //
+ // Reserved, must be set to zero.
+ //
+ UINT32 reserved;
+} PXE_CPB_RECEIVE;
+
+typedef struct s_pxe_db_receive {
+ //
+ // Source and destination MAC addresses from media header.
+ //
+ PXE_MAC_ADDR SrcAddr;
+ PXE_MAC_ADDR DestAddr;
+
+ //
+ // Length of received frame. May be larger than receive buffer size.
+ // The receive buffer will not be overwritten. This is how to tell
+ // if data was lost because the receive buffer was too small.
+ //
+ UINT32 FrameLen;
+
+ //
+ // Protocol type from media header.
+ //
+ PXE_MEDIA_PROTOCOL Protocol;
+
+ //
+ // Length of media header in received frame.
+ //
+ UINT16 MediaHeaderLen;
+
+ //
+ // Type of receive frame.
+ //
+ PXE_FRAME_TYPE Type;
+
+ //
+ // Reserved, must be zero.
+ //
+ UINT8 reserved[7];
+
+} PXE_DB_RECEIVE;
+
+#pragma pack()
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/EfiSpec.h b/EdkCompatibilityPkg/Foundation/Include/EfiSpec.h new file mode 100644 index 0000000000..633c595db0 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/EfiSpec.h @@ -0,0 +1,51 @@ +/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ EfiSpec.h
+
+Abstract:
+
+ EFI master include file.
+
+ This is the main include file for EFI components. There should be
+ no defines or macros added to this file, other than the EFI version
+ information already in this file.
+
+ Don't add include files to the list for convenience, only add things
+ that are architectural. Don't add Protocols or GUID include files here
+
+--*/
+
+#ifndef _EFI_SPEC_H_
+#define _EFI_SPEC_H_
+
+#include "EfiCommon.h"
+#include "EfiApi.h"
+#include "EfiDevicePath.h"
+
+//
+// Check to make sure EFI_SPECIFICATION_VERSION and TIANO_RELEASE_VERSION are defined.
+//
+#if !defined(EFI_SPECIFICATION_VERSION)
+ #error EFI_SPECIFICATION_VERSION not defined
+#elif !defined(TIANO_RELEASE_VERSION)
+ #error TIANO_RELEASE_VERSION not defined
+#elif (TIANO_RELEASE_VERSION == 0)
+//
+// UEFI mode with no Tiano extensions is legal
+//
+#elif ((TIANO_RELEASE_VERSION < 0x00080005) && (EFI_SPECIFICATION_VERSION >= 0x00020000))
+ #error Illegal combination of EFI_SPECIFICATION_VERSION and TIANO_RELEASE_VERSION versions
+#endif
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/EfiStdArg.h b/EdkCompatibilityPkg/Foundation/Include/EfiStdArg.h new file mode 100644 index 0000000000..d125cedac7 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/EfiStdArg.h @@ -0,0 +1,75 @@ +/*++
+
+Copyright (c) 2004, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ EfiStdArg.h
+
+Abstract:
+
+ Support for variable length argument lists using the ANSI standard.
+
+ Since we are using the ANSI standard we used the standard nameing and
+ did not folow the coding convention
+
+ VA_LIST - typedef for argument list.
+ VA_START (VA_LIST Marker, argument before the ...) - Init Marker for use.
+ VA_END (VA_LIST Marker) - Clear Marker
+ VA_ARG (VA_LIST Marker, var arg size) - Use Marker to get an argumnet from
+ the ... list. You must know the size and pass it in this macro.
+
+ example:
+
+ UINTN
+ ExampleVarArg (
+ IN UINTN NumberOfArgs,
+ ...
+ )
+ {
+ VA_LIST Marker;
+ UINTN Index;
+ UINTN Result;
+
+ //
+ // Initialize the Marker
+ //
+ VA_START (Marker, NumberOfArgs);
+ for (Index = 0, Result = 0; Index < NumberOfArgs; Index++) {
+ //
+ // The ... list is a series of UINTN values, so average them up.
+ //
+ Result += VA_ARG (Marker, UINTN);
+ }
+
+ VA_END (Marker);
+ return Result
+ }
+
+--*/
+
+#ifndef _EFISTDARG_H_
+#define _EFISTDARG_H_
+
+#define _EFI_INT_SIZE_OF(n) ((sizeof (n) + sizeof (UINTN) - 1) &~(sizeof (UINTN) - 1))
+
+//
+// Also support coding convention rules for var arg macros
+//
+#ifndef VA_START
+
+typedef CHAR8 *VA_LIST;
+#define VA_START(ap, v) (ap = (VA_LIST) & (v) + _EFI_INT_SIZE_OF (v))
+#define VA_ARG(ap, t) (*(t *) ((ap += _EFI_INT_SIZE_OF (t)) - _EFI_INT_SIZE_OF (t)))
+#define VA_END(ap) (ap = (VA_LIST) 0)
+
+#endif
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/EfiTpm.h b/EdkCompatibilityPkg/Foundation/Include/EfiTpm.h new file mode 100644 index 0000000000..67379aa42d --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/EfiTpm.h @@ -0,0 +1,144 @@ +/*++
+
+Copyright (c) 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ EfiTpm.h
+
+Abstract:
+
+ EFI definition according to TCG_EFI_Platform_1_20_Final
+
+ See http://trustedcomputinggroup.org for latest specification updates
+
+--*/
+
+#ifndef _EFI_TPM_H_
+#define _EFI_TPM_H_
+
+#include <Tiano.h>
+
+//
+// The start of TPM return codes
+//
+#define TPM_BASE (EFI_MAX_BIT + (EFI_MAX_BIT >> 1))
+#include <IndustryStandard/Tpm12.h>
+
+//
+// Standard event types
+//
+#define EV_POST_CODE ((TCG_EVENTTYPE) 0x00000001)
+#define EV_SEPARATOR ((TCG_EVENTTYPE) 0x00000004)
+#define EV_S_CRTM_CONTENTS ((TCG_EVENTTYPE) 0x00000007)
+#define EV_S_CRTM_VERSION ((TCG_EVENTTYPE) 0x00000008)
+
+//
+// EFI specific event types
+//
+#define EV_EFI_EVENT_BASE ((TCG_EVENTTYPE) 0x80000000)
+#define EV_EFI_VARIABLE_DRIVER_CONFIG (EV_EFI_EVENT_BASE + 1)
+#define EV_EFI_VARIABLE_BOOT (EV_EFI_EVENT_BASE + 2)
+#define EV_EFI_BOOT_SERVICES_APPLICATION (EV_EFI_EVENT_BASE + 3)
+#define EV_EFI_BOOT_SERVICES_DRIVER (EV_EFI_EVENT_BASE + 4)
+#define EV_EFI_RUNTIME_SERVICES_DRIVER (EV_EFI_EVENT_BASE + 5)
+#define EV_EFI_GPT_EVENT (EV_EFI_EVENT_BASE + 6)
+#define EV_EFI_ACTION (EV_EFI_EVENT_BASE + 7)
+#define EV_EFI_PLATFORM_FIRMWARE_BLOB (EV_EFI_EVENT_BASE + 8)
+#define EV_EFI_HANDOFF_TABLES (EV_EFI_EVENT_BASE + 9)
+
+//
+// Set structure alignment to 1-byte
+//
+#pragma pack (push, 1)
+
+typedef UINT32 TCG_EVENTTYPE;
+
+#define TCG_DIGEST TPM_DIGEST
+#define TCG_PCRINDEX TPM_PCRINDEX
+
+//
+// TCG_PCR_EVENT
+//
+typedef struct tdTCG_PCR_EVENT {
+ TCG_PCRINDEX PCRIndex; // PCRIndex event extended to
+ TCG_EVENTTYPE EventType; // TCG EFI event type
+ TCG_DIGEST Digest; // Value extended into PCRIndex
+ UINT32 EventSize; // Size of the event data
+ UINT8 Event[1]; // The event data
+} TCG_PCR_EVENT;
+
+//
+// TCG_PCR_EVENT_HDR
+//
+typedef struct tdTCG_PCR_EVENT_HDR {
+ TCG_PCRINDEX PCRIndex;
+ TCG_EVENTTYPE EventType;
+ TCG_DIGEST Digest;
+ UINT32 EventSize;
+} TCG_PCR_EVENT_HDR;
+
+//
+// EFI_PLATFORM_FIRMWARE_BLOB
+//
+// BlobLength should be of type UINTN but we use UINT64 here
+// because PEI is 32-bit while DXE is 64-bit on x64 platforms
+//
+typedef struct tdEFI_PLATFORM_FIRMWARE_BLOB {
+ EFI_PHYSICAL_ADDRESS BlobBase;
+ UINT64 BlobLength;
+} EFI_PLATFORM_FIRMWARE_BLOB;
+
+//
+// EFI_IMAGE_LOAD_EVENT
+//
+// This structure is used in EV_EFI_BOOT_SERVICES_APPLICATION,
+// EV_EFI_BOOT_SERVICES_DRIVER and EV_EFI_RUNTIME_SERVICES_DRIVER
+//
+typedef struct tdEFI_IMAGE_LOAD_EVENT {
+ EFI_PHYSICAL_ADDRESS ImageLocationInMemory;
+ UINTN ImageLengthInMemory;
+ UINTN ImageLinkTimeAddress;
+ UINTN LengthOfDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL DevicePath[1];
+} EFI_IMAGE_LOAD_EVENT;
+
+//
+// EFI_HANDOFF_TABLE_POINTERS
+//
+// This structure is used in EV_EFI_HANDOFF_TABLES event to facilitate
+// the measurement of given configuration tables.
+//
+typedef struct tdEFI_HANDOFF_TABLE_POINTERS {
+ UINTN NumberOfTables;
+ EFI_CONFIGURATION_TABLE TableEntry[1];
+} EFI_HANDOFF_TABLE_POINTERS;
+
+//
+// EFI_VARIABLE_DATA
+//
+// This structure serves as the header for measuring variables. The name of the
+// variable (in Unicode format) should immediately follow, then the variable
+// data.
+//
+typedef struct tdEFI_VARIABLE_DATA {
+ EFI_GUID VariableName;
+ UINTN UnicodeNameLength;
+ UINTN VariableDataLength;
+ CHAR16 UnicodeName[1];
+ INT8 VariableData[1]; // Driver or platform-specific data
+} EFI_VARIABLE_DATA;
+
+//
+// Restore original structure alignment
+//
+#pragma pack (pop)
+
+#endif // _EFI_TPM_H_
diff --git a/EdkCompatibilityPkg/Foundation/Include/EfiVariable.h b/EdkCompatibilityPkg/Foundation/Include/EfiVariable.h new file mode 100644 index 0000000000..b2a96f4a48 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/EfiVariable.h @@ -0,0 +1,85 @@ +/*++
+
+Copyright (c) 2004, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ EfiVariable.h
+
+Abstract:
+
+ Header file for EFI Variable Services
+
+--*/
+
+#ifndef _EFI_VARIABLE_H_
+#define _EFI_VARIABLE_H_
+
+#define VARIABLE_STORE_SIGNATURE EFI_SIGNATURE_32 ('$', 'V', 'S', 'S')
+
+#define MAX_VARIABLE_SIZE 1024
+
+//
+// Enlarges the hardware error record maximum variable size to 32K bytes
+//
+#if (EFI_SPECIFICATION_VERSION >= 0x0002000A)
+#define MAX_HARDWARE_ERROR_VARIABLE_SIZE 0x8000
+#endif
+
+#define VARIABLE_DATA 0x55AA
+
+//
+// Variable Store Header flags
+//
+#define VARIABLE_STORE_FORMATTED 0x5a
+#define VARIABLE_STORE_HEALTHY 0xfe
+
+//
+// Variable Store Status
+//
+typedef enum {
+ EfiRaw,
+ EfiValid,
+ EfiInvalid,
+ EfiUnknown
+} VARIABLE_STORE_STATUS;
+
+//
+// Variable State flags
+//
+#define VAR_IN_DELETED_TRANSITION 0xfe // Variable is in obsolete transistion
+#define VAR_DELETED 0xfd // Variable is obsolete
+#define VAR_ADDED 0x7f // Variable has been completely added
+#define IS_VARIABLE_STATE(_c, _Mask) (BOOLEAN) (((~_c) & (~_Mask)) != 0)
+
+#pragma pack(1)
+
+typedef struct {
+ UINT32 Signature;
+ UINT32 Size;
+ UINT8 Format;
+ UINT8 State;
+ UINT16 Reserved;
+ UINT32 Reserved1;
+} VARIABLE_STORE_HEADER;
+
+typedef struct {
+ UINT16 StartId;
+ UINT8 State;
+ UINT8 Reserved;
+ UINT32 Attributes;
+ UINT32 NameSize;
+ UINT32 DataSize;
+ EFI_GUID VendorGuid;
+} VARIABLE_HEADER;
+
+#pragma pack()
+
+#endif // _EFI_VARIABLE_H_
diff --git a/EdkCompatibilityPkg/Foundation/Include/EfiWorkingBlockHeader.h b/EdkCompatibilityPkg/Foundation/Include/EfiWorkingBlockHeader.h new file mode 100644 index 0000000000..a67d041218 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/EfiWorkingBlockHeader.h @@ -0,0 +1,47 @@ +/*++
+
+Copyright (c) 2004 - 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ EfiWorkingBlockHeader.h
+
+Abstract:
+
+ Defines data structure that is the headers found at the runtime
+ updatable firmware volumes, such as the FileSystemGuid of the
+ working block, the header structure of the variable block, FTW
+ working block, or event log block.
+
+--*/
+
+#ifndef _EFI_WORKING_BLOCK_HEADER_H_
+#define _EFI_WORKING_BLOCK_HEADER_H_
+
+//
+// EFI Fault tolerant working block header
+// The header is immediately followed by the write queue.
+//
+typedef struct {
+ EFI_GUID Signature;
+ UINT32 Crc;
+ UINT8 WorkingBlockValid : 1;
+ UINT8 WorkingBlockInvalid : 1;
+#define WORKING_BLOCK_VALID 0x1
+#define WORKING_BLOCK_INVALID 0x2
+ UINT8 Reserved : 6;
+ UINT8 Reserved3[3];
+ UINT64 WriteQueueSize;
+ //
+ // UINT8 WriteQueue[WriteQueueSize];
+ //
+} EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER;
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/Ia32/EfiBind.h b/EdkCompatibilityPkg/Foundation/Include/Ia32/EfiBind.h new file mode 100644 index 0000000000..ae60a28e27 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/Ia32/EfiBind.h @@ -0,0 +1,269 @@ +/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ EfiBind.h
+
+Abstract:
+
+ Processor or Compiler specific defines and types for IA-32.
+ We are using the ANSI C 2000 _t type definitions for basic types.
+ This it technically a violation of the coding standard, but they
+ are used to make EfiTypes.h portable. Code other than EfiTypes.h
+ should never use any ANSI C 2000 _t integer types.
+
+--*/
+
+#ifndef _EFI_BIND_H_
+#define _EFI_BIND_H_
+
+#ifdef EFI_DEBUG
+
+#ifdef EFI_NT_EMULATOR
+
+#define EFI_DRIVER_ENTRY_POINT(InitFunction) \
+ EFI_STATUS \
+ EFIAPI \
+ InitFunction ( \
+ EFI_HANDLE ImageHandle, \
+ EFI_SYSTEM_TABLE *SystemTable \
+ ); \
+ \
+ UINTN \
+ __stdcall \
+ _DllMainCRTStartup ( \
+ UINTN Inst, \
+ UINTN reason_for_call, \
+ VOID *rserved \
+ ) \
+ { \
+ return 1; \
+ } \
+ \
+ EFI_STATUS \
+ __declspec( dllexport ) \
+ __cdecl \
+ InitializeDriver ( \
+ VOID *ImageHandle, \
+ VOID *SystemTable \
+ ) \
+ { \
+ return InitFunction(ImageHandle, SystemTable); \
+ }
+
+#define EFI_APPLICATION_ENTRY_POINT EFI_DRIVER_ENTRY_POINT
+
+#else
+
+#define EFI_DRIVER_ENTRY_POINT(InitFunction)
+#define EFI_APPLICATION_ENTRY_POINT EFI_DRIVER_ENTRY_POINT
+
+#endif
+
+#else
+
+#define EFI_DRIVER_ENTRY_POINT(InitFunction)
+#define EFI_APPLICATION_ENTRY_POINT EFI_DRIVER_ENTRY_POINT
+
+#endif
+
+
+
+
+
+//
+// Make sure we are useing the correct packing rules per EFI specification
+//
+#pragma pack()
+
+#if _MSC_EXTENSIONS
+
+//
+// Disable warning that make it impossible to compile at /W4
+// This only works for Microsoft* tools
+//
+
+//
+// Disabling bitfield type checking warnings.
+//
+#pragma warning ( disable : 4214 )
+
+//
+// Disabling the unreferenced formal parameter warnings.
+//
+#pragma warning ( disable : 4100 )
+
+//
+// Disable slightly different base types warning as CHAR8 * can not be set
+// to a constant string.
+//
+#pragma warning ( disable : 4057 )
+
+//
+// ASSERT(FALSE) or while (TRUE) are legal constructes so supress this warning
+//
+#pragma warning ( disable : 4127 )
+
+//
+// Int64ShllMod32 unreferenced inline function
+//
+#pragma warning ( disable : 4514 )
+
+//
+// Unreferenced formal parameter - We are object oriented, so we pass This even
+// if we don't need them.
+//
+#pragma warning ( disable : 4100 )
+
+//
+// This warning is caused by empty (after preprocessing) souce file.
+//
+#pragma warning ( disable : 4206 )
+
+
+#endif
+
+
+#if (__STDC_VERSION__ < 199901L)
+ //
+ // No ANSI C 2000 stdint.h integer width declarations, so define equivalents
+ //
+
+ #if _MSC_EXTENSIONS
+
+ //
+ // use Microsoft* C complier dependent interger width types
+ //
+ typedef unsigned __int64 uint64_t;
+ typedef __int64 int64_t;
+ typedef unsigned __int32 uint32_t;
+ typedef __int32 int32_t;
+ typedef unsigned short uint16_t;
+ typedef short int16_t;
+ typedef unsigned char uint8_t;
+ typedef char int8_t;
+ #else
+
+ //
+ // Assume standard IA-32 alignment.
+ // BugBug: Need to check portability of long long
+ //
+ typedef unsigned long long uint64_t;
+ typedef long long int64_t;
+ typedef unsigned int uint32_t;
+ typedef int int32_t;
+ typedef unsigned short uint16_t;
+ typedef short int16_t;
+ typedef unsigned char uint8_t;
+ typedef char int8_t;
+ #endif
+#else
+ //
+ // Use ANSI C 2000 stdint.h integer width declarations
+ //
+ #include "stdint.h"
+#endif
+
+//
+// Native integer size in stdint.h
+//
+typedef uint32_t uintn_t;
+typedef int32_t intn_t;
+
+//
+// Processor specific defines
+//
+#define EFI_MAX_BIT 0x80000000
+#define MAX_2_BITS 0xC0000000
+
+//
+// Maximum legal IA-32 address
+//
+#define EFI_MAX_ADDRESS 0xFFFFFFFF
+
+//
+// Bad pointer value to use in check builds.
+// if you see this value you are using uninitialized or free'ed data
+//
+#define EFI_BAD_POINTER 0xAFAFAFAF
+#define EFI_BAD_POINTER_AS_BYTE 0xAF
+
+//
+// Inject a break point in the code to assist debugging for NT Emulation Environment
+// For real hardware, just put in a halt loop. Don't do a while(1) because the
+// compiler will optimize away the rest of the function following, so that you run out in
+// the weeds if you skip over it with a debugger.
+//
+#define EFI_BREAKPOINT() __asm { int 3 }
+#define EFI_DEADLOOP() { volatile UINTN __iii; __iii = 1; while (__iii); }
+
+//
+// Memory Fence forces serialization, and is needed to support out of order
+// memory transactions. The Memory Fence is mainly used to make sure IO
+// transactions complete in a deterministic sequence, and to syncronize locks
+// an other MP code. Currently no memory fencing is required.
+//
+#define MEMORY_FENCE()
+
+//
+// Some compilers don't support the forward reference construct:
+// typedef struct XXXXX. The forward reference is required for
+// ANSI compatibility.
+//
+// The following macro provide a workaround for such cases.
+//
+
+
+#ifdef EFI_NO_INTERFACE_DECL
+ #define EFI_FORWARD_DECLARATION(x)
+#else
+ #define EFI_FORWARD_DECLARATION(x) typedef struct _##x x
+#endif
+
+
+//
+// Some C compilers optimize the calling conventions to increase performance.
+// _EFIAPI is used to make all public APIs follow the standard C calling
+// convention.
+//
+#if _MSC_EXTENSIONS
+ //
+ // Microsoft* compiler requires _EFIAPI useage, __cdecl is Microsoft* specific C.
+ //
+
+ #define _EFIAPI __cdecl
+#else
+ #define _EFIAPI
+#endif
+
+
+#ifdef _EFI_WINNT
+
+ #define EFI_SUPPRESS_BENIGN_REDEFINITION_OF_TYPE_WARNING() \
+ warning ( disable : 4142 )
+
+ #define EFI_DEFAULT_BENIGN_REDEFINITION_OF_TYPE_WARNING() \
+ warning ( default : 4142 )
+#else
+
+ #define EFI_SUPPRESS_BENIGN_REDEFINITION_OF_TYPE_WARNING() \
+ warning ( disable : 4068 )
+
+ #define EFI_DEFAULT_BENIGN_REDEFINITION_OF_TYPE_WARNING() \
+ warning ( default : 4068 )
+
+#endif
+
+
+
+#endif
+
diff --git a/EdkCompatibilityPkg/Foundation/Include/Ia32/EfiPeOptionalHeader.h b/EdkCompatibilityPkg/Foundation/Include/Ia32/EfiPeOptionalHeader.h new file mode 100644 index 0000000000..549d9f4fc4 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/Ia32/EfiPeOptionalHeader.h @@ -0,0 +1,38 @@ +/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ EfiPeOptionalHeader.h
+
+Abstract:
+ Defines the optional header in the PE image per the PE specification. This
+ file must be included only from within EfiImage.h since
+ EFI_IMAGE_DATA_DIRECTORY and EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES are defined
+ there.
+
+--*/
+
+#ifndef _EFI_PE_OPTIONAL_HEADER_H_
+#define _EFI_PE_OPTIONAL_HEADER_H_
+
+#define EFI_IMAGE_MACHINE_TYPE (EFI_IMAGE_MACHINE_IA32)
+
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
+ (((Machine) == EFI_IMAGE_MACHINE_IA32) || ((Machine) == EFI_IMAGE_MACHINE_EBC))
+
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_X64)
+
+#define EFI_IMAGE_NT_OPTIONAL_HDR_MAGIC EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC
+typedef EFI_IMAGE_OPTIONAL_HEADER32 EFI_IMAGE_OPTIONAL_HEADER;
+typedef EFI_IMAGE_NT_HEADERS32 EFI_IMAGE_NT_HEADERS;
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/Ia32/TianoBind.h b/EdkCompatibilityPkg/Foundation/Include/Ia32/TianoBind.h new file mode 100644 index 0000000000..edf599a27f --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/Ia32/TianoBind.h @@ -0,0 +1,102 @@ +/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ TianoBind.h
+
+Abstract:
+
+ Tiano's Processor or Compiler specific defines and types for IA-32
+ besides EfiBind.h.
+
+--*/
+
+#ifndef _TIANO_BIND_H_
+#define _TIANO_BIND_H_
+
+#include "EfiBind.h"
+
+#ifdef EFI_DEBUG
+
+#ifdef EFI_NT_EMULATOR
+
+#define EFI_DXE_ENTRY_POINT(InitFunction) \
+ VOID \
+ EFIAPI \
+ InitFunction ( \
+ IN VOID *HobStart \
+ ); \
+ \
+ UINTN \
+ __stdcall \
+ _DllMainCRTStartup ( \
+ UINTN Inst, \
+ UINTN reason_for_call, \
+ VOID *rserved \
+ ) \
+ { \
+ return 1; \
+ } \
+ \
+ VOID \
+ __declspec( dllexport ) \
+ __cdecl \
+ InitializeDriver ( \
+ VOID *Hob \
+ ) \
+ { \
+ InitFunction(Hob); \
+ }
+
+
+
+
+#define EFI_SMI_HANDLER_ENTRY_POINT(InitFunction) \
+ UINTN \
+ __stdcall \
+ _DllMainCRTStartup ( \
+ UINTN Inst, \
+ UINTN reason_for_call, \
+ VOID *rserved \
+ ) \
+ { \
+ return 1; \
+ } \
+ \
+ EFI_STATUS \
+ __declspec( dllexport ) \
+ __cdecl \
+ InitializeDriver ( \
+ VOID *ImageHandle, \
+ VOID *Smst, \
+ VOID *CommunicationBuffer, \
+ UINTN *SourceSize \
+ ) \
+ { \
+ return InitFunction(ImageHandle, Smst, CommunicationBuffer, SourceSize); \
+ }
+
+#else
+
+#define EFI_DXE_ENTRY_POINT(InitFunction)
+#define EFI_SMI_HANDLER_ENTRY_POINT(InitFunction)
+
+#endif
+
+#else
+
+#define EFI_DXE_ENTRY_POINT(InitFunction)
+#define EFI_SMI_HANDLER_ENTRY_POINT(InitFunction)
+
+#endif
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi.h new file mode 100644 index 0000000000..6a7246f72e --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi.h @@ -0,0 +1,31 @@ +/*++
+
+Copyright (c) 2004 - 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ Acpi.h
+
+Abstract:
+
+ This file contains some basic ACPI definitions that are consumed by drivers
+ that do not care about ACPI versions.
+
+--*/
+
+#ifndef _ACPI_H_
+#define _ACPI_H_
+
+#include "AcpiCommon.h"
+#include "Acpi1_0.h"
+#include "Acpi2_0.h"
+#include "Acpi3_0.h"
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi1_0.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi1_0.h new file mode 100644 index 0000000000..84c4147cc6 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi1_0.h @@ -0,0 +1,299 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ Acpi1_0.h
+
+Abstract:
+
+ ACPI 1.0b definitions from the ACPI Specification, revision 1.0b
+
+--*/
+
+#ifndef _ACPI_1_0_H_
+#define _ACPI_1_0_H_
+
+//
+// Statements that include other files
+//
+#include "AcpiCommon.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// ACPI 1.0b table structures
+//
+//
+// Root System Description Pointer Structure
+//
+typedef struct {
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Reserved;
+ UINT32 RsdtAddress;
+} EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header followed by a
+// variable number of UINT32 table pointers.
+//
+//
+// RSDT Revision (as defined in ACPI 1.0b spec.)
+//
+#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Fixed ACPI Description Table Structure (FADT)
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 IntModel;
+ UINT8 Reserved1;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 Reserved2;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 Reserved3;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT8 Reserved4;
+ UINT8 Reserved5;
+ UINT8 Reserved6;
+ UINT32 Flags;
+} EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE;
+
+//
+// FADT Version (as defined in ACPI 1.0b spec.)
+//
+#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_1_0_WBINVD (1 << 0)
+#define EFI_ACPI_1_0_WBINVD_FLUSH (1 << 1)
+#define EFI_ACPI_1_0_PROC_C1 (1 << 2)
+#define EFI_ACPI_1_0_P_LVL2_UP (1 << 3)
+#define EFI_ACPI_1_0_PWR_BUTTON (1 << 4)
+#define EFI_ACPI_1_0_SLP_BUTTON (1 << 5)
+#define EFI_ACPI_1_0_FIX_RTC (1 << 6)
+#define EFI_ACPI_1_0_RTC_S4 (1 << 7)
+#define EFI_ACPI_1_0_TMR_VAL_EXT (1 << 8)
+#define EFI_ACPI_1_0_DCK_CAP (1 << 9)
+
+//
+// Firmware ACPI Control Structure
+//
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT8 Reserved[40];
+} EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+//
+// Firmware Control Structure Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_1_0_S4BIOS_F (1 << 0)
+
+//
+// Multiple APIC Description Table header definition. The rest of the table
+// must be defined in a platform specific manner.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+//
+// MADT Revision (as defined in ACPI 1.0b spec.)
+//
+#define EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Multiple APIC Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_1_0_PCAT_COMPAT (1 << 0)
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x09 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC 0x00
+#define EFI_ACPI_1_0_IO_APIC 0x01
+#define EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE 0x02
+#define EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
+#define EFI_ACPI_1_0_LOCAL_APIC_NMI 0x04
+
+//
+// APIC Structure Definitions
+//
+//
+// Processor Local APIC Structure Definition
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 ApicId;
+ UINT32 Flags;
+} EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+//
+// Local APIC Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_1_0_LOCAL_APIC_ENABLED (1 << 0)
+
+//
+// IO APIC Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 SystemVectorBase;
+} EFI_ACPI_1_0_IO_APIC_STRUCTURE;
+
+//
+// Interrupt Source Override Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterruptVector;
+ UINT16 Flags;
+} EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+//
+// Non-Maskable Interrupt Source Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterruptVector;
+} EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+//
+// Local APIC NMI Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT16 Flags;
+ UINT8 LocalApicInti;
+} EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE;
+
+//
+// Smart Battery Description Table (SBST)
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
+} EFI_ACPI_1_0_SMART_BATTERY_DESCRIPTION_TABLE;
+
+//
+// Known table signatures
+//
+//
+// "RSD PTR " Root System Description Pointer
+//
+#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE 0x2052545020445352
+
+//
+// "APIC" Multiple APIC Description Table
+//
+#define EFI_ACPI_1_0_APIC_SIGNATURE 0x43495041
+
+//
+// "DSDT" Differentiated System Description Table
+//
+#define EFI_ACPI_1_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445344
+
+//
+// "FACS" Firmware ACPI Control Structure
+//
+#define EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE 0x53434146
+
+//
+// "FACP" Fixed ACPI Description Table
+//
+#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE 0x50434146
+
+//
+// "PSDT" Persistent System Description Table
+//
+#define EFI_ACPI_1_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445350
+
+//
+// "RSDT" Root System Description Table
+//
+#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445352
+
+//
+// "SBST" Smart Battery Specification Table
+//
+#define EFI_ACPI_1_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE 0x54534253
+
+//
+// "SSDT" Secondary System Description Table
+//
+#define EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445353
+
+#pragma pack()
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi2_0.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi2_0.h new file mode 100644 index 0000000000..60c2e40e5c --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi2_0.h @@ -0,0 +1,513 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ Acpi2_0.h
+
+Abstract:
+
+ ACPI 2.0 definitions from the ACPI Specification, revision 2.0
+
+--*/
+
+#ifndef _ACPI_2_0_H_
+#define _ACPI_2_0_H_
+
+//
+// Statements that include other files
+//
+#include "AcpiCommon.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// ACPI Specification Revision
+//
+#define EFI_ACPI_2_0_REVISION 0x02
+
+//
+// ACPI 2.0 Generic Address Space definition
+//
+typedef struct {
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 Reserved;
+ UINT64 Address;
+} EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_2_0_SYSTEM_MEMORY 0
+#define EFI_ACPI_2_0_SYSTEM_IO 1
+#define EFI_ACPI_2_0_PCI_CONFIGURATION_SPACE 2
+#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER 3
+#define EFI_ACPI_2_0_SMBUS 4
+#define EFI_ACPI_2_0_FUNCTIONAL_FIXED_HARDWARE 0x7F
+
+//
+// ACPI 2.0 table structures
+//
+//
+// Root System Description Pointer Structure
+//
+typedef struct {
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
+} EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+//
+// RSD_PTR Revision (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02
+
+//
+// Common table header, this prefaces all ACPI tables, including FACS, but
+// excluding the RSD PTR structure
+//
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_2_0_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header followed by a
+// variable number of UINT32 table pointers.
+//
+//
+// RSDT Revision (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header followed by a
+// variable number of UINT64 table pointers.
+//
+//
+// XSDT Revision (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Fixed ACPI Description Table Structure (FADT)
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT8 Reserved2[3];
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+} EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE;
+
+//
+// FADT Version (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x03
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_2_0_LEGACY_DEVICES (1 << 0)
+#define EFI_ACPI_2_0_8042 (1 << 1)
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_2_0_WBINVD (1 << 0)
+#define EFI_ACPI_2_0_WBINVD_FLUSH (1 << 1)
+#define EFI_ACPI_2_0_PROC_C1 (1 << 2)
+#define EFI_ACPI_2_0_P_LVL2_UP (1 << 3)
+#define EFI_ACPI_2_0_PWR_BUTTON (1 << 4)
+#define EFI_ACPI_2_0_SLP_BUTTON (1 << 5)
+#define EFI_ACPI_2_0_FIX_RTC (1 << 6)
+#define EFI_ACPI_2_0_RTC_S4 (1 << 7)
+#define EFI_ACPI_2_0_TMR_VAL_EXT (1 << 8)
+#define EFI_ACPI_2_0_DCK_CAP (1 << 9)
+#define EFI_ACPI_2_0_RESET_REG_SUP (1 << 10)
+#define EFI_ACPI_2_0_SEALED_CASE (1 << 11)
+#define EFI_ACPI_2_0_HEADLESS (1 << 12)
+#define EFI_ACPI_2_0_CPU_SW_SLP (1 << 13)
+
+//
+// Firmware ACPI Control Structure
+//
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved[31];
+} EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+//
+// FACS Version (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x01
+
+//
+// Firmware Control Structure Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_2_0_S4BIOS_F (1 << 0)
+
+//
+// Multiple APIC Description Table header definition. The rest of the table
+// must be defined in a platform specific manner.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+//
+// MADT Revision (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Multiple APIC Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_2_0_PCAT_COMPAT (1 << 0)
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x09 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC 0x00
+#define EFI_ACPI_2_0_IO_APIC 0x01
+#define EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE 0x02
+#define EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
+#define EFI_ACPI_2_0_LOCAL_APIC_NMI 0x04
+#define EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
+#define EFI_ACPI_2_0_IO_SAPIC 0x06
+#define EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC 0x07
+#define EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES 0x08
+
+//
+// APIC Structure Definitions
+//
+//
+// Processor Local APIC Structure Definition
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 ApicId;
+ UINT32 Flags;
+} EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+//
+// Local APIC Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED (1 << 0)
+
+//
+// IO APIC Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
+} EFI_ACPI_2_0_IO_APIC_STRUCTURE;
+
+//
+// Interrupt Source Override Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
+} EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+//
+// Non-Maskable Interrupt Source Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
+} EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+//
+// Local APIC NMI Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
+} EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE;
+
+//
+// Local APIC Address Override Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
+} EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+//
+// IO SAPIC Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
+} EFI_ACPI_2_0_IO_SAPIC_STRUCTURE;
+
+//
+// Local SAPIC Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+} EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+//
+// Platform Interrupt Sources Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 Reserved;
+} EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+//
+// Smart Battery Description Table (SBST)
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
+} EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE;
+
+//
+// SBST Version (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Embedded Controller Boot Resources Table (ECDT)
+// The table is followed by a null terminated ASCII string that contains
+// a fully qualified reference to the name space object.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
+} EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+//
+// ECDT Version (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
+
+//
+// Known table signatures
+//
+//
+// "RSD PTR " Root System Description Pointer
+//
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE 0x2052545020445352
+
+//
+// "SPIC" Multiple SAPIC Description Table
+//
+// BUGBUG: Don't know where this came from except SR870BN4 uses it.
+// #define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE 0x43495053
+//
+#define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE 0x43495041
+
+//
+// "BOOT" MS Simple Boot Spec
+//
+#define EFI_ACPI_2_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE 0x544F4F42
+
+//
+// "DBGP" MS Bebug Port Spec
+//
+#define EFI_ACPI_2_0_DEBUG_PORT_TABLE_SIGNATURE 0x50474244
+
+//
+// "DSDT" Differentiated System Description Table
+//
+#define EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445344
+
+//
+// "ECDT" Embedded Controller Boot Resources Table
+//
+#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE 0x54444345
+
+//
+// "ETDT" Event Timer Description Table
+//
+#define EFI_ACPI_2_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE 0x54445445
+
+//
+// "FACS" Firmware ACPI Control Structure
+//
+#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE 0x53434146
+
+//
+// "FACP" Fixed ACPI Description Table
+//
+#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE 0x50434146
+
+//
+// "APIC" Multiple APIC Description Table
+//
+#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE 0x43495041
+
+//
+// "PSDT" Persistent System Description Table
+//
+#define EFI_ACPI_2_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445350
+
+//
+// "RSDT" Root System Description Table
+//
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445352
+
+//
+// "SBST" Smart Battery Specification Table
+//
+#define EFI_ACPI_2_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE 0x54534253
+
+//
+// "SLIT" System Locality Information Table
+//
+#define EFI_ACPI_2_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE 0x54494C53
+
+//
+// "SPCR" Serial Port Concole Redirection Table
+//
+#define EFI_ACPI_2_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE 0x52435053
+
+//
+// "SRAT" Static Resource Affinity Table
+//
+#define EFI_ACPI_2_0_STATIC_RESOURCE_AFFINITY_TABLE_SIGNATURE 0x54415253
+
+//
+// "SSDT" Secondary System Description Table
+//
+#define EFI_ACPI_2_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445353
+
+//
+// "SPMI" Server Platform Management Interface Table
+//
+#define EFI_ACPI_2_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_SIGNATURE 0x494D5053
+
+//
+// "XSDT" Extended System Description Table
+//
+#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445358
+
+#pragma pack()
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi3_0.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi3_0.h new file mode 100644 index 0000000000..be4483ac68 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi3_0.h @@ -0,0 +1,681 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ Acpi3_0.h
+
+Abstract:
+
+ ACPI 3.0 definitions from the ACPI Specification Revision 3.0
+
+--*/
+
+#ifndef _ACPI_3_0_H_
+#define _ACPI_3_0_H_
+
+//
+// Statements that include other files
+//
+#include "AcpiCommon.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// ACPI Specification Revision
+//
+#define EFI_ACPI_3_0_REVISION 0x03
+
+//
+// ACPI 3.0 Generic Address Space definition
+//
+typedef struct {
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
+} EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_3_0_SYSTEM_MEMORY 0
+#define EFI_ACPI_3_0_SYSTEM_IO 1
+#define EFI_ACPI_3_0_PCI_CONFIGURATION_SPACE 2
+#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER 3
+#define EFI_ACPI_3_0_SMBUS 4
+#define EFI_ACPI_3_0_FUNCTIONAL_FIXED_HARDWARE 0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_3_0_UNDEFINED 0
+#define EFI_ACPI_3_0_BYTE 1
+#define EFI_ACPI_3_0_WORD 2
+#define EFI_ACPI_3_0_DWORD 3
+#define EFI_ACPI_3_0_QWORD 4
+
+//
+// ACPI 3.0 table structures
+//
+//
+// Root System Description Pointer Structure
+//
+typedef struct {
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
+} EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+//
+// RSD_PTR Revision (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 // ACPISpec30 (Revision 3.0) says current value is 2
+//
+// Common table header, this prefaces all ACPI tables, including FACS, but
+// excluding the RSD PTR structure
+//
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_3_0_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header followed by a
+// variable number of UINT32 table pointers.
+//
+//
+// RSDT Revision (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header followed by a
+// variable number of UINT64 table pointers.
+//
+//
+// XSDT Revision (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Fixed ACPI Description Table Structure (FADT)
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT8 Reserved2[3];
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+} EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE;
+
+//
+// FADT Version (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x04
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_3_0_PM_PROFILE_UNSPECIFIED 0
+#define EFI_ACPI_3_0_PM_PROFILE_DESKTOP 1
+#define EFI_ACPI_3_0_PM_PROFILE_MOBILE 2
+#define EFI_ACPI_3_0_PM_PROFILE_WORKSTATION 3
+#define EFI_ACPI_3_0_PM_PROFILE_ENTERPRISE_SERVER 4
+#define EFI_ACPI_3_0_PM_PROFILE_SOHO_SERVER 5
+#define EFI_ACPI_3_0_PM_PROFILE_APPLIANCE_PC 6
+#define EFI_ACPI_3_0_PM_PROFILE_PERFORMANCE_SERVER 7
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_LEGACY_DEVICES (1 << 0)
+#define EFI_ACPI_3_0_8042 (1 << 1)
+#define EFI_ACPI_3_0_VGA_NOT_PRESENT (1 << 2)
+#define EFI_ACPI_3_0_MSI_NOT_SUPPORTED (1 << 3)
+#define EFI_ACPI_3_0_PCIE_ASPM_CONTROLS (1 << 4)
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_WBINVD (1 << 0)
+#define EFI_ACPI_3_0_WBINVD_FLUSH (1 << 1)
+#define EFI_ACPI_3_0_PROC_C1 (1 << 2)
+#define EFI_ACPI_3_0_P_LVL2_UP (1 << 3)
+#define EFI_ACPI_3_0_PWR_BUTTON (1 << 4)
+#define EFI_ACPI_3_0_SLP_BUTTON (1 << 5)
+#define EFI_ACPI_3_0_FIX_RTC (1 << 6)
+#define EFI_ACPI_3_0_RTC_S4 (1 << 7)
+#define EFI_ACPI_3_0_TMR_VAL_EXT (1 << 8)
+#define EFI_ACPI_3_0_DCK_CAP (1 << 9)
+#define EFI_ACPI_3_0_RESET_REG_SUP (1 << 10)
+#define EFI_ACPI_3_0_SEALED_CASE (1 << 11)
+#define EFI_ACPI_3_0_HEADLESS (1 << 12)
+#define EFI_ACPI_3_0_CPU_SW_SLP (1 << 13)
+#define EFI_ACPI_3_0_PCI_EXP_WAK (1 << 14)
+#define EFI_ACPI_3_0_USE_PLATFORM_CLOCK (1 << 15)
+#define EFI_ACPI_3_0_S4_RTC_STS_VALID (1 << 16)
+#define EFI_ACPI_3_0_REMOTE_POWER_ON_CAPABLE (1 << 17)
+#define EFI_ACPI_3_0_FORCE_APIC_CLUSTER_MODEL (1 << 18)
+#define EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE (1 << 19)
+
+//
+// Firmware ACPI Control Structure
+//
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved[31];
+} EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+//
+// FACS Version (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x01
+
+//
+// Firmware Control Structure Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_S4BIOS_F (1 << 0)
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header followed by a
+// definition block.
+//
+#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+
+//
+// Multiple APIC Description Table header definition. The rest of the table
+// must be defined in a platform specific manner.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+//
+// MADT Revision (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x02
+
+//
+// Multiple APIC Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_PCAT_COMPAT (1 << 0)
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x09 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC 0x00
+#define EFI_ACPI_3_0_IO_APIC 0x01
+#define EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE 0x02
+#define EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
+#define EFI_ACPI_3_0_LOCAL_APIC_NMI 0x04
+#define EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
+#define EFI_ACPI_3_0_IO_SAPIC 0x06
+#define EFI_ACPI_3_0_LOCAL_SAPIC 0x07
+#define EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES 0x08
+
+//
+// APIC Structure Definitions
+//
+//
+// Processor Local APIC Structure Definition
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 ApicId;
+ UINT32 Flags;
+} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+//
+// Local APIC Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_3_0_LOCAL_APIC_ENABLED (1 << 0)
+
+//
+// IO APIC Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
+} EFI_ACPI_3_0_IO_APIC_STRUCTURE;
+
+//
+// Interrupt Source Override Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
+} EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+//
+// Platform Interrupt Sources Structure Definition
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
+} EFI_ACPI_3_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_POLARITY (3 << 0)
+#define EFI_ACPI_3_0_TRIGGER_MODE (3 << 2)
+
+//
+// Non-Maskable Interrupt Source Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
+} EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+//
+// Local APIC NMI Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
+} EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE;
+
+//
+// Local APIC Address Override Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
+} EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+//
+// IO SAPIC Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
+} EFI_ACPI_3_0_IO_SAPIC_STRUCTURE;
+
+//
+// Local SAPIC Structure
+// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
+} EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+//
+// Platform Interrupt Sources Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+} EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+//
+// Platform Interrupt Source Flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_CPEI_PROCESSOR_OVERRIDE (1 << 0)
+
+//
+// Smart Battery Description Table (SBST)
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
+} EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE;
+
+//
+// SBST Version (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Embedded Controller Boot Resources Table (ECDT)
+// The table is followed by a null terminated ASCII string that contains
+// a fully qualified reference to the name space object.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
+} EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+//
+// ECDT Version (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
+
+//
+// System Resource Affinity Table (SRAT. The rest of the table
+// must be defined in a platform specific manner.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; // Must be set to 1
+ UINT64 Reserved2;
+} EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+//
+// SRAT Version (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x02
+
+//
+// SRAT structure types.
+// All other values between 0x02 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00
+#define EFI_ACPI_3_0_MEMORY_AFFINITY 0x01
+
+//
+// Processor Local APIC/SAPIC Affinity Structure Definition
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT8 Reserved[4];
+} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+//
+// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+//
+// Memory Affinity Structure Definition
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
+} EFI_ACPI_3_0_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_3_0_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_3_0_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_3_0_MEMORY_NONVOLATILE (1 << 2)
+
+//
+// System Locality Distance Information Table (SLIT).
+// The rest of the table is a matrix.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
+} EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+//
+// SLIT Version (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01
+
+//
+// Known table signatures
+//
+//
+// "RSD PTR " Root System Description Pointer
+//
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE 0x2052545020445352
+
+//
+// "APIC" Multiple APIC Description Table
+//
+#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE 0x43495041
+
+//
+// "DSDT" Differentiated System Description Table
+//
+#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445344
+
+//
+// "ECDT" Embedded Controller Boot Resources Table
+//
+#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE 0x54444345
+
+//
+// "FACP" Fixed ACPI Description Table
+//
+#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE 0x50434146
+
+//
+// "FACS" Firmware ACPI Control Structure
+//
+#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE 0x53434146
+
+//
+// "PSDT" Persistent System Description Table
+//
+#define EFI_ACPI_3_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445350
+
+//
+// "RSDT" Root System Description Table
+//
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445352
+
+//
+// "SBST" Smart Battery Specification Table
+//
+#define EFI_ACPI_3_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE 0x54534253
+
+//
+// "SLIT" System Locality Information Table
+//
+#define EFI_ACPI_3_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE 0x54494C53
+
+//
+// "SRAT" System Resource Affinity Table
+//
+#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE 0x54415253
+
+//
+// "SSDT" Secondary System Description Table
+//
+#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445353
+
+//
+// "XSDT" Extended System Description Table
+//
+#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445358
+
+//
+// "BOOT" MS Simple Boot Spec
+//
+#define EFI_ACPI_3_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE 0x544F4F42
+
+//
+// "CPEP" Corrected Platform Error Polling Table
+// See
+//
+#define EFI_ACPI_3_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE 0x50455043
+
+//
+// "DBGP" MS Debug Port Spec
+//
+#define EFI_ACPI_3_0_DEBUG_PORT_TABLE_SIGNATURE 0x50474244
+
+//
+// "ETDT" Event Timer Description Table
+//
+#define EFI_ACPI_3_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE 0x54445445
+
+//
+// "HPET" IA-PC High Precision Event Timer Table
+//
+#define EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE 0x54455048
+
+//
+// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+//
+#define EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE 0x4746434D
+
+//
+// "SPCR" Serial Port Concole Redirection Table
+//
+#define EFI_ACPI_3_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE 0x52435053
+
+//
+// "SPMI" Server Platform Management Interface Table
+//
+#define EFI_ACPI_3_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE 0x494D5053
+
+//
+// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+//
+#define EFI_ACPI_3_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE 0x41504354
+
+//
+// "WDRT" Watchdog Resource Table
+//
+#define EFI_ACPI_3_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE 0x54524457
+
+#pragma pack()
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/AcpiCommon.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/AcpiCommon.h new file mode 100644 index 0000000000..945e787788 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/AcpiCommon.h @@ -0,0 +1,98 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ AcpiCommon.h
+
+Abstract:
+
+ This file contains some basic ACPI definitions that are consumed by drivers
+ that do not care about ACPI versions.
+
+--*/
+
+#ifndef _ACPI_COMMON_H_
+#define _ACPI_COMMON_H_
+
+#include "Tiano.h"
+
+//
+// Common table header, this prefaces all ACPI tables, including FACS, but
+// excluding the RSD PTR structure
+//
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_COMMON_HEADER;
+
+//
+// Common ACPI description table header. This structure prefaces most ACPI tables.
+//
+#pragma pack(1)
+
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT8 Revision;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT64 OemTableId;
+ UINT32 OemRevision;
+ UINT32 CreatorId;
+ UINT32 CreatorRevision;
+} EFI_ACPI_DESCRIPTION_HEADER;
+
+#pragma pack()
+//
+// Define for Pci Host Bridge Resource Allocation
+//
+#define ACPI_ADDRESS_SPACE_DESCRIPTOR 0x8A
+#define ACPI_END_TAG_DESCRIPTOR 0x79
+
+#define ACPI_ADDRESS_SPACE_TYPE_MEM 0x00
+#define ACPI_ADDRESS_SPACE_TYPE_IO 0x01
+#define ACPI_ADDRESS_SPACE_TYPE_BUS 0x02
+
+//
+// Make sure structures match spec
+//
+#pragma pack(1)
+
+typedef struct {
+ UINT8 Desc;
+ UINT16 Len;
+ UINT8 ResType;
+ UINT8 GenFlag;
+ UINT8 SpecificFlag;
+ UINT64 AddrSpaceGranularity;
+ UINT64 AddrRangeMin;
+ UINT64 AddrRangeMax;
+ UINT64 AddrTranslationOffset;
+ UINT64 AddrLen;
+} EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR;
+
+typedef struct {
+ UINT8 Desc;
+ UINT8 Checksum;
+} EFI_ACPI_END_TAG_DESCRIPTOR;
+
+//
+// General use definitions
+//
+#define EFI_ACPI_RESERVED_BYTE 0x00
+#define EFI_ACPI_RESERVED_WORD 0x0000
+#define EFI_ACPI_RESERVED_DWORD 0x00000000
+#define EFI_ACPI_RESERVED_QWORD 0x0000000000000000
+
+#pragma pack()
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/AlertStandardFormatTable.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/AlertStandardFormatTable.h new file mode 100644 index 0000000000..f750a63b40 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/AlertStandardFormatTable.h @@ -0,0 +1,123 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ AlertStandardFormatTable.h
+
+Abstract:
+
+ ACPI Alert Standard Format Description Table ASF! as described
+ in the ASF2.0 Specification
+
+--*/
+
+#ifndef _ALERT_STANDARD_FORMAT_TABLE_H
+#define _ALERT_STANDARD_FORMAT_TABLE_H
+
+#include "Acpi2_0.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack (1)
+
+//
+// Information Record header that appears at the beginning of each record
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 RecordLength;
+} EFI_ACPI_ASF_RECORD_HEADER;
+
+//
+// This structure contains information that identifies the system type
+// and configuration
+//
+typedef struct {
+ EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
+ UINT8 MinWatchDogResetValue;
+ UINT8 MinPollingInterval;
+ UINT16 SystemID;
+ UINT32 IANAManufactureID;
+ UINT8 FeatureFlags;
+ UINT8 Reserved[3];
+} EFI_ACPI_ASF_INFO;
+
+//
+// Alert sensors definition
+//
+#define ASF_ALRT_SENSOR_ARRAY_LENGTH 36
+
+typedef struct {
+ EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
+ UINT8 AssertionEventBitMask;
+ UINT8 DeassertionEventBitMask;
+ UINT8 NumberOfAlerts;
+ UINT8 ArrayElementLength;
+ UINT8 DeviceArray[ASF_ALRT_SENSOR_ARRAY_LENGTH];
+} EFI_ACPI_ASF_ALRT;
+
+//
+// Alert Remote Control System Actions
+//
+#define ASF_RCTL_DEVICES_ARRAY_LENGTH 16
+typedef struct {
+ EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
+ UINT8 NumberOfControls;
+ UINT8 ArrayElementLength;
+ UINT16 RctlReserved;
+ UINT8 ControlArray[ASF_RCTL_DEVICES_ARRAY_LENGTH];
+} EFI_ACPI_ASF_RCTL;
+
+//
+// Remote Control Capabilities
+//
+typedef struct {
+ EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
+ UINT8 RemoteControlCapabilities[7];
+ UINT8 RMCPCompletionCode;
+ UINT32 RMCPIANA;
+ UINT8 RMCPSpecialCommand;
+ UINT8 RMCPSpecialCommandParameter[2];
+ UINT8 RMCPBootOptions[2];
+ UINT8 RMCPOEMParameters[2];
+} EFI_ACPI_ASF_RMCP;
+
+//
+// SMBus Devices with fixed addresses
+//
+#define ASF_ADDR_DEVICE_ARRAY_LENGTH 16
+typedef struct {
+ EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
+ UINT8 SEEPROMAddress;
+ UINT8 NumberOfDevices;
+ UINT8 FixedSmbusAddresses[ASF_ADDR_DEVICE_ARRAY_LENGTH];
+} EFI_ACPI_ASF_ADDR;
+
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_ASF_INFO AsfInfo;
+ EFI_ACPI_ASF_ALRT AsfAlert;
+ EFI_ACPI_ASF_RCTL AsfRctl;
+ EFI_ACPI_ASF_RMCP AsfRmcp;
+ EFI_ACPI_ASF_ADDR AsfAddr;
+} EFI_ACPI_1_0_ASF_DESCRIPTION_TABLE;
+
+//
+// "ASF!" ASF Description Table Signature
+//
+#define EFI_ACPI_1_0_ASF_DESCRIPTION_TABLE_SIGNATURE 0x21465341
+
+#pragma pack ()
+
+#endif // _ALERT_STANDARD_FORMAT_TABLE_H
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/DMARemappingReportingTable.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/DMARemappingReportingTable.h new file mode 100644 index 0000000000..78162c4196 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/DMARemappingReportingTable.h @@ -0,0 +1,202 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ DMARemappingReportingTable.h
+
+Abstract:
+
+ The definition for ACPI DMA-Remapping Reporting (DMAR) Table.
+ It is defined in "Intel VT for Direct IO Architecture Specification".
+
+--*/
+
+#ifndef _EFI_DMA_REMAPPING_REPORTING_TABLE_H_
+#define _EFI_DMA_REMAPPING_REPORTING_TABLE_H_
+
+#include "AcpiCommon.h"
+
+//
+// "DMAR" DMAR Description Table Signature
+//
+#define EFI_ACPI_DMAR_DESCRIPTION_TABLE_SIGNATURE 0x52414d44
+
+//
+// DMAR Revision
+//
+#define EFI_ACPI_DMAR_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Ensure proper structure formats
+//
+#pragma pack (1)
+
+//
+// Definition for DMA Remapping Structure Types
+//
+#define EFI_ACPI_DMA_REMAPPING_STRUCTURE_TYPE_DRHD 0
+#define EFI_ACPI_DMA_REMAPPING_STRUCTURE_TYPE_RMRR 1
+#define EFI_ACPI_DMA_REMAPPING_STRUCTURE_TYPE_ATSR 2
+
+//
+// Definition for DMA Remapping Structure Header
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+} EFI_ACPI_DMAR_STRUCTURE_HEADER;
+
+//
+// Definition for DMA-Remapping PCI Path
+//
+typedef struct {
+ UINT8 Device;
+ UINT8 Function;
+} EFI_ACPI_DMAR_PCI_PATH;
+
+//
+// Definition for DMA-Remapping Device Scope Entry Structure
+//
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_ENDPOINT 0x01
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_BRIDGE 0x02
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_IOAPIC 0x03
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_MSI_CAPABLE_HPET 0x04
+typedef struct {
+ UINT8 DeviceScopeEntryType;
+ UINT8 Length;
+ UINT16 Reserved_2;
+ UINT8 EnumerationID;
+ UINT8 StartingBusNumber;
+} EFI_ACPI_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE;
+
+//
+// Definition for DMA-Remapping Hardware Definition (DRHD) Structure
+//
+#define EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_ALL_SET 0x1
+#define EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_ALL_CLEAR 0x0
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT8 Flags;
+ UINT8 Reserved_5;
+ UINT16 SegmentNumber;
+ UINT64 RegisterBaseAddress;
+} EFI_ACPI_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE;
+
+//
+// Definition for Reserved Memory Region Reporting (RMRR) Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT8 Reserved_4[2];
+ UINT16 SegmentNumber;
+ UINT64 ReservedMemoryRegionBaseAddress;
+ UINT64 ReservedMemoryRegionLimitAddress;
+} EFI_ACPI_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE;
+
+//
+// Definition for Root Port ATS Capability Reporting (ATSR) Structure
+//
+#define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS_SET 0x1
+#define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS_CLEAR 0x0
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT8 Flags;
+ UINT8 Reserved_5;
+ UINT16 SegmentNumber;
+} EFI_ACPI_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE;
+
+//
+// Definition for DMA Remapping Structure
+//
+typedef union {
+ EFI_ACPI_DMAR_STRUCTURE_HEADER DMARStructureHeader;
+ EFI_ACPI_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE DMARHardwareUnitDefinition;
+ EFI_ACPI_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE DMARReservedMemoryRegionReporting;
+ EFI_ACPI_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE DMARRootPortATSCapabilityReporting;
+} EFI_ACPI_DMA_REMAPPING_STRUCTURE;
+
+//
+// Definition for DMA-Remapping Reporting ACPI Table
+//
+#define EFI_ACPI_DMAR_TABLE_FLAGS_INTR_REMAP_SET 0x01
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 HostAddressWidth;
+ UINT8 Flags;
+ UINT8 Reserved_38[10];
+} EFI_ACPI_DMAR_DESCRIPTION_TABLE;
+
+//
+// The Platform specific definition can be as follows:
+// NOTE: we use /**/ as comment for user convenience to copy it.
+//
+
+/*
+
+//
+// Dmar.h
+//
+
+#define EFI_ACPI_MAX_NUM_PCI_PATH_ENTRIES 0x01 // user need to update
+typedef struct {
+ EFI_ACPI_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE Header;
+ EFI_ACPI_DMAR_PCI_PATH PciPath[EFI_ACPI_MAX_NUM_PCI_PATH_ENTRIES];
+} EFI_ACPI_3_0_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE;
+
+#define EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_DHRD_ENTRY 0x01 // user need to update
+typedef struct {
+ EFI_ACPI_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE Header;
+ EFI_ACPI_3_0_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE DeviceScopeEntry[EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_DHRD_ENTRY];
+} EFI_ACPI_3_0_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE;
+
+#define EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_RMRR_ENTRY 0x01 // user need to update
+typedef struct {
+ EFI_ACPI_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE Header;
+ EFI_ACPI_3_0_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE DeviceScopeEntry[EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_RMRR_ENTRY];
+} EFI_ACPI_3_0_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE;
+
+#define EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_ATSR_ENTRY 0x01 // user need to update
+typedef struct {
+ EFI_ACPI_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE Header;
+ EFI_ACPI_3_0_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE DeviceScopeEntry[EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_ATSR_ENTRY];
+} EFI_ACPI_3_0_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE;
+
+#define EFI_ACPI_DMAR_DHRD_ENTRY_COUNT 0x1 // user need to update
+#define EFI_ACPI_DMAR_RMRR_ENTRY_COUNT 0x1 // user need to update
+#define EFI_ACPI_DMAR_ATSR_ENTRY_COUNT 0x1 // user need to update
+
+typedef struct {
+ EFI_ACPI_DMAR_DESCRIPTION_TABLE Header;
+
+#if EFI_ACPI_3_0_DMAR_DHRD_ENTRY_COUNT > 0
+ EFI_ACPI_3_0_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE Dhrd[EFI_ACPI_DMAR_DHRD_ENTRY_COUNT];
+#endif
+
+#if EFI_ACPI_3_0_DMAR_RMRR_ENTRY_COUNT > 0
+ EFI_ACPI_3_0_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE Rmrr[EFI_ACPI_DMAR_RMRR_ENTRY_COUNT];
+#endif
+
+#if EFI_ACPI_3_0_DMAR_ATSR_ENTRY_COUNT > 0
+ EFI_ACPI_3_0_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE Atsr[EFI_ACPI_DMAR_ATSR_ENTRY_COUNT];
+#endif
+
+} EFI_ACPI_3_0_DMA_REMAPPING_REPORTING_TABLE;
+
+*/
+
+#pragma pack()
+
+#endif
+
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/HighPrecisionEventTimerTable.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/HighPrecisionEventTimerTable.h new file mode 100644 index 0000000000..ee23907633 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/HighPrecisionEventTimerTable.h @@ -0,0 +1,62 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ HighPrecisionEventTimerTable.h
+
+Abstract:
+
+ ACPI high precision event timer table definition, defined at
+ Intel IA-PC HPET (High Precision Event Timers) Specification.
+
+--*/
+
+#ifndef _HIGH_PRECISION_EVENT_TIMER_TABLE_H_
+#define _HIGH_PRECISION_EVENT_TIMER_TABLE_H_
+
+//
+// Include files
+//
+#include "Acpi2_0.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// High Precision Event Timer Table header definition.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 EventTimerBlockId;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddressLower32Bit;
+ UINT8 HpetNumber;
+ UINT16 MainCounterMinimumClockTickInPeriodicMode;
+ UINT8 PageProtectionAndOemAttribute;
+} EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER;
+
+//
+// HPET Revision (defined in spec)
+//
+#define EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION 0x01
+
+//
+// Page protection setting
+// Values 3 through 15 are reserved for use by the specification
+//
+#define EFI_ACPI_NO_PAGE_PROTECTION 0
+#define EFI_ACPI_4KB_PAGE_PROTECTION 1
+#define EFI_ACPI_64KB_PAGE_PROTECTION 2
+
+#pragma pack()
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/LegacyBiosMpTable.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/LegacyBiosMpTable.h new file mode 100644 index 0000000000..bf484a7541 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/LegacyBiosMpTable.h @@ -0,0 +1,283 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ LegacyBiosMpTable.h
+
+Abstract:
+ Defives data structures per Multi Processor Specification Ver 1.4.
+
+--*/
+
+#ifndef LEGACY_BIOS_MPTABLE_H_
+#define LEGACY_BIOS_MPTABLE_H_
+
+#include "Tiano.h"
+
+#define EFI_LEGACY_MP_TABLE_REV_1_4 0x04
+
+//
+// Define MP table structures. All are packed.
+//
+#pragma pack(push, 1)
+
+#define EFI_LEGACY_MP_TABLE_FLOATING_POINTER_SIGNATURE EFI_SIGNATURE_32 ('_', 'M', 'P', '_')
+typedef struct {
+ UINT32 Signature;
+ UINT32 PhysicalAddress;
+ UINT8 Length;
+ UINT8 SpecRev;
+ UINT8 Checksum;
+ UINT8 FeatureByte1;
+ struct {
+ UINT32 Reserved1 : 6;
+ UINT32 MutipleClk : 1;
+ UINT32 Imcr : 1;
+ UINT32 Reserved2 : 24;
+ } FeatureByte2_5;
+} EFI_LEGACY_MP_TABLE_FLOATING_POINTER;
+
+#define EFI_LEGACY_MP_TABLE_HEADER_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'M', 'P')
+typedef struct {
+ UINT32 Signature;
+ UINT16 BaseTableLength;
+ UINT8 SpecRev;
+ UINT8 Checksum;
+ CHAR8 OemId[8];
+ CHAR8 OemProductId[12];
+ UINT32 OemTablePointer;
+ UINT16 OemTableSize;
+ UINT16 EntryCount;
+ UINT32 LocalApicAddress;
+ UINT16 ExtendedTableLength;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved;
+} EFI_LEGACY_MP_TABLE_HEADER;
+
+typedef struct {
+ UINT8 EntryType;
+} EFI_LEGACY_MP_TABLE_ENTRY_TYPE;
+
+//
+// Entry Type 0: Processor.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_PROCESSOR 0x00
+typedef struct {
+ UINT8 EntryType;
+ UINT8 Id;
+ UINT8 Ver;
+ struct {
+ UINT8 Enabled : 1;
+ UINT8 Bsp : 1;
+ UINT8 Reserved : 6;
+ } Flags;
+ struct {
+ UINT32 Stepping : 4;
+ UINT32 Model : 4;
+ UINT32 Family : 4;
+ UINT32 Reserved : 20;
+ } Signature;
+ struct {
+ UINT32 Fpu : 1;
+ UINT32 Reserved1 : 6;
+ UINT32 Mce : 1;
+ UINT32 Cx8 : 1;
+ UINT32 Apic : 1;
+ UINT32 Reserved2 : 22;
+ } Features;
+ UINT32 Reserved1;
+ UINT32 Reserved2;
+} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR;
+
+//
+// Entry Type 1: Bus.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_BUS 0x01
+typedef struct {
+ UINT8 EntryType;
+ UINT8 Id;
+ CHAR8 TypeString[6];
+} EFI_LEGACY_MP_TABLE_ENTRY_BUS;
+
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUS "CBUS " // Corollary CBus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUSII "CBUSII" // Corollary CBUS II
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_EISA "EISA " // Extended ISA
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_FUTURE "FUTURE" // IEEE FutureBus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_INTERN "INTERN" // Internal bus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_ISA "ISA " // Industry Standard Architecture
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBI "MBI " // Multibus I
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBII "MBII " // Multibus II
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MCA "MCA " // Micro Channel Architecture
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPI "MPI " // MPI
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPSA "MPSA " // MPSA
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_NUBUS "NUBUS " // Apple Macintosh NuBus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCI "PCI " // Peripheral Component Interconnect
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCMCIA "PCMCIA" // PC Memory Card International Assoc.
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_TC "TC " // DEC TurboChannel
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VL "VL " // VESA Local Bus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VME "VME " // VMEbus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_XPRESS "XPRESS" // Express System Bus
+//
+// Entry Type 2: I/O APIC.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IOAPIC 0x02
+typedef struct {
+ UINT8 EntryType;
+ UINT8 Id;
+ UINT8 Ver;
+ struct {
+ UINT8 Enabled : 1;
+ UINT8 Reserved : 7;
+ } Flags;
+ UINT32 Address;
+} EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC;
+
+//
+// Entry Type 3: I/O Interrupt Assignment.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IO_INT 0x03
+typedef struct {
+ UINT8 EntryType;
+ UINT8 IntType;
+ struct {
+ UINT16 Polarity : 2;
+ UINT16 Trigger : 2;
+ UINT16 Reserved : 12;
+ } Flags;
+ UINT8 SourceBusId;
+ union {
+ struct {
+ UINT8 IntNo : 2;
+ UINT8 Dev : 5;
+ UINT8 Reserved : 1;
+ } fields;
+ UINT8 byte;
+ } SourceBusIrq;
+ UINT8 DestApicId;
+ UINT8 DestApicIntIn;
+} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT;
+
+typedef enum {
+ EfiLegacyMpTableEntryIoIntTypeInt = 0,
+ EfiLegacyMpTableEntryIoIntTypeNmi = 1,
+ EfiLegacyMpTableEntryIoIntTypeSmi = 2,
+ EfiLegacyMpTableEntryIoIntTypeExtInt= 3,
+} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_TYPE;
+
+typedef enum {
+ EfiLegacyMpTableEntryIoIntFlagsPolaritySpec = 0x0,
+ EfiLegacyMpTableEntryIoIntFlagsPolarityActiveHigh = 0x1,
+ EfiLegacyMpTableEntryIoIntFlagsPolarityReserved = 0x2,
+ EfiLegacyMpTableEntryIoIntFlagsPolarityActiveLow = 0x3,
+} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_POLARITY;
+
+typedef enum {
+ EfiLegacyMpTableEntryIoIntFlagsTriggerSpec = 0x0,
+ EfiLegacyMpTableEntryIoIntFlagsTriggerEdge = 0x1,
+ EfiLegacyMpTableEntryIoIntFlagsTriggerReserved = 0x2,
+ EfiLegacyMpTableEntryIoIntFlagsTriggerLevel = 0x3,
+} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_TRIGGER;
+
+//
+// Entry Type 4: Local Interrupt Assignment.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_LOCAL_INT 0x04
+typedef struct {
+ UINT8 EntryType;
+ UINT8 IntType;
+ struct {
+ UINT16 Polarity : 2;
+ UINT16 Trigger : 2;
+ UINT16 Reserved : 12;
+ } Flags;
+ UINT8 SourceBusId;
+ UINT8 SourceBusIrq;
+ UINT8 DestApicId;
+ UINT8 DestApicIntIn;
+} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT;
+
+typedef enum {
+ EfiLegacyMpTableEntryLocalIntTypeInt = 0,
+ EfiLegacyMpTableEntryLocalIntTypeNmi = 1,
+ EfiLegacyMpTableEntryLocalIntTypeSmi = 2,
+ EfiLegacyMpTableEntryLocalIntTypeExtInt = 3,
+} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_TYPE;
+
+typedef enum {
+ EfiLegacyMpTableEntryLocalIntFlagsPolaritySpec = 0x0,
+ EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveHigh= 0x1,
+ EfiLegacyMpTableEntryLocalIntFlagsPolarityReserved = 0x2,
+ EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveLow = 0x3,
+} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_POLARITY;
+
+typedef enum {
+ EfiLegacyMpTableEntryLocalIntFlagsTriggerSpec = 0x0,
+ EfiLegacyMpTableEntryLocalIntFlagsTriggerEdge = 0x1,
+ EfiLegacyMpTableEntryLocalIntFlagsTriggerReserved = 0x2,
+ EfiLegacyMpTableEntryLocalIntFlagsTriggerLevel = 0x3,
+} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_TRIGGER;
+
+//
+// Entry Type 128: System Address Space Mapping.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_SYS_ADDR_SPACE_MAPPING 0x80
+typedef struct {
+ UINT8 EntryType;
+ UINT8 Length;
+ UINT8 BusId;
+ UINT8 AddressType;
+ UINT64 AddressBase;
+ UINT64 AddressLength;
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING;
+
+typedef enum {
+ EfiLegacyMpTableEntryExtSysAddrSpaceMappingIo = 0,
+ EfiLegacyMpTableEntryExtSysAddrSpaceMappingMemory = 1,
+ EfiLegacyMpTableEntryExtSysAddrSpaceMappingPrefetch = 2,
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING_TYPE;
+
+//
+// Entry Type 129: Bus Hierarchy.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_BUS_HIERARCHY 0x81
+typedef struct {
+ UINT8 EntryType;
+ UINT8 Length;
+ UINT8 BusId;
+ struct {
+ UINT8 SubtractiveDecode : 1;
+ UINT8 Reserved : 7;
+ } BusInfo;
+ UINT8 ParentBus;
+ UINT8 Reserved1;
+ UINT8 Reserved2;
+ UINT8 Reserved3;
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY;
+
+//
+// Entry Type 130: Compatibility Bus Address Space Modifier.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_COMPAT_BUS_ADDR_SPACE_MODIFIER 0x82
+typedef struct {
+ UINT8 EntryType;
+ UINT8 Length;
+ UINT8 BusId;
+ struct {
+ UINT8 RangeMode : 1;
+ UINT8 Reserved : 7;
+ } AddrMode;
+ UINT32 PredefinedRangeList;
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER;
+
+#pragma pack(pop)
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h new file mode 100644 index 0000000000..5bbc05957e --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h @@ -0,0 +1,56 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ MemoryMappedConfigurationSpaceAccessTable.h
+
+Abstract:
+
+ ACPI memory mapped configuration space access table definition, defined at
+ in the PCI Firmware Specification, version 3.0.
+ Specification is available at http://www.pcisig.com.
+
+--*/
+
+#ifndef _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_
+#define _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_
+
+//
+// Include files
+//
+#include "AcpiCommon.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// Memory Mapped Configuration Space Access Table (MCFG)
+// This table is a basic description table header followed by
+// a number of base address allocation structures.
+//
+typedef struct {
+ UINT64 BaseAddress;
+ UINT16 PciSegmentGroupNumber;
+ UINT8 StartBusNumber;
+ UINT8 EndBusNumber;
+ UINT32 Reserved;
+} EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE;
+
+//
+// MCFG Revision (defined in spec)
+//
+#define EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION 0x01
+
+#pragma pack()
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/SdramSpd.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/SdramSpd.h new file mode 100644 index 0000000000..f8ca8485d4 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/SdramSpd.h @@ -0,0 +1,73 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ SdramSpd.h
+
+Abstract:
+
+ This file contains definitions for the SPD fields on an SDRAM.
+
+--*/
+
+#ifndef _SDRAM_SPD_H
+#define _SDRAM_SPD_H
+
+//
+// SDRAM SPD field definitions
+//
+#define SPD_MEMORY_TYPE 2
+#define SPD_SDRAM_ROW_ADDR 3
+#define SPD_SDRAM_COL_ADDR 4
+#define SPD_SDRAM_MODULE_ROWS 5
+#define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6
+#define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7
+#define SPD_SDRAM_ECC_SUPPORT 11
+#define SPD_SDRAM_REFRESH 12
+#define SPD_SDRAM_WIDTH 13
+#define SPD_SDRAM_ERROR_WIDTH 14
+#define SPD_SDRAM_BURST_LENGTH 16
+#define SPD_SDRAM_NO_OF_BANKS 17
+#define SPD_SDRAM_CAS_LATENCY 18
+#define SPD_SDRAM_MODULE_ATTR 21
+
+#define SPD_SDRAM_TCLK1_PULSE 9 // cycle time for highest cas latency
+#define SPD_SDRAM_TAC1_PULSE 10 // access time for highest cas latency
+#define SPD_SDRAM_TCLK2_PULSE 23 // cycle time for 2nd highest cas latency
+#define SPD_SDRAM_TAC2_PULSE 24 // access time for 2nd highest cas latency
+#define SPD_SDRAM_TCLK3_PULSE 25 // cycle time for 3rd highest cas latency
+#define SPD_SDRAM_TAC3_PULSE 26 // access time for 3rd highest cas latency
+#define SPD_SDRAM_MIN_PRECHARGE 27
+#define SPD_SDRAM_ACTIVE_MIN 28
+#define SPD_SDRAM_RAS_CAS 29
+#define SPD_SDRAM_RAS_PULSE 30
+#define SPD_SDRAM_DENSITY 31
+
+//
+// Memory Type Definitions
+//
+#define SPD_VAL_SDR_TYPE 4 // SDR SDRAM memory
+#define SPD_VAL_DDR_TYPE 7 // DDR SDRAM memory
+#define SPD_VAL_DDR2_TYPE 8 // DDR2 SDRAM memory
+//
+// ECC Type Definitions
+//
+#define SPD_ECC_TYPE_NONE 0x00 // No error checking
+#define SPD_ECC_TYPE_PARITY 0x01 // No error checking
+#define SPD_ECC_TYPE_ECC 0x02 // Error checking only
+//
+// Module Attributes (Bit positions)
+//
+#define SPD_BUFFERED 0x01
+#define SPD_REGISTERED 0x02
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/ServerProcessorManagementInterfaceTable.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/ServerProcessorManagementInterfaceTable.h new file mode 100644 index 0000000000..2c2a925e60 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/ServerProcessorManagementInterfaceTable.h @@ -0,0 +1,80 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ ServerProcessorManagementInterfaceTable.h
+
+Abstract:
+
+ ACPI Server Processor Management Interface Table SPMI as described
+ in the IPMI2.0 Specification Revistion 1.5
+
+--*/
+
+#ifndef _SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_H_
+#define _SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_H_
+
+#include "Acpi2_0.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack (1)
+
+//
+// Server Processor Management Interface Table definition.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved_36;
+ UINT8 InterfaceType;
+ UINT16 SpecificationRevision;
+ UINT8 InterruptType;
+ UINT8 GPE;
+ UINT8 Reserved_42;
+ UINT8 PCIDeviceFlag;
+ UINT32 GlobalSystemInterrupt;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;
+ UINT8 PCISegmentGroup_UID1;
+ UINT8 PCIBusNumber_UID2;
+ UINT8 PCIDeviceNumber_UID3;
+ UINT8 PCIFunctionNumber_UID4;
+} EFI_ACPI_SERVER_PROCESSOR_MANAGEMENT_INTERFACE_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+//
+// SPMI Revision
+//
+#define EFI_ACPI_SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_REVISION 0x05
+
+//
+// Interface Type
+//
+#define EFI_ACPI_SPMI_INTERFACE_TYPE_RESERVED 0
+#define EFI_ACPI_SPMI_INTERFACE_TYPE_KCS 1
+#define EFI_ACPI_SPMI_INTERFACE_TYPE_SMIC 2
+#define EFI_ACPI_SPMI_INTERFACE_TYPE_BT 3
+#define EFI_ACPI_SPMI_INTERFACE_TYPE_SSIF 4
+
+//
+// SPMI Specfication Revision
+//
+#define EFI_ACPI_SPMI_SPECIFICATION_REVISION 0x0150
+
+//
+// SPMI Interrupt Type
+//
+#define EFI_ACPI_SPMI_INTERRUPT_TYPE_SCI 0x1
+#define EFI_ACPI_SPMI_INTERRUPT_TYPE_IOAPIC 0x2
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Smbios.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Smbios.h new file mode 100644 index 0000000000..10ef37ddf7 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Smbios.h @@ -0,0 +1,576 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ Smbios.h
+
+Abstract:
+
+--*/
+
+#ifndef _SMBIOS_TABLE_H_
+#define _SMBIOS_TABLE_H_
+
+#include "Tiano.h"
+
+#pragma pack(1)
+
+typedef UINT8 SMBIOS_TABLE_STRING;
+
+typedef struct {
+ UINT8 AnchorString[4];
+ UINT8 EntryPointStructureChecksum;
+ UINT8 EntryPointLength;
+ UINT8 MajorVersion;
+ UINT8 MinorVersion;
+ UINT16 MaxStructureSize;
+ UINT8 EntryPointRevision;
+ UINT8 FormattedArea[5];
+ UINT8 IntermediateAnchorString[5];
+ UINT8 IntermediateChecksum;
+ UINT16 TableLength;
+ UINT32 TableAddress;
+ UINT16 NumberOfSmbiosStructures;
+ UINT8 SmbiosBcdRevision;
+} SMBIOS_TABLE_STRUCTURE;
+
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Handle;
+} SMBIOS_TABLE_HEADER;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING Vendor;
+ SMBIOS_TABLE_STRING BiosVersion;
+ UINT16 BiosSegment;
+ SMBIOS_TABLE_STRING BiosReleaseDate;
+ UINT8 BiosSize;
+ UINT64 BiosCharacteristics;
+ UINT8 BIOSCharacteristicsExtensionBytes[2];
+ UINT8 SystemBiosMajorRelease;
+ UINT8 SystemBiosMinorRelease;
+ UINT8 EmbeddedControllerFirmwareMajorRelease;
+ UINT8 EmbeddedControllerFirmwareMinorRelease;
+} SMBIOS_TABLE_TYPE0;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING ProductName;
+ SMBIOS_TABLE_STRING Version;
+ SMBIOS_TABLE_STRING SerialNumber;
+ EFI_GUID Uuid;
+ UINT8 WakeUpType;
+ SMBIOS_TABLE_STRING SKUNumber;
+ SMBIOS_TABLE_STRING Family;
+} SMBIOS_TABLE_TYPE1;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING ProductName;
+ SMBIOS_TABLE_STRING Version;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING AssetTag;
+ UINT8 FeatureFlag;
+ SMBIOS_TABLE_STRING LocationInChassis;
+ UINT16 ChassisHandle;
+ UINT8 BoardType;
+ UINT8 NumberOfContainedObjectHandles;
+ UINT16 ContainedObjectHandles[1];
+} SMBIOS_TABLE_TYPE2;
+
+typedef struct {
+ UINT8 ContainedElementType;
+ UINT8 ContainedElementMinimum;
+ UINT8 ContainedElementMaximum;
+} CONTAINED_ELEMENT;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING Manufacturer;
+ UINT8 Type;
+ SMBIOS_TABLE_STRING Version;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING AssetTag;
+ UINT8 BootupState;
+ UINT8 PowerSupplyState;
+ UINT8 ThermalState;
+ UINT8 SecurityStatus;
+ UINT8 OemDefined[4];
+ UINT8 Height;
+ UINT8 NumberofPowerCords;
+ UINT8 ContainedElementCount;
+ UINT8 ContainedElementRecordLength;
+ CONTAINED_ELEMENT ContainedElements[1];
+} SMBIOS_TABLE_TYPE3;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 Socket;
+ UINT8 ProcessorType;
+ UINT8 ProcessorFamily;
+ SMBIOS_TABLE_STRING ProcessorManufacture;
+ UINT8 ProcessorId[8];
+ SMBIOS_TABLE_STRING ProcessorVersion;
+ UINT8 Voltage;
+ UINT16 ExternalClock;
+ UINT16 MaxSpeed;
+ UINT16 CurrentSpeed;
+ UINT8 Status;
+ UINT8 ProcessorUpgrade;
+ UINT16 L1CacheHandle;
+ UINT16 L2CacheHandle;
+ UINT16 L3CacheHandle;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING AssetTag;
+ SMBIOS_TABLE_STRING PartNumber;
+} SMBIOS_TABLE_TYPE4;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 ErrDetectMethod;
+ UINT8 ErrCorrectCapability;
+ UINT8 SupportInterleave;
+ UINT8 CurrentInterleave;
+ UINT8 MaxMemoryModuleSize;
+ UINT16 SupportSpeed;
+ UINT16 SupportMemoryType;
+ UINT8 MemoryModuleVoltage;
+ UINT8 AssociatedMemorySlotNum;
+ UINT16 MemoryModuleConfigHandles[1];
+// UINT8 EnableErrCorrectCapabilities;
+} SMBIOS_TABLE_TYPE5;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING SocketDesignation;
+ UINT8 BankConnections;
+ UINT8 CurrentSpeed;
+ UINT16 CurrentMemoryType;
+ UINT8 InstalledSize;
+ UINT8 EnabledSize;
+ UINT8 ErrorStatus;
+} SMBIOS_TABLE_TYPE6;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING SocketDesignation;
+ UINT16 CacheConfiguration;
+ UINT16 MaximumCacheSize;
+ UINT16 InstalledSize;
+ UINT16 SupportedSRAMType;
+ UINT16 CurrentSRAMType;
+ UINT8 CacheSpeed;
+ UINT8 ErrorCorrectionType;
+ UINT8 SystemCacheType;
+ UINT8 Associativity;
+} SMBIOS_TABLE_TYPE7;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING InternalReferenceDesignator;
+ UINT8 InternalConnectorType;
+ SMBIOS_TABLE_STRING ExternalReferenceDesignator;
+ UINT8 ExternalConnectorType;
+ UINT8 PortType;
+} SMBIOS_TABLE_TYPE8;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING SlotDesignation;
+ UINT8 SlotType;
+ UINT8 SlotDataBusWidth;
+ UINT8 CurrentUsage;
+ UINT8 SlotLength;
+ UINT16 SlotID;
+ UINT8 SlotCharacteristics1;
+ UINT8 SlotCharacteristics2;
+} SMBIOS_TABLE_TYPE9;
+
+typedef struct {
+ UINT8 DeviceType;
+ SMBIOS_TABLE_STRING DescriptionString;
+} DEVICE_STRUCT;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ DEVICE_STRUCT Device[1];
+} SMBIOS_TABLE_TYPE10;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 StringCount;
+} SMBIOS_TABLE_TYPE11;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 StringCount;
+} SMBIOS_TABLE_TYPE12;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 InstallableLanguages;
+ UINT8 Flags;
+ UINT8 reserved[15];
+ SMBIOS_TABLE_STRING CurrentLanguages;
+} SMBIOS_TABLE_TYPE13;
+
+typedef struct {
+ UINT8 ItemType;
+ UINT16 ItemHandle;
+} GROUP_STRUCT;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING GroupName;
+ GROUP_STRUCT Group[1];
+} SMBIOS_TABLE_TYPE14;
+
+typedef struct {
+ UINT8 LogType;
+ UINT8 DataFormatType;
+} EVENT_LOG_TYPE;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT16 LogAreaLength;
+ UINT16 LogHeaderStartOffset;
+ UINT16 LogDataStartOffset;
+ UINT8 AccessMethod;
+ UINT8 LogStatus;
+ UINT32 LogChangeToken;
+ UINT32 AccessMethodAddress;
+ UINT8 LogHeaderFormat;
+ UINT8 NumberOfSupportedLogTypeDescriptors;
+ UINT8 LengthOfLogTypeDescriptor;
+ EVENT_LOG_TYPE EventLogTypeDescriptors[1];
+} SMBIOS_TABLE_TYPE15;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 Location;
+ UINT8 Use;
+ UINT8 MemoryErrorCorrection;
+ UINT32 MaximumCapacity;
+ UINT16 MemoryErrorInformationHandle;
+ UINT16 NumberOfMemoryDevices;
+} SMBIOS_TABLE_TYPE16;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT16 MemoryArrayHandle;
+ UINT16 MemoryErrorInformationHandle;
+ UINT16 TotalWidth;
+ UINT16 DataWidth;
+ UINT16 Size;
+ UINT8 FormFactor;
+ UINT8 DeviceSet;
+ SMBIOS_TABLE_STRING DeviceLocator;
+ SMBIOS_TABLE_STRING BankLocator;
+ UINT8 MemoryType;
+ UINT16 TypeDetail;
+ UINT16 Speed;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING AssetTag;
+ SMBIOS_TABLE_STRING PartNumber;
+} SMBIOS_TABLE_TYPE17;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 ErrorType;
+ UINT8 ErrorGranularity;
+ UINT8 ErrorOperation;
+ UINT32 VendorSyndrome;
+ UINT32 MemoryArrayErrorAddress;
+ UINT32 DeviceErrorAddress;
+ UINT32 ErrorResolution;
+} SMBIOS_TABLE_TYPE18;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT32 StartingAddress;
+ UINT32 EndingAddress;
+ UINT16 MemoryArrayHandle;
+ UINT8 PartitionWidth;
+} SMBIOS_TABLE_TYPE19;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT32 StartingAddress;
+ UINT32 EndingAddress;
+ UINT16 MemoryDeviceHandle;
+ UINT16 MemoryArrayMappedAddressHandle;
+ UINT8 PartitionRowPosition;
+ UINT8 InterleavePosition;
+ UINT8 InterleavedDataDepth;
+} SMBIOS_TABLE_TYPE20;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 Type;
+ UINT8 Interface;
+ UINT8 NumberOfButtons;
+} SMBIOS_TABLE_TYPE21;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING Location;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING ManufactureDate;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING DeviceName;
+ UINT8 DeviceChemistry;
+ UINT16 DeviceCapacity;
+ UINT16 DesignVoltage;
+ SMBIOS_TABLE_STRING SBDSVersionNumber;
+ UINT8 MaximumErrorInBatteryData;
+ UINT16 SBDSSerialNumber;
+ UINT16 SBDSManufactureDate;
+ SMBIOS_TABLE_STRING SBDSDeviceChemistry;
+ UINT8 DesignCapacityMultiplier;
+ UINT32 OEMSpecific;
+} SMBIOS_TABLE_TYPE22;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 Capabilities;
+ UINT16 ResetCount;
+ UINT16 ResetLimit;
+ UINT16 TimerInterval;
+ UINT16 Timeout;
+} SMBIOS_TABLE_TYPE23;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 HardwareSecuritySettings;
+} SMBIOS_TABLE_TYPE24;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 NextScheduledPowerOnMonth;
+ UINT8 NextScheduledPowerOnDayOfMonth;
+ UINT8 NextScheduledPowerOnHour;
+ UINT8 NextScheduledPowerOnMinute;
+ UINT8 NextScheduledPowerOnSecond;
+} SMBIOS_TABLE_TYPE25;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING Description;
+ UINT8 LocationAndStatus;
+ UINT16 MaximumValue;
+ UINT16 MinimumValue;
+ UINT16 Resolution;
+ UINT16 Tolerance;
+ UINT16 Accuracy;
+ UINT32 OEMDefined;
+ UINT16 NominalValue;
+} SMBIOS_TABLE_TYPE26;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT16 TemperatureProbeHandle;
+ UINT8 DeviceTypeAndStatus;
+ UINT8 CoolingUnitGroup;
+ UINT32 OEMDefined;
+ UINT16 NominalSpeed;
+} SMBIOS_TABLE_TYPE27;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING Description;
+ UINT8 LocationAndStatus;
+ UINT16 MaximumValue;
+ UINT16 MinimumValue;
+ UINT16 Resolution;
+ UINT16 Tolerance;
+ UINT16 Accuracy;
+ UINT32 OEMDefined;
+ UINT16 NominalValue;
+} SMBIOS_TABLE_TYPE28;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING Description;
+ UINT8 LocationAndStatus;
+ UINT16 MaximumValue;
+ UINT16 MinimumValue;
+ UINT16 Resolution;
+ UINT16 Tolerance;
+ UINT16 Accuracy;
+ UINT32 OEMDefined;
+ UINT16 NominalValue;
+} SMBIOS_TABLE_TYPE29;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING ManufacturerName;
+ UINT8 Connections;
+} SMBIOS_TABLE_TYPE30;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 Checksum;
+ UINT8 Reserved1;
+ UINT16 Reserved2;
+ UINT32 BisEntry16;
+ UINT32 BisEntry32;
+ UINT64 Reserved3;
+ UINT32 Reserved4;
+} SMBIOS_TABLE_TYPE31;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 Reserved[6];
+ UINT8 BootStatus[1];
+} SMBIOS_TABLE_TYPE32;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 ErrorType;
+ UINT8 ErrorGranularity;
+ UINT8 ErrorOperation;
+ UINT32 VendorSyndrome;
+ UINT64 MemoryArrayErrorAddress;
+ UINT64 DeviceErrorAddress;
+ UINT32 ErrorResolution;
+} SMBIOS_TABLE_TYPE33;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING Description;
+ UINT8 Type;
+ UINT32 Address;
+ UINT8 AddressType;
+} SMBIOS_TABLE_TYPE34;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING Description;
+ UINT16 ManagementDeviceHandle;
+ UINT16 ComponentHandle;
+ UINT16 ThresholdHandle;
+} SMBIOS_TABLE_TYPE35;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT16 LowerThresholdNonCritical;
+ UINT16 UpperThresholdNonCritical;
+ UINT16 LowerThresholdCritical;
+ UINT16 UpperThresholdCritical;
+ UINT16 LowerThresholdNonRecoverable;
+ UINT16 UpperThresholdNonRecoverable;
+} SMBIOS_TABLE_TYPE36;
+
+typedef struct {
+ UINT8 DeviceLoad;
+ UINT16 DeviceHandle;
+} MEMORY_DEVICE;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 ChannelType;
+ UINT8 MaximumChannelLoad;
+ UINT8 MemoryDeviceCount;
+ MEMORY_DEVICE MemoryDevice[1];
+} SMBIOS_TABLE_TYPE37;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 InterfaceType;
+ UINT8 IPMISpecificationRevision;
+ UINT8 I2CSlaveAddress;
+ UINT8 NVStorageDeviceAddress;
+ UINT64 BaseAddress;
+ UINT8 BaseAddressModifier_InterruptInfo;
+ UINT8 InterruptNumber;
+} SMBIOS_TABLE_TYPE38;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 PowerUnitGroup;
+ SMBIOS_TABLE_STRING Location;
+ SMBIOS_TABLE_STRING DeviceName;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING AssetTagNumber;
+ SMBIOS_TABLE_STRING ModelPartNumber;
+ SMBIOS_TABLE_STRING RevisionLevel;
+ UINT16 MaxPowerCapacity;
+ UINT16 PowerSupplyCharacteristics;
+ UINT16 InputVoltageProbeHandle;
+ UINT16 CoolingDeviceHandle;
+ UINT16 InputCurrentProbeHandle;
+} SMBIOS_TABLE_TYPE39;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+} SMBIOS_TABLE_TYPE126;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+} SMBIOS_TABLE_TYPE127;
+
+typedef union {
+ SMBIOS_TABLE_HEADER *Hdr;
+ SMBIOS_TABLE_TYPE0 *Type0;
+ SMBIOS_TABLE_TYPE1 *Type1;
+ SMBIOS_TABLE_TYPE2 *Type2;
+ SMBIOS_TABLE_TYPE3 *Type3;
+ SMBIOS_TABLE_TYPE4 *Type4;
+ SMBIOS_TABLE_TYPE5 *Type5;
+ SMBIOS_TABLE_TYPE6 *Type6;
+ SMBIOS_TABLE_TYPE7 *Type7;
+ SMBIOS_TABLE_TYPE8 *Type8;
+ SMBIOS_TABLE_TYPE9 *Type9;
+ SMBIOS_TABLE_TYPE10 *Type10;
+ SMBIOS_TABLE_TYPE11 *Type11;
+ SMBIOS_TABLE_TYPE12 *Type12;
+ SMBIOS_TABLE_TYPE13 *Type13;
+ SMBIOS_TABLE_TYPE14 *Type14;
+ SMBIOS_TABLE_TYPE15 *Type15;
+ SMBIOS_TABLE_TYPE16 *Type16;
+ SMBIOS_TABLE_TYPE17 *Type17;
+ SMBIOS_TABLE_TYPE18 *Type18;
+ SMBIOS_TABLE_TYPE19 *Type19;
+ SMBIOS_TABLE_TYPE20 *Type20;
+ SMBIOS_TABLE_TYPE21 *Type21;
+ SMBIOS_TABLE_TYPE22 *Type22;
+ SMBIOS_TABLE_TYPE23 *Type23;
+ SMBIOS_TABLE_TYPE24 *Type24;
+ SMBIOS_TABLE_TYPE25 *Type25;
+ SMBIOS_TABLE_TYPE26 *Type26;
+ SMBIOS_TABLE_TYPE27 *Type27;
+ SMBIOS_TABLE_TYPE28 *Type28;
+ SMBIOS_TABLE_TYPE29 *Type29;
+ SMBIOS_TABLE_TYPE30 *Type30;
+ SMBIOS_TABLE_TYPE31 *Type31;
+ SMBIOS_TABLE_TYPE32 *Type32;
+ SMBIOS_TABLE_TYPE33 *Type33;
+ SMBIOS_TABLE_TYPE34 *Type34;
+ SMBIOS_TABLE_TYPE35 *Type35;
+ SMBIOS_TABLE_TYPE36 *Type36;
+ SMBIOS_TABLE_TYPE37 *Type37;
+ SMBIOS_TABLE_TYPE38 *Type38;
+ SMBIOS_TABLE_TYPE39 *Type39;
+ SMBIOS_TABLE_TYPE126 *Type126;
+ SMBIOS_TABLE_TYPE127 *Type127;
+ UINT8 *Raw;
+} SMBIOS_STRUCTURE_POINTER;
+
+#pragma pack()
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Tpm12.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Tpm12.h new file mode 100644 index 0000000000..077498a51d --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Tpm12.h @@ -0,0 +1,1847 @@ +/*++
+
+Copyright (c) 2005 - 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ Tpm12.h
+
+Abstract:
+
+ TPM Specification data structures (TCG TPM Specification Version 1.2 Revision 94)
+
+ See http://trustedcomputinggroup.org for latest specification updates
+
+--*/
+
+#ifndef _TPM12_H_
+#define _TPM12_H_
+
+//
+// Structures are all packed on 1-byte alignment
+//
+
+#pragma pack (push)
+#pragma pack (1)
+
+//
+// Part 2, section 2.2: Basic types & Helper redefinitions
+//
+typedef UINT8 TPM_AUTH_DATA_USAGE;
+typedef UINT8 TPM_PAYLOAD_TYPE;
+typedef UINT8 TPM_VERSION_BYTE;
+typedef UINT16 TPM_TAG;
+typedef UINT16 TPM_PROTOCOL_ID;
+typedef UINT16 TPM_STARTUP_TYPE;
+typedef UINT16 TPM_ENC_SCHEME;
+typedef UINT16 TPM_SIG_SCHEME;
+typedef UINT16 TPM_MIGRATE_SCHEME;
+typedef UINT16 TPM_PHYSICAL_PRESENCE;
+typedef UINT16 TPM_ENTITY_TYPE;
+typedef UINT16 TPM_KEY_USAGE;
+typedef UINT16 TPM_EK_TYPE;
+typedef UINT16 TPM_STRUCTURE_TAG;
+typedef UINT16 TPM_PLATFORM_SPECIFIC;
+typedef UINT32 TPM_COMMAND_CODE;
+typedef UINT32 TPM_CAPABILITY_AREA;
+typedef UINT32 TPM_KEY_FLAGS;
+typedef UINT32 TPM_ALGORITHM_ID;
+typedef UINT32 TPM_MODIFIER_INDICATOR;
+typedef UINT32 TPM_ACTUAL_COUNT;
+typedef UINT32 TPM_TRANSPORT_ATTRIBUTES;
+typedef UINT32 TPM_AUTHHANDLE;
+typedef UINT32 TPM_DIRINDEX;
+typedef UINT32 TPM_KEY_HANDLE;
+typedef UINT32 TPM_PCRINDEX;
+typedef UINT32 TPM_RESULT;
+typedef UINT32 TPM_RESOURCE_TYPE;
+typedef UINT32 TPM_KEY_CONTROL;
+typedef UINT32 TPM_NV_INDEX;
+typedef UINT32 TPM_FAMILY_ID;
+typedef UINT32 TPM_FAMILY_VERIFICATION;
+typedef UINT32 TPM_STARTUP_EFFECTS;
+typedef UINT32 TPM_SYM_MODE;
+typedef UINT32 TPM_FAMILY_FLAGS;
+typedef UINT32 TPM_DELEGATE_INDEX;
+typedef UINT32 TPM_CMK_DELEGATE;
+typedef UINT32 TPM_COUNT_ID;
+typedef UINT32 TPM_REDIT_COMMAND;
+typedef UINT32 TPM_TRANSHANDLE;
+typedef UINT32 TPM_HANDLE;
+typedef UINT32 TPM_FAMILY_OPERATION;
+
+//
+// Part 2, section 2.2.4: Vendor specific
+// The following defines allow for the quick specification of a
+// vendor specific item.
+//
+#define TPM_Vendor_Specific32 ((UINT32) 0x00000400)
+#define TPM_Vendor_Specific8 ((UINT8) 0x80)
+
+//
+// Part 2, section 3.1: Structure TAGs
+//
+#define TPM_TAG_CONTEXTBLOB ((TPM_STRUCTURE_TAG) 0x0001)
+#define TPM_TAG_CONTEXT_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0002)
+#define TPM_TAG_CONTEXTPOINTER ((TPM_STRUCTURE_TAG) 0x0003)
+#define TPM_TAG_CONTEXTLIST ((TPM_STRUCTURE_TAG) 0x0004)
+#define TPM_TAG_SIGNINFO ((TPM_STRUCTURE_TAG) 0x0005)
+#define TPM_TAG_PCR_INFO_LONG ((TPM_STRUCTURE_TAG) 0x0006)
+#define TPM_TAG_PERSISTENT_FLAGS ((TPM_STRUCTURE_TAG) 0x0007)
+#define TPM_TAG_VOLATILE_FLAGS ((TPM_STRUCTURE_TAG) 0x0008)
+#define TPM_TAG_PERSISTENT_DATA ((TPM_STRUCTURE_TAG) 0x0009)
+#define TPM_TAG_VOLATILE_DATA ((TPM_STRUCTURE_TAG) 0x000A)
+#define TPM_TAG_SV_DATA ((TPM_STRUCTURE_TAG) 0x000B)
+#define TPM_TAG_EK_BLOB ((TPM_STRUCTURE_TAG) 0x000C)
+#define TPM_TAG_EK_BLOB_AUTH ((TPM_STRUCTURE_TAG) 0x000D)
+#define TPM_TAG_COUNTER_VALUE ((TPM_STRUCTURE_TAG) 0x000E)
+#define TPM_TAG_TRANSPORT_INTERNAL ((TPM_STRUCTURE_TAG) 0x000F)
+#define TPM_TAG_TRANSPORT_LOG_IN ((TPM_STRUCTURE_TAG) 0x0010)
+#define TPM_TAG_TRANSPORT_LOG_OUT ((TPM_STRUCTURE_TAG) 0x0011)
+#define TPM_TAG_AUDIT_EVENT_IN ((TPM_STRUCTURE_TAG) 0x0012)
+#define TPM_TAG_AUDIT_EVENT_OUT ((TPM_STRUCTURE_TAG) 0x0013)
+#define TPM_TAG_CURRENT_TICKS ((TPM_STRUCTURE_TAG) 0x0014)
+#define TPM_TAG_KEY ((TPM_STRUCTURE_TAG) 0x0015)
+#define TPM_TAG_STORED_DATA12 ((TPM_STRUCTURE_TAG) 0x0016)
+#define TPM_TAG_NV_ATTRIBUTES ((TPM_STRUCTURE_TAG) 0x0017)
+#define TPM_TAG_NV_DATA_PUBLIC ((TPM_STRUCTURE_TAG) 0x0018)
+#define TPM_TAG_NV_DATA_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0019)
+#define TPM_TAG_DELEGATIONS ((TPM_STRUCTURE_TAG) 0x001A)
+#define TPM_TAG_DELEGATE_PUBLIC ((TPM_STRUCTURE_TAG) 0x001B)
+#define TPM_TAG_DELEGATE_TABLE_ROW ((TPM_STRUCTURE_TAG) 0x001C)
+#define TPM_TAG_TRANSPORT_AUTH ((TPM_STRUCTURE_TAG) 0x001D)
+#define TPM_TAG_TRANSPORT_PUBLIC ((TPM_STRUCTURE_TAG) 0x001E)
+#define TPM_TAG_PERMANENT_FLAGS ((TPM_STRUCTURE_TAG) 0x001F)
+#define TPM_TAG_STCLEAR_FLAGS ((TPM_STRUCTURE_TAG) 0x0020)
+#define TPM_TAG_STANY_FLAGS ((TPM_STRUCTURE_TAG) 0x0021)
+#define TPM_TAG_PERMANENT_DATA ((TPM_STRUCTURE_TAG) 0x0022)
+#define TPM_TAG_STCLEAR_DATA ((TPM_STRUCTURE_TAG) 0x0023)
+#define TPM_TAG_STANY_DATA ((TPM_STRUCTURE_TAG) 0x0024)
+#define TPM_TAG_FAMILY_TABLE_ENTRY ((TPM_STRUCTURE_TAG) 0x0025)
+#define TPM_TAG_DELEGATE_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0026)
+#define TPM_TAG_DELG_KEY_BLOB ((TPM_STRUCTURE_TAG) 0x0027)
+#define TPM_TAG_KEY12 ((TPM_STRUCTURE_TAG) 0x0028)
+#define TPM_TAG_CERTIFY_INFO2 ((TPM_STRUCTURE_TAG) 0x0029)
+#define TPM_TAG_DELEGATE_OWNER_BLOB ((TPM_STRUCTURE_TAG) 0x002A)
+#define TPM_TAG_EK_BLOB_ACTIVATE ((TPM_STRUCTURE_TAG) 0x002B)
+#define TPM_TAG_DAA_BLOB ((TPM_STRUCTURE_TAG) 0x002C)
+#define TPM_TAG_DAA_CONTEXT ((TPM_STRUCTURE_TAG) 0x002D)
+#define TPM_TAG_DAA_ENFORCE ((TPM_STRUCTURE_TAG) 0x002E)
+#define TPM_TAG_DAA_ISSUER ((TPM_STRUCTURE_TAG) 0x002F)
+#define TPM_TAG_CAP_VERSION_INFO ((TPM_STRUCTURE_TAG) 0x0030)
+#define TPM_TAG_DAA_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0031)
+#define TPM_TAG_DAA_TPM ((TPM_STRUCTURE_TAG) 0x0032)
+#define TPM_TAG_CMK_MIGAUTH ((TPM_STRUCTURE_TAG) 0x0033)
+#define TPM_TAG_CMK_SIGTICKET ((TPM_STRUCTURE_TAG) 0x0034)
+#define TPM_TAG_CMK_MA_APPROVAL ((TPM_STRUCTURE_TAG) 0x0035)
+#define TPM_TAG_QUOTE_INFO2 ((TPM_STRUCTURE_TAG) 0x0036)
+
+//
+// Part 2, section 4: TPM Types
+//
+
+//
+// Part 2, section 4.1: TPM_RESOURCE_TYPE
+//
+#define TPM_RT_KEY ((TPM_RESOURCE_TYPE) 0x00000001) // The handle is a key handle and is the result of a LoadKey type operation
+#define TPM_RT_AUTH ((TPM_RESOURCE_TYPE) 0x00000002) // The handle is an authorization handle. Auth handles come from TPM_OIAP, TPM_OSAP and TPM_DSAP
+#define TPM_RT_HASH ((TPM_RESOURCE_TYPE) 0x00000003) // Reserved for hashes
+#define TPM_RT_TRANS ((TPM_RESOURCE_TYPE) 0x00000004) // The handle is for a transport session. Transport handles come from TPM_EstablishTransport
+#define TPM_RT_CONTEXT ((TPM_RESOURCE_TYPE) 0x00000005) // Resource wrapped and held outside the TPM using the context save/restore commands
+#define TPM_RT_COUNTER ((TPM_RESOURCE_TYPE) 0x00000006) // Reserved for counters
+#define TPM_RT_DELEGATE ((TPM_RESOURCE_TYPE) 0x00000007) // The handle is for a delegate row. These are the internal rows held in NV storage by the TPM
+#define TPM_RT_DAA_TPM ((TPM_RESOURCE_TYPE) 0x00000008) // The value is a DAA TPM specific blob
+#define TPM_RT_DAA_V0 ((TPM_RESOURCE_TYPE) 0x00000009) // The value is a DAA V0 parameter
+#define TPM_RT_DAA_V1 ((TPM_RESOURCE_TYPE) 0x0000000A) // The value is a DAA V1 parameter
+
+//
+// Part 2, section 4.2: TPM_PAYLOAD_TYPE
+//
+#define TPM_PT_ASYM ((TPM_PAYLOAD_TYPE) 0x01) // The entity is an asymmetric key
+#define TPM_PT_BIND ((TPM_PAYLOAD_TYPE) 0x02) // The entity is bound data
+#define TPM_PT_MIGRATE ((TPM_PAYLOAD_TYPE) 0x03) // The entity is a migration blob
+#define TPM_PT_MAINT ((TPM_PAYLOAD_TYPE) 0x04) // The entity is a maintenance blob
+#define TPM_PT_SEAL ((TPM_PAYLOAD_TYPE) 0x05) // The entity is sealed data
+#define TPM_PT_MIGRATE_RESTRICTED ((TPM_PAYLOAD_TYPE) 0x06) // The entity is a restricted-migration asymmetric key
+#define TPM_PT_MIGRATE_EXTERNAL ((TPM_PAYLOAD_TYPE) 0x07) // The entity is a external migratable key
+#define TPM_PT_CMK_MIGRATE ((TPM_PAYLOAD_TYPE) 0x08) // The entity is a CMK migratable blob
+#define TPM_PT_VENDOR_SPECIFIC ((TPM_PAYLOAD_TYPE) 0x80) // 0x80 - 0xFF Vendor specific payloads
+
+//
+// Part 2, section 4.3: TPM_ENTIRY_TYPE
+//
+#define TPM_ET_KEYHANDLE ((UINT16) 0x0001) // The entity is a keyHandle or key
+#define TPM_ET_OWNER ((UINT16) 0x0002) // The entity is the TPM Owner
+#define TPM_ET_DATA ((UINT16) 0x0003) // The entity is some data
+#define TPM_ET_SRK ((UINT16) 0x0004) // The entity is the SRK
+#define TPM_ET_KEY ((UINT16) 0x0005) // The entity is a key or keyHandle
+#define TPM_ET_REVOKE ((UINT16) 0x0006) // The entity is the RevokeTrust value
+#define TPM_ET_DEL_OWNER_BLOB ((UINT16) 0x0007) // The entity is a delegate owner blob
+#define TPM_ET_DEL_ROW ((UINT16) 0x0008) // The entity is a delegate row
+#define TPM_ET_DEL_KEY_BLOB ((UINT16) 0x0009) // The entity is a delegate key blob
+#define TPM_ET_COUNTER ((UINT16) 0x000A) // The entity is a counter
+#define TPM_ET_NV ((UINT16) 0x000B) // The entity is a NV index
+#define TPM_ET_RESERVED_HANDLE ((UINT16) 0x0040) // Reserved. This value avoids collisions with the handle MSB setting.
+//
+// TPM_ENTITY_TYPE MSB Values: The MSB is used to indicate the ADIP encryption sheme when applicable
+//
+#define TPM_ET_XOR ((UINT16) 0x0000) // ADIP encryption scheme: XOR
+#define TPM_ET_AES128 ((UINT16) 0x0006) // ADIP encryption scheme: AES 128 bits
+
+//
+// Part 2, section 4.4.1: Reserved Key Handles
+//
+#define TPM_KH_SRK ((TPM_KEY_HANDLE) 0x40000000) // The handle points to the SRK
+#define TPM_KH_OWNER ((TPM_KEY_HANDLE) 0x40000001) // The handle points to the TPM Owner
+#define TPM_KH_REVOKE ((TPM_KEY_HANDLE) 0x40000002) // The handle points to the RevokeTrust value
+#define TPM_KH_TRANSPORT ((TPM_KEY_HANDLE) 0x40000003) // The handle points to the EstablishTransport static authorization
+#define TPM_KH_OPERATOR ((TPM_KEY_HANDLE) 0x40000004) // The handle points to the Operator auth
+#define TPM_KH_ADMIN ((TPM_KEY_HANDLE) 0x40000005) // The handle points to the delegation administration auth
+#define TPM_KH_EK ((TPM_KEY_HANDLE) 0x40000006) // The handle points to the PUBEK, only usable with TPM_OwnerReadInternalPub
+
+//
+// Part 2, section 4.5: TPM_STARTUP_TYPE
+//
+#define TPM_ST_CLEAR ((TPM_STARTUP_TYPE) 0x0001) // The TPM is starting up from a clean state
+#define TPM_ST_STATE ((TPM_STARTUP_TYPE) 0x0002) // The TPM is starting up from a saved state
+#define TPM_ST_DEACTIVATED ((TPM_STARTUP_TYPE) 0x0003) // The TPM is to startup and set the deactivated flag to TRUE
+
+//
+// Part 2, section 4.6: TPM_STATUP_EFFECTS
+// The table makeup is still an open issue.
+//
+
+//
+// Part 2, section 4.7: TPM_PROTOCOL_ID
+//
+#define TPM_PID_OIAP ((TPM_PROTOCOL_ID) 0x0001) // The OIAP protocol.
+#define TPM_PID_OSAP ((TPM_PROTOCOL_ID) 0x0002) // The OSAP protocol.
+#define TPM_PID_ADIP ((TPM_PROTOCOL_ID) 0x0003) // The ADIP protocol.
+#define TPM_PID_ADCP ((TPM_PROTOCOL_ID) 0x0004) // The ADCP protocol.
+#define TPM_PID_OWNER ((TPM_PROTOCOL_ID) 0x0005) // The protocol for taking ownership of a TPM.
+#define TPM_PID_DSAP ((TPM_PROTOCOL_ID) 0x0006) // The DSAP protocol
+#define TPM_PID_TRANSPORT ((TPM_PROTOCOL_ID) 0x0007) // The transport protocol
+
+//
+// Part 2, section 4.8: TPM_ALGORITHM_ID
+// The TPM MUST support the algorithms TPM_ALG_RSA, TPM_ALG_SHA, TPM_ALG_HMAC,
+// TPM_ALG_MGF1
+//
+#define TPM_ALG_RSA ((TPM_ALGORITHM_ID) 0x00000001) // The RSA algorithm.
+#define TPM_ALG_DES ((TPM_ALGORITHM_ID) 0x00000002) // The DES algorithm
+#define TPM_ALG_3DES ((TPM_ALGORITHM_ID) 0x00000003) // The 3DES algorithm in EDE mode
+#define TPM_ALG_SHA ((TPM_ALGORITHM_ID) 0x00000004) // The SHA1 algorithm
+#define TPM_ALG_HMAC ((TPM_ALGORITHM_ID) 0x00000005) // The RFC 2104 HMAC algorithm
+#define TPM_ALG_AES128 ((TPM_ALGORITHM_ID) 0x00000006) // The AES algorithm, key size 128
+#define TPM_ALG_MGF1 ((TPM_ALGORITHM_ID) 0x00000007) // The XOR algorithm using MGF1 to create a string the size of the encrypted block
+#define TPM_ALG_AES192 ((TPM_ALGORITHM_ID) 0x00000008) // AES, key size 192
+#define TPM_ALG_AES256 ((TPM_ALGORITHM_ID) 0x00000009) // AES, key size 256
+#define TPM_ALG_XOR ((TPM_ALGORITHM_ID) 0x0000000A) // XOR using the rolling nonces
+
+//
+// Part 2, section 4.9: TPM_PHYSICAL_PRESENCE
+//
+#define TPM_PHYSICAL_PRESENCE_HW_DISABLE ((TPM_PHYSICAL_PRESENCE) 0x0200) // Sets the physicalPresenceHWEnable to FALSE
+#define TPM_PHYSICAL_PRESENCE_CMD_DISABLE ((TPM_PHYSICAL_PRESENCE) 0x0100) // Sets the physicalPresenceCMDEnable to FALSE
+#define TPM_PHYSICAL_PRESENCE_LIFETIME_LOCK ((TPM_PHYSICAL_PRESENCE) 0x0080) // Sets the physicalPresenceLifetimeLock to TRUE
+#define TPM_PHYSICAL_PRESENCE_HW_ENABLE ((TPM_PHYSICAL_PRESENCE) 0x0040) // Sets the physicalPresenceHWEnable to TRUE
+#define TPM_PHYSICAL_PRESENCE_CMD_ENABLE ((TPM_PHYSICAL_PRESENCE) 0x0020) // Sets the physicalPresenceCMDEnable to TRUE
+#define TPM_PHYSICAL_PRESENCE_NOTPRESENT ((TPM_PHYSICAL_PRESENCE) 0x0010) // Sets PhysicalPresence = FALSE
+#define TPM_PHYSICAL_PRESENCE_PRESENT ((TPM_PHYSICAL_PRESENCE) 0x0008) // Sets PhysicalPresence = TRUE
+#define TPM_PHYSICAL_PRESENCE_LOCK ((TPM_PHYSICAL_PRESENCE) 0x0004) // Sets PhysicalPresenceLock = TRUE
+
+//
+// Part 2, section 4.10: TPM_MIGRATE_SCHEME
+//
+#define TPM_MS_MIGRATE ((TPM_MIGRATE_SCHEME) 0x0001) // A public key that can be used with all TPM migration commands other than 'ReWrap' mode.
+#define TPM_MS_REWRAP ((TPM_MIGRATE_SCHEME) 0x0002) // A public key that can be used for the ReWrap mode of TPM_CreateMigrationBlob.
+#define TPM_MS_MAINT ((TPM_MIGRATE_SCHEME) 0x0003) // A public key that can be used for the Maintenance commands
+#define TPM_MS_RESTRICT_MIGRATE ((TPM_MIGRATE_SCHEME) 0x0004) // The key is to be migrated to a Migration Authority.
+#define TPM_MS_RESTRICT_APPROVE_DOUBLE ((TPM_MIGRATE_SCHEME) 0x0005) // The key is to be migrated to an entity approved by a Migration Authority using double wrapping
+
+//
+// Part 2, section 4.11: TPM_EK_TYPE
+//
+#define TPM_EK_TYPE_ACTIVATE ((TPM_EK_TYPE) 0x0001) // The blob MUST be TPM_EK_BLOB_ACTIVATE
+#define TPM_EK_TYPE_AUTH ((TPM_EK_TYPE) 0x0002) // The blob MUST be TPM_EK_BLOB_AUTH
+
+//
+// Part 2, section 4.12: TPM_PLATFORM_SPECIFIC
+//
+#define TPM_PS_PC_11 ((TPM_PLATFORM_SPECIFIC) 0x0001) // PC Specific version 1.1
+#define TPM_PS_PC_12 ((TPM_PLATFORM_SPECIFIC) 0x0002) // PC Specific version 1.2
+#define TPM_PS_PDA_12 ((TPM_PLATFORM_SPECIFIC) 0x0003) // PDA Specific version 1.2
+#define TPM_PS_Server_12 ((TPM_PLATFORM_SPECIFIC) 0x0004) // Server Specific version 1.2
+#define TPM_PS_Mobile_12 ((TPM_PLATFORM_SPECIFIC) 0x0005) // Mobil Specific version 1.2
+
+//
+// Part 2, section 5: Basic Structures
+//
+
+//
+// Part 2, section 5.1: TPM_STRUCT_VER
+//
+typedef struct tdTPM_STRUCT_VER {
+ UINT8 major;
+ UINT8 minor;
+ UINT8 revMajor;
+ UINT8 revMinor;
+} TPM_STRUCT_VER;
+
+//
+// Part 2, section 5.3: TPM_VERSION
+//
+typedef struct tdTPM_VERSION {
+ TPM_VERSION_BYTE major;
+ TPM_VERSION_BYTE minor;
+ UINT8 revMajor;
+ UINT8 revMinor;
+} TPM_VERSION;
+
+//
+// Part 2, section 5.4: TPM_DIGEST
+//
+#define TPM_SHA1_160_HASH_LEN 0x14
+#define TPM_SHA1BASED_NONCE_LEN TPM_SHA1_160_HASH_LEN
+
+typedef struct tdTPM_DIGEST{
+ UINT8 digest[TPM_SHA1_160_HASH_LEN];
+} TPM_DIGEST;
+
+typedef TPM_DIGEST TPM_CHOSENID_HASH; // This SHALL be the digest of the chosen identityLabel and privacyCA for a new TPM identity.
+typedef TPM_DIGEST TPM_COMPOSITE_HASH; // This SHALL be the hash of a list of PCR indexes and PCR values that a key or data is bound to.
+typedef TPM_DIGEST TPM_DIRVALUE; // This SHALL be the value of a DIR register
+typedef TPM_DIGEST TPM_HMAC;
+typedef TPM_DIGEST TPM_PCRVALUE; // The value inside of the PCR
+typedef TPM_DIGEST TPM_AUDITDIGEST; // This SHALL be the value of the current internal audit state
+typedef TPM_DIGEST TPM_DAA_TPM_SEED; // This SHALL be a random value generated by a TPM immediately after the EK is installed in that TPM, whenever an EK is installed in that TPM
+typedef TPM_DIGEST TPM_DAA_CONTEXT_SEED; // This SHALL be a random value
+
+//
+// Part 2, section 5.5: TPM_NONCE
+//
+typedef struct tdTPM_NONCE{
+ UINT8 nonce[20];
+} TPM_NONCE;
+
+//
+// Part 2, section 5.6: TPM_AUTHDATA
+//
+typedef UINT8 tdTPM_AUTHDATA[20];
+typedef tdTPM_AUTHDATA TPM_AUTHDATA;
+typedef TPM_AUTHDATA TPM_SECRET;
+typedef TPM_AUTHDATA TPM_ENCAUTH;
+
+//
+// Part 2, section 5.7: TPM_KEY_HANDLE_LIST
+// Size of handle is loaded * sizeof(TPM_KEY_HANDLE)
+//
+typedef struct tdTPM_KEY_HANDLE_LIST {
+ UINT16 loaded;
+ TPM_KEY_HANDLE handle[1];
+} TPM_KEY_HANDLE_LIST;
+
+//
+// Part 2, section 5.8: TPM_KEY_USAGE values
+//
+
+#define TPM_KEY_SIGNING ((UINT16) 0x0010)
+// TPM_KEY_SIGNING SHALL indicate a signing key. The [private] key SHALL be
+// used for signing operations, only. This means that it MUST be a leaf of the
+// Protected Storage key hierarchy.
+
+#define TPM_KEY_STORAGE ((UINT16) 0x0011)
+// TPM_KEY_STORAGE SHALL indicate a storage key. The key SHALL be used to wrap
+// and unwrap other keys in the Protected Storage hierarchy
+
+#define TPM_KEY_IDENTITY ((UINT16) 0x0012)
+// TPM_KEY_IDENTITY SHALL indicate an identity key. The key SHALL be used for
+// operations that require a TPM identity, only.
+
+#define TPM_KEY_AUTHCHANGE ((UINT16) 0x0013)
+// TPM_KEY_AUTHCHANGE SHALL indicate an ephemeral key that is in use during
+// the ChangeAuthAsym process, only.
+
+#define TPM_KEY_BIND ((UINT16) 0x0014)
+// TPM_KEY_BIND SHALL indicate a key that can be used for TPM_Bind and
+// TPM_Unbind operations only.
+
+#define TPM_KEY_LEGACY ((UINT16) 0x0015)
+// TPM_KEY_LEGACY SHALL indicate a key that can perform signing and binding
+// operations. The key MAY be used for both signing and binding operations.
+// The TPM_KEY_LEGACY key type is to allow for use by applications where both
+// signing and encryption operations occur with the same key. The use of this
+// key type is not recommended TPM_KEY_MIGRATE 0x0016 This SHALL indicate a
+// key in use for TPM_MigrateKey
+
+#define TPM_KEY_MIGRATE ((UINT16) 0x0016)
+// TPM_KEY_MIGRAGE SHALL indicate a key in use for TPM_MigrateKey
+
+//
+// Part 2, section 5.8.1: Encryption/Signature schemes
+//
+
+#define TPM_ES_NONE ((TPM_ENC_SCHEME) 0x0001)
+#define TPM_ES_RSAESPKCSv15 ((TPM_ENC_SCHEME) 0x0002)
+#define TPM_ES_RSAESOAEP_SHA1_MGF1 ((TPM_ENC_SCHEME) 0x0003)
+#define TPM_ES_SYM_CNT ((TPM_ENC_SCHEME) 0x0004)
+#define TPM_ES_SYM_OFB ((TPM_ENC_SCHEME) 0x0005)
+
+#define TPM_SS_NONE ((TPM_SIG_SCHEME) 0x0001)
+#define TPM_SS_RSASSAPKCS1v15_SHA1 ((TPM_SIG_SCHEME) 0x0002)
+#define TPM_SS_RSASSAPKCS1v15_DER ((TPM_SIG_SCHEME) 0x0003)
+#define TPM_SS_RSASSAPKCS1v15_INFO ((TPM_SIG_SCHEME) 0x0004)
+
+//
+// Part 2, section 5.9: TPM_AUTH_DATA_USAGE values
+//
+#define TPM_AUTH_NEVER ((TPM_AUTH_DATA_USAGE) 0x00)
+#define TPM_AUTH_ALWAYS ((TPM_AUTH_DATA_USAGE) 0x01)
+#define TPM_AUTH_PRIV_USE_ONLY ((TPM_AUTH_DATA_USAGE) 0x03)
+
+//
+// Part 2, section 5.10: TPM_KEY_FLAGS
+//
+enum tdTPM_KEY_FLAGS {
+ redirection = 0x00000001,
+ migratable = 0x00000002,
+ isVolatile = 0x00000004,
+ pcrIgnoredOnRead = 0x00000008,
+ migrateAuthority = 0x00000010
+};
+
+//
+// Part 2, section 5.11: TPM_CHANGEAUTH_VALIDATE
+//
+typedef struct tdTPM_CHANGEAUTH_VALIDATE {
+ TPM_SECRET newAuthSecret;
+ TPM_NONCE n1;
+} TPM_CHANGEAUTH_VALIDATE;
+
+//
+// Part 2, section 5.12: TPM_MIGRATIONKEYAUTH
+// decalared after section 10 to catch declaration of TPM_PUBKEY
+//
+// Part 2 section 10.1: TPM_KEY_PARMS
+// [size_is(parmSize)] BYTE* parms;
+//
+typedef struct tdTPM_KEY_PARMS {
+ TPM_ALGORITHM_ID algorithmID;
+ TPM_ENC_SCHEME encScheme;
+ TPM_SIG_SCHEME sigScheme;
+ UINT32 parmSize;
+ UINT8 *parms;
+} TPM_KEY_PARMS;
+
+//
+// Part 2, section 10.4: TPM_STORE_PUBKEY
+//
+typedef struct tdTPM_STORE_PUBKEY {
+ UINT32 keyLength;
+ UINT8 key[1];
+} TPM_STORE_PUBKEY;
+
+//
+// Part 2, section 10.5: TPM_PUBKEY
+//
+typedef struct tdTPM_PUBKEY{
+ TPM_KEY_PARMS algorithmParms;
+ TPM_STORE_PUBKEY pubKey;
+} TPM_PUBKEY;
+
+//
+// Part 2, section 5.12: TPM_MIGRATIONKEYAUTH
+//
+typedef struct tdTPM_MIGRATIONKEYAUTH{
+ TPM_PUBKEY migrationKey;
+ TPM_MIGRATE_SCHEME migrationScheme;
+ TPM_DIGEST digest;
+} TPM_MIGRATIONKEYAUTH;
+
+//
+// Part 2, section 5.13: TPM_COUNTER_VALUE
+//
+typedef struct tdTPM_COUNTER_VALUE{
+ TPM_STRUCTURE_TAG tag;
+ UINT8 label[4];
+ TPM_ACTUAL_COUNT counter;
+} TPM_COUNTER_VALUE;
+
+//
+// Part 2, section 5.14: TPM_SIGN_INFO
+// Size of data indicated by dataLen
+//
+typedef struct tdTPM_SIGN_INFO {
+ TPM_STRUCTURE_TAG tag;
+ UINT8 fixed[4];
+ TPM_NONCE replay;
+ UINT32 dataLen;
+ UINT8 *data;
+} TPM_SIGN_INFO;
+
+//
+// Part 2, section 5.15: TPM_MSA_COMPOSITE
+// Number of migAuthDigest indicated by MSAlist
+//
+typedef struct tdTPM_MSA_COMPOSITE {
+ UINT32 MSAlist;
+ TPM_DIGEST migAuthDigest[1];
+} TPM_MSA_COMPOSITE;
+
+//
+// Part 2, section 5.16: TPM_CMK_AUTH
+//
+typedef struct tdTPM_CMK_AUTH{
+ TPM_DIGEST migrationAuthorityDigest;
+ TPM_DIGEST destinationKeyDigest;
+ TPM_DIGEST sourceKeyDigest;
+} TPM_CMK_AUTH;
+
+//
+// Part 2, section 5.17: TPM_CMK_DELEGATE
+//
+#define TPM_CMK_DELEGATE_SIGNING (((TPM_CMK_DELEGATE)1) << 31)
+#define TPM_CMK_DELEGATE_STORAGE (((TPM_CMK_DELEGATE)1) << 30)
+#define TPM_CMK_DELEGATE_BIND (((TPM_CMK_DELEGATE)1) << 29)
+#define TPM_CMK_DELEGATE_LEGACY (((TPM_CMK_DELEGATE)1) << 28)
+#define TPM_CMK_DELEGATE_MIGRATE (((TPM_CMK_DELEGATE)1) << 27)
+
+//
+// Part 2, section 5.18: TPM_SELECT_SIZE
+//
+typedef struct tdTPM_SELECT_SIZE {
+ UINT8 major;
+ UINT8 minor;
+ UINT16 reqSize;
+} TPM_SELECT_SIZE;
+
+//
+// Part 2, section 5,19: TPM_CMK_MIGAUTH
+//
+typedef struct tdTPM_CMK_MIGAUTH{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST msaDigest;
+ TPM_DIGEST pubKeyDigest;
+} TPM_CMK_MIGAUTH;
+
+//
+// Part 2, section 5.20: TPM_CMK_SIGTICKET
+//
+typedef struct tdTPM_CMK_SIGTICKET{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST verKeyDigest;
+ TPM_DIGEST signedData;
+} TPM_CMK_SIGTICKET;
+
+//
+// Part 2, section 5.21: TPM_CMK_MA_APPROVAL
+//
+typedef struct tdTPM_CMK_MA_APPROVAL{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST migrationAuthorityDigest;
+} TPM_CMK_MA_APPROVAL;
+
+//
+// Part 2, section 6: Command Tags
+//
+#define TPM_TAG_RQU_COMMAND ((TPM_STRUCTURE_TAG) 0x00C1)
+#define TPM_TAG_RQU_AUTH1_COMMAND ((TPM_STRUCTURE_TAG) 0x00C2)
+#define TPM_TAG_RQU_AUTH2_COMMAND ((TPM_STRUCTURE_TAG) 0x00C3)
+#define TPM_TAG_RSP_COMMAND ((TPM_STRUCTURE_TAG) 0x00C4)
+#define TPM_TAG_RSP_AUTH1_COMMAND ((TPM_STRUCTURE_TAG) 0x00C5)
+#define TPM_TAG_RSP_AUTH2_COMMAND ((TPM_STRUCTURE_TAG) 0x00C6)
+
+//
+// Part 2, section 7.1: TPM_PERMANENT_FLAGS
+//
+typedef struct tdTPM_PERMANENT_FLAGS{
+ TPM_STRUCTURE_TAG tag;
+ BOOLEAN disable;
+ BOOLEAN ownership;
+ BOOLEAN deactivated;
+ BOOLEAN readPubek;
+ BOOLEAN disableOwnerClear;
+ BOOLEAN allowMaintenance;
+ BOOLEAN physicalPresenceLifetimeLock;
+ BOOLEAN physicalPresenceHWEnable;
+ BOOLEAN physicalPresenceCMDEnable;
+ BOOLEAN CEKPUsed;
+ BOOLEAN TPMpost;
+ BOOLEAN TPMpostLock;
+ BOOLEAN FIPS;
+ BOOLEAN operator;
+ BOOLEAN enableRevokeEK;
+ BOOLEAN nvLocked;
+ BOOLEAN readSRKPub;
+ BOOLEAN tpmEstablished;
+ BOOLEAN maintenanceDone;
+} TPM_PERMANENT_FLAGS;
+
+//
+// Part 2, section 7.1.1: PERMANENT_FLAGS Subcap for SetCapability
+//
+#define TPM_PF_DISABLE ((TPM_CAPABILITY_AREA) 1)
+#define TPM_PF_OWNERSHIP ((TPM_CAPABILITY_AREA) 2)
+#define TPM_PF_DEACTIVATED ((TPM_CAPABILITY_AREA) 3)
+#define TPM_PF_READPUBEK ((TPM_CAPABILITY_AREA) 4)
+#define TPM_PF_DISABLEOWNERCLEAR ((TPM_CAPABILITY_AREA) 5)
+#define TPM_PF_ALLOWMAINTENANCE ((TPM_CAPABILITY_AREA) 6)
+#define TPM_PF_PHYSICALPRESENCELIFETIMELOCK ((TPM_CAPABILITY_AREA) 7)
+#define TPM_PF_PHYSICALPRESENCEHWENABLE ((TPM_CAPABILITY_AREA) 8)
+#define TPM_PF_PHYSICALPRESENCECMDENABLE ((TPM_CAPABILITY_AREA) 9)
+#define TPM_PF_CEKPUSED ((TPM_CAPABILITY_AREA) 10)
+#define TPM_PF_TPMPOST ((TPM_CAPABILITY_AREA) 11)
+#define TPM_PF_TPMPOSTLOCK ((TPM_CAPABILITY_AREA) 12)
+#define TPM_PF_FIPS ((TPM_CAPABILITY_AREA) 13)
+#define TPM_PF_OPERATOR ((TPM_CAPABILITY_AREA) 14)
+#define TPM_PF_ENABLEREVOKEEK ((TPM_CAPABILITY_AREA) 15)
+#define TPM_PF_NV_LOCKED ((TPM_CAPABILITY_AREA) 16)
+#define TPM_PF_READSRKPUB ((TPM_CAPABILITY_AREA) 17)
+#define TPM_PF_TPMESTABLISHED ((TPM_CAPABILITY_AREA) 18)
+#define TPM_PF_MAINTENANCEDONE ((TPM_CAPABILITY_AREA) 19)
+
+//
+// Part 2, section 7.2: TPM_STCLEAR_FLAGS
+//
+typedef struct tdTPM_STCLEAR_FLAGS{
+ TPM_STRUCTURE_TAG tag;
+ BOOLEAN deactivated;
+ BOOLEAN disableForceClear;
+ BOOLEAN physicalPresence;
+ BOOLEAN physicalPresenceLock;
+ BOOLEAN bGlobalLock;
+} TPM_STCLEAR_FLAGS;
+
+//
+// Part 2, section 7.2.1: STCLEAR_FLAGS Subcap for SetCapability
+//
+#define TPM_SF_DEACTIVATED ((TPM_CAPABILITY_AREA) 1)
+#define TPM_SF_DISABLEFORCECLEAR ((TPM_CAPABILITY_AREA) 2)
+#define TPM_SF_PHYSICALPRESENCE ((TPM_CAPABILITY_AREA) 3)
+#define TPM_SF_PHYSICALPRESENCELOCK ((TPM_CAPABILITY_AREA) 4)
+#define TPM_SF_BGLOBALLOCK ((TPM_CAPABILITY_AREA) 5)
+
+//
+// Part 2, section 7.3: TPM_STANY_FLAGS
+//
+typedef struct tdTPM_STANY_FLAGS{
+ TPM_STRUCTURE_TAG tag;
+ BOOLEAN postInitialise;
+ TPM_MODIFIER_INDICATOR localityModifier;
+ BOOLEAN transportExclusive;
+ BOOLEAN TOSPresent;
+} TPM_STANY_FLAGS;
+
+//
+// Part 2, section 7.3.1: STANY_FLAGS Subcap for SetCapability
+//
+#define TPM_AF_POSTINITIALISE ((TPM_CAPABILITY_AREA) 1)
+#define TPM_AF_LOCALITYMODIFIER ((TPM_CAPABILITY_AREA) 2)
+#define TPM_AF_TRANSPORTEXCLUSIVE ((TPM_CAPABILITY_AREA) 3)
+#define TPM_AF_TOSPRESENT ((TPM_CAPABILITY_AREA) 4)
+
+//
+// All those structures (section 7.4, 7.5, 7.6) are not normative and
+// thus no definitions here
+//
+// Part 2, section 7.4: TPM_PERMANENT_DATA
+//
+//#define TPM_MIN_COUNTERS 4 // the minimum number of counters is 4
+//#define TPM_DELEGATE_KEY TPM_KEY
+//#define TPM_NUM_PCR 16
+//#define TPM_MAX_NV_WRITE_NOOWNER 64
+//typedef struct tdTPM_PERMANENT_DATA
+//{
+// TPM_STRUCTURE_TAG tag;
+// UINT8 revMajor;
+// UINT8 revMinor;
+// TPM_NONCE tpmProof;
+// TPM_NONCE ekReset;
+// TPM_SECRET ownerAuth;
+// TPM_SECRET operatorAuth;
+// TPM_DIRVALUE authDIR[1];
+// TPM_PUBKEY manuMaintPub;
+// TPM_KEY endorsementKey;
+// TPM_KEY srk;
+// TPM_KEY contextKey;
+// TPM_KEY delegateKey;
+// TPM_COUNTER_VALUE auditMonotonicCounter;
+// TPM_COUNTER_VALUE monitonicCounter[TPM_MIN_COUNTERS];
+// TPM_PCR_ATTRIBUTES pcrAttrib[TPM_NUM_PCR];
+// UINT8 ordinalAuditStatus[];
+// UINT8 *rngState;
+// TPM_FAMILY_TABLE familyTable;
+// TPM_DELEGATE_TABLE delegateTable;
+// UINT32 maxNVBufSize;
+// UINT32 lastFamilyID;
+// UINT32 noOwnerNVWrite;
+// TPM_CMK_DELEGATE restrictDelegate;
+// TPM_DAA_TPM_SEED tpmDAASeed;
+//} TPM_PERMANENT_DATA;
+
+//
+// Part 2, section 7.5: TPM_STCLEAR_DATA
+// available inside TPM only
+//
+//typedef struct tdTPM_STCLEAR_DATA
+//{
+// TPM_STRUCTURE_TAG tag;
+// TPM_NONCE contextNonceKey;
+// TPM_COUNT_ID countID;
+// UINT32 ownerReference;
+// BOOLEAN disableResetLock;
+//} TPM_STCLEAR_DATA;
+
+//
+// Part 2, section 7.6: TPM_STANY_DATA
+// available inside TPM only
+//
+//typedef struct tdTPM_STANY_DATA
+//{
+// TPM_STRUCTURE_TAG tag;
+// TPM_NONCE contextNonceSession;
+// TPM_DIGEST auditDigest;
+// TPM_CURRENT_TICKS currentTicks;
+// UINT32 contextCount;
+// UINT32 contextList[TPM_MIN_SESSION_LIST];
+// TPM_SESSION_DATA sessions[TPM_MIN_SESSIONS];
+//} TPM_STANY_DATA;
+
+//
+// Part 2, section 8: PCR Structures
+//
+
+//
+// Part 2, section 8.1: TPM_PCR_SELECTION
+// Size of pcrSelect[] indicated by sizeOfSelect
+//
+typedef struct tdTPM_PCR_SELECTION {
+ UINT16 sizeOfSelect;
+ UINT8 pcrSelect[1];
+} TPM_PCR_SELECTION;
+
+//
+// Part 2, section 8.2: TPM_PCR_COMPOSITE
+// Size of pcrValue[] indicated by valueSize
+//
+typedef struct tdTPM_PCR_COMPOSITE {
+ TPM_PCR_SELECTION select;
+ UINT32 valueSize;
+ TPM_PCRVALUE pcrValue[1];
+} TPM_PCR_COMPOSITE;
+
+//
+// Part 2, section 8.3: TPM_PCR_INFO
+//
+typedef struct tdTPM_PCR_INFO {
+ TPM_PCR_SELECTION pcrSelection;
+ TPM_COMPOSITE_HASH digestAtRelease;
+ TPM_COMPOSITE_HASH digestAtCreation;
+} TPM_PCR_INFO;
+
+//
+// Part 2, section 8.6: TPM_LOCALITY_SELECTION
+//
+typedef UINT8 TPM_LOCALITY_SELECTION;
+
+#define TPM_LOC_FOUR ((UINT8) 0x10)
+#define TPM_LOC_THREE ((UINT8) 0x08)
+#define TPM_LOC_TWO ((UINT8) 0x04)
+#define TPM_LOC_ONE ((UINT8) 0x02)
+#define TPM_LOC_ZERO ((UINT8) 0x01)
+
+//
+// Part 2, section 8.4: TPM_PCR_INFO_LONG
+//
+typedef struct tdTPM_PCR_INFO_LONG {
+ TPM_STRUCTURE_TAG tag;
+ TPM_LOCALITY_SELECTION localityAtCreation;
+ TPM_LOCALITY_SELECTION localityAtRelease;
+ TPM_PCR_SELECTION creationPCRSelection;
+ TPM_PCR_SELECTION releasePCRSelection;
+ TPM_COMPOSITE_HASH digestAtCreation;
+ TPM_COMPOSITE_HASH digestAtRelease;
+} TPM_PCR_INFO_LONG;
+
+//
+// Part 2, section 8.5: TPM_PCR_INFO_SHORT
+//
+typedef struct tdTPM_PCR_INFO_SHORT{
+ TPM_PCR_SELECTION pcrSelection;
+ TPM_LOCALITY_SELECTION localityAtRelease;
+ TPM_COMPOSITE_HASH digestAtRelease;
+} TPM_PCR_INFO_SHORT;
+
+//
+// Part 2, section 8.8: TPM_PCR_ATTRIBUTES
+//
+typedef struct tdTPM_PCR_ATTRIBUTES{
+ BOOLEAN pcrReset;
+ TPM_LOCALITY_SELECTION pcrExtendLocal;
+ TPM_LOCALITY_SELECTION pcrResetLocal;
+} TPM_PCR_ATTRIBUTES;
+
+//
+// Part 2, section 9: Storage Structures
+//
+
+//
+// Part 2, section 9.1: TPM_STORED_DATA
+// [size_is(sealInfoSize)] BYTE* sealInfo;
+// [size_is(encDataSize)] BYTE* encData;
+//
+typedef struct tdTPM_STORED_DATA {
+ TPM_STRUCT_VER ver;
+ UINT32 sealInfoSize;
+ UINT8 *sealInfo;
+ UINT32 encDataSize;
+ UINT8 *encData;
+} TPM_STORED_DATA;
+
+//
+// Part 2, section 9.2: TPM_STORED_DATA12
+// [size_is(sealInfoSize)] BYTE* sealInfo;
+// [size_is(encDataSize)] BYTE* encData;
+//
+typedef struct tdTPM_STORED_DATA12 {
+ TPM_STRUCTURE_TAG tag;
+ TPM_ENTITY_TYPE et;
+ UINT32 sealInfoSize;
+ UINT8 *sealInfo;
+ UINT32 encDataSize;
+ UINT8 *encData;
+} TPM_STORED_DATA12;
+
+//
+// Part 2, section 9.3: TPM_SEALED_DATA
+// [size_is(dataSize)] BYTE* data;
+//
+typedef struct tdTPM_SEALED_DATA {
+ TPM_PAYLOAD_TYPE payload;
+ TPM_SECRET authData;
+ TPM_NONCE tpmProof;
+ TPM_DIGEST storedDigest;
+ UINT32 dataSize;
+ UINT8 *data;
+} TPM_SEALED_DATA;
+
+//
+// Part 2, section 9.4: TPM_SYMMETRIC_KEY
+// [size_is(size)] BYTE* data;
+//
+typedef struct tdTPM_SYMMETRIC_KEY {
+ TPM_ALGORITHM_ID algId;
+ TPM_ENC_SCHEME encScheme;
+ UINT16 dataSize;
+ UINT8 *data;
+} TPM_SYMMETRIC_KEY;
+
+//
+// Part 2, section 9.5: TPM_BOUND_DATA
+//
+typedef struct tdTPM_BOUND_DATA {
+ TPM_STRUCT_VER ver;
+ TPM_PAYLOAD_TYPE payload;
+ UINT8 payloadData[1];
+} TPM_BOUND_DATA;
+
+//
+// Part 2 section 10: TPM_KEY complex
+//
+
+//
+// Part 2, section 10.2: TPM_KEY
+// [size_is(encDataSize)] BYTE* encData;
+//
+typedef struct tdTPM_KEY{
+ TPM_STRUCT_VER ver;
+ TPM_KEY_USAGE keyUsage;
+ TPM_KEY_FLAGS keyFlags;
+ TPM_AUTH_DATA_USAGE authDataUsage;
+ TPM_KEY_PARMS algorithmParms;
+ UINT32 PCRInfoSize;
+ UINT8 *PCRInfo;
+ TPM_STORE_PUBKEY pubKey;
+ UINT32 encDataSize;
+ UINT8 *encData;
+} TPM_KEY;
+
+//
+// Part 2, section 10.3: TPM_KEY12
+// [size_is(encDataSize)] BYTE* encData;
+//
+typedef struct tdTPM_KEY12{
+ TPM_STRUCTURE_TAG tag;
+ UINT16 fill;
+ TPM_KEY_USAGE keyUsage;
+ TPM_KEY_FLAGS keyFlags;
+ TPM_AUTH_DATA_USAGE authDataUsage;
+ TPM_KEY_PARMS algorithmParms;
+ UINT32 PCRInfoSize;
+ UINT8 *PCRInfo;
+ TPM_STORE_PUBKEY pubKey;
+ UINT32 encDataSize;
+ UINT8 *encData;
+} TPM_KEY12;
+
+//
+// Part 2, section 10.7: TPM_STORE_PRIVKEY
+// [size_is(keyLength)] BYTE* key;
+//
+typedef struct tdTPM_STORE_PRIVKEY {
+ UINT32 keyLength;
+ UINT8 *key;
+} TPM_STORE_PRIVKEY;
+
+//
+// Part 2, section 10.6: TPM_STORE_ASYMKEY
+//
+typedef struct tdTPM_STORE_ASYMKEY { // pos len total
+ TPM_PAYLOAD_TYPE payload; // 0 1 1
+ TPM_SECRET usageAuth; // 1 20 21
+ TPM_SECRET migrationAuth; // 21 20 41
+ TPM_DIGEST pubDataDigest; // 41 20 61
+ TPM_STORE_PRIVKEY privKey; // 61 132-151 193-214
+} TPM_STORE_ASYMKEY;
+
+//
+// Part 2, section 10.8: TPM_MIGRATE_ASYMKEY
+// [size_is(partPrivKeyLen)] BYTE* partPrivKey;
+//
+typedef struct tdTPM_MIGRATE_ASYMKEY { // pos len total
+ TPM_PAYLOAD_TYPE payload; // 0 1 1
+ TPM_SECRET usageAuth; // 1 20 21
+ TPM_DIGEST pubDataDigest; // 21 20 41
+ UINT32 partPrivKeyLen; // 41 4 45
+ UINT8 *partPrivKey; // 45 112-127 157-172
+} TPM_MIGRATE_ASYMKEY;
+
+//
+// Part 2, section 10.9: TPM_KEY_CONTROL
+//
+#define TPM_KEY_CONTROL_OWNER_EVICT ((UINT32) 0x00000001)
+
+//
+// Part 2, section 11: Signed Structures
+//
+
+typedef struct tdTPM_CERTIFY_INFO
+{
+ TPM_STRUCT_VER version;
+ TPM_KEY_USAGE keyUsage;
+ TPM_KEY_FLAGS keyFlags;
+ TPM_AUTH_DATA_USAGE authDataUsage;
+ TPM_KEY_PARMS algorithmParms;
+ TPM_DIGEST pubkeyDigest;
+ TPM_NONCE data;
+ BOOLEAN parentPCRStatus;
+ UINT32 PCRInfoSize;
+ UINT8 *PCRInfo;
+} TPM_CERTIFY_INFO;
+
+typedef struct tdTPM_CERTIFY_INFO2
+{
+ TPM_STRUCTURE_TAG tag;
+ UINT8 fill;
+ TPM_PAYLOAD_TYPE payloadType;
+ TPM_KEY_USAGE keyUsage;
+ TPM_KEY_FLAGS keyFlags;
+ TPM_AUTH_DATA_USAGE authDataUsage;
+ TPM_KEY_PARMS algorithmParms;
+ TPM_DIGEST pubkeyDigest;
+ TPM_NONCE data;
+ BOOLEAN parentPCRStatus;
+ UINT32 PCRInfoSize;
+ UINT8 *PCRInfo;
+ UINT32 migrationAuthoritySize;
+ UINT8 *migrationAuthority;
+} TPM_CERTIFY_INFO2;
+
+typedef struct tdTPM_QUOTE_INFO
+{
+ TPM_STRUCT_VER version;
+ UINT8 fixed[4];
+ TPM_COMPOSITE_HASH digestValue;
+ TPM_NONCE externalData;
+} TPM_QUOTE_INFO;
+
+typedef struct tdTPM_QUOTE_INFO2
+{
+ TPM_STRUCTURE_TAG tag;
+ UINT8 fixed[4];
+ TPM_NONCE externalData;
+ TPM_PCR_INFO_SHORT infoShort;
+} TPM_QUOTE_INFO2;
+
+//
+// Part 2, section 12: Identity Structures
+//
+
+typedef struct tdTPM_EK_BLOB
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_EK_TYPE ekType;
+ UINT32 blobSize;
+ UINT8 *blob;
+} TPM_EK_BLOB;
+
+typedef struct tdTPM_EK_BLOB_ACTIVATE
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_SYMMETRIC_KEY sessionKey;
+ TPM_DIGEST idDigest;
+ TPM_PCR_INFO_SHORT pcrInfo;
+} TPM_EK_BLOB_ACTIVATE;
+
+typedef struct tdTPM_EK_BLOB_AUTH
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_SECRET authValue;
+} TPM_EK_BLOB_AUTH;
+
+
+// TPM_CHOSENID_HASH = SHA(identityLabel || privacyCA)
+typedef TPM_DIGEST TPM_CHOSENID_HASH;
+
+typedef struct tdTPM_IDENTITY_CONTENTS
+{
+ TPM_STRUCT_VER ver;
+ UINT32 ordinal;
+ TPM_CHOSENID_HASH labelPrivCADigest;
+ TPM_PUBKEY identityPubKey;
+} TPM_IDENTITY_CONTENTS;
+
+typedef struct tdTPM_IDENTITY_REQ
+{
+ UINT32 asymSize;
+ UINT32 symSize;
+ TPM_KEY_PARMS asymAlgorithm;
+ TPM_KEY_PARMS symAlgorithm;
+ UINT8 *asymBlob;
+ UINT8 *symBlob;
+} TPM_IDENTITY_REQ;
+
+typedef struct tdTPM_IDENTITY_PROOF
+{
+ TPM_STRUCT_VER ver;
+ UINT32 labelSize;
+ UINT32 identityBindingSize;
+ UINT32 endorsementSize;
+ UINT32 platformSize;
+ UINT32 conformanceSize;
+ TPM_PUBKEY identityKey;
+ UINT8 *labelArea;
+ UINT8 *identityBinding;
+ UINT8 *endorsementCredential;
+ UINT8 *platformCredential;
+ UINT8 *conformanceCredential;
+} TPM_IDENTITY_PROOF;
+
+typedef struct tdTPM_ASYM_CA_CONTENTS
+{
+ TPM_SYMMETRIC_KEY sessionKey;
+ TPM_DIGEST idDigest;
+} TPM_ASYM_CA_CONTENTS;
+
+typedef struct tdTPM_SYM_CA_ATTESTATION
+{
+ UINT32 credSize;
+ TPM_KEY_PARMS algorithm;
+ UINT8 *credential;
+} TPM_SYM_CA_ATTESTATION;
+
+//
+// Part 2, section 15: TPM_CURRENT_TICKS
+// Placed here out of order because definitions are used in section 13.
+//
+typedef struct tdTPM_CURRENT_TICKS {
+ TPM_STRUCTURE_TAG tag;
+ UINT64 currentTicks;
+ UINT16 tickRate;
+ TPM_NONCE tickNonce;
+} TPM_CURRENT_TICKS;
+
+//
+// Part 2, section 13: Transport structures
+//
+
+#define TPM_TRANSPORT_ENCRYPT ((UINT32)0x00000001)
+#define TPM_TRANSPORT_LOG ((UINT32)0x00000002)
+#define TPM_TRANSPORT_EXCLUSIVE ((UINT32)0x00000004)
+
+typedef struct tdTPM_TRANSPORT_PUBLIC
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_TRANSPORT_ATTRIBUTES transAttributes;
+ TPM_ALGORITHM_ID algId;
+ TPM_ENC_SCHEME encScheme;
+} TPM_TRANSPORT_PUBLIC;
+
+typedef struct tdTPM_TRANSPORT_INTERNAL
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_AUTHDATA authData;
+ TPM_TRANSPORT_PUBLIC transPublic;
+ TPM_TRANSHANDLE transHandle;
+ TPM_NONCE transNonceEven;
+ TPM_DIGEST transDigest;
+} TPM_TRANSPORT_INTERNAL;
+
+typedef struct tdTPM_TRANSPORT_LOG_IN
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST parameters;
+ TPM_DIGEST pubKeyHash;
+} TPM_TRANSPORT_LOG_IN;
+
+typedef struct tdTPM_TRANSPORT_LOG_OUT
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_CURRENT_TICKS currentTicks;
+ TPM_DIGEST parameters;
+ TPM_MODIFIER_INDICATOR locality;
+} TPM_TRANSPORT_LOG_OUT;
+
+typedef struct tdTPM_TRANSPORT_AUTH
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_AUTHDATA authData;
+} TPM_TRANSPORT_AUTH;
+
+//
+// Part 2, section 14: Audit Structures
+//
+
+typedef struct tdTPM_AUDIT_EVENT_IN
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST inputParms;
+ TPM_COUNTER_VALUE auditCount;
+} TPM_AUDIT_EVENT_IN;
+
+typedef struct tdTPM_AUDIT_EVENT_OUT
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_COMMAND_CODE ordinal;
+ TPM_DIGEST outputParms;
+ TPM_COUNTER_VALUE auditCount;
+ TPM_RESULT returnCode;
+} TPM_AUDIT_EVENT_OUT;
+
+//
+// Part 2, section 16: Return Codes
+//
+#ifndef TPM_BASE
+#error "TPM Error Codes require definition of TPM_BASE"
+#endif
+
+#define TPM_VENDOR_ERROR TPM_Vendor_Specific32
+#define TPM_NON_FATAL 0x00000800
+
+#define TPM_SUCCESS ((TPM_RESULT) TPM_BASE)
+#define TPM_AUTHFAIL ((TPM_RESULT) (TPM_BASE + 1))
+#define TPM_BADINDEX ((TPM_RESULT) (TPM_BASE + 2))
+#define TPM_BAD_PARAMETER ((TPM_RESULT) (TPM_BASE + 3))
+#define TPM_AUDITFAILURE ((TPM_RESULT) (TPM_BASE + 4))
+#define TPM_CLEAR_DISABLED ((TPM_RESULT) (TPM_BASE + 5))
+#define TPM_DEACTIVATED ((TPM_RESULT) (TPM_BASE + 6))
+#define TPM_DISABLED ((TPM_RESULT) (TPM_BASE + 7))
+#define TPM_DISABLED_CMD ((TPM_RESULT) (TPM_BASE + 8))
+#define TPM_FAIL ((TPM_RESULT) (TPM_BASE + 9))
+#define TPM_BAD_ORDINAL ((TPM_RESULT) (TPM_BASE + 10))
+#define TPM_INSTALL_DISABLED ((TPM_RESULT) (TPM_BASE + 11))
+#define TPM_INVALID_KEYHANDLE ((TPM_RESULT) (TPM_BASE + 12))
+#define TPM_KEYNOTFOUND ((TPM_RESULT) (TPM_BASE + 13))
+#define TPM_INAPPROPRIATE_ENC ((TPM_RESULT) (TPM_BASE + 14))
+#define TPM_MIGRATEFAIL ((TPM_RESULT) (TPM_BASE + 15))
+#define TPM_INVALID_PCR_INFO ((TPM_RESULT) (TPM_BASE + 16))
+#define TPM_NOSPACE ((TPM_RESULT) (TPM_BASE + 17))
+#define TPM_NOSRK ((TPM_RESULT) (TPM_BASE + 18))
+#define TPM_NOTSEALED_BLOB ((TPM_RESULT) (TPM_BASE + 19))
+#define TPM_OWNER_SET ((TPM_RESULT) (TPM_BASE + 20))
+#define TPM_RESOURCES ((TPM_RESULT) (TPM_BASE + 21))
+#define TPM_SHORTRANDOM ((TPM_RESULT) (TPM_BASE + 22))
+#define TPM_SIZE ((TPM_RESULT) (TPM_BASE + 23))
+#define TPM_WRONGPCRVAL ((TPM_RESULT) (TPM_BASE + 24))
+#define TPM_BAD_PARAM_SIZE ((TPM_RESULT) (TPM_BASE + 25))
+#define TPM_SHA_THREAD ((TPM_RESULT) (TPM_BASE + 26))
+#define TPM_SHA_ERROR ((TPM_RESULT) (TPM_BASE + 27))
+#define TPM_FAILEDSELFTEST ((TPM_RESULT) (TPM_BASE + 28))
+#define TPM_AUTH2FAIL ((TPM_RESULT) (TPM_BASE + 29))
+#define TPM_BADTAG ((TPM_RESULT) (TPM_BASE + 30))
+#define TPM_IOERROR ((TPM_RESULT) (TPM_BASE + 31))
+#define TPM_ENCRYPT_ERROR ((TPM_RESULT) (TPM_BASE + 32))
+#define TPM_DECRYPT_ERROR ((TPM_RESULT) (TPM_BASE + 33))
+#define TPM_INVALID_AUTHHANDLE ((TPM_RESULT) (TPM_BASE + 34))
+#define TPM_NO_ENDORSEMENT ((TPM_RESULT) (TPM_BASE + 35))
+#define TPM_INVALID_KEYUSAGE ((TPM_RESULT) (TPM_BASE + 36))
+#define TPM_WRONG_ENTITYTYPE ((TPM_RESULT) (TPM_BASE + 37))
+#define TPM_INVALID_POSTINIT ((TPM_RESULT) (TPM_BASE + 38))
+#define TPM_INAPPROPRIATE_SIG ((TPM_RESULT) (TPM_BASE + 39))
+#define TPM_BAD_KEY_PROPERTY ((TPM_RESULT) (TPM_BASE + 40))
+#define TPM_BAD_MIGRATION ((TPM_RESULT) (TPM_BASE + 41))
+#define TPM_BAD_SCHEME ((TPM_RESULT) (TPM_BASE + 42))
+#define TPM_BAD_DATASIZE ((TPM_RESULT) (TPM_BASE + 43))
+#define TPM_BAD_MODE ((TPM_RESULT) (TPM_BASE + 44))
+#define TPM_BAD_PRESENCE ((TPM_RESULT) (TPM_BASE + 45))
+#define TPM_BAD_VERSION ((TPM_RESULT) (TPM_BASE + 46))
+#define TPM_NO_WRAP_TRANSPORT ((TPM_RESULT) (TPM_BASE + 47))
+#define TPM_AUDITFAIL_UNSUCCESSFUL ((TPM_RESULT) (TPM_BASE + 48))
+#define TPM_AUDITFAIL_SUCCESSFUL ((TPM_RESULT) (TPM_BASE + 49))
+#define TPM_NOTRESETABLE ((TPM_RESULT) (TPM_BASE + 50))
+#define TPM_NOTLOCAL ((TPM_RESULT) (TPM_BASE + 51))
+#define TPM_BAD_TYPE ((TPM_RESULT) (TPM_BASE + 52))
+#define TPM_INVALID_RESOURCE ((TPM_RESULT) (TPM_BASE + 53))
+#define TPM_NOTFIPS ((TPM_RESULT) (TPM_BASE + 54))
+#define TPM_INVALID_FAMILY ((TPM_RESULT) (TPM_BASE + 55))
+#define TPM_NO_NV_PERMISSION ((TPM_RESULT) (TPM_BASE + 56))
+#define TPM_REQUIRES_SIGN ((TPM_RESULT) (TPM_BASE + 57))
+#define TPM_KEY_NOTSUPPORTED ((TPM_RESULT) (TPM_BASE + 58))
+#define TPM_AUTH_CONFLICT ((TPM_RESULT) (TPM_BASE + 59))
+#define TPM_AREA_LOCKED ((TPM_RESULT) (TPM_BASE + 60))
+#define TPM_BAD_LOCALITY ((TPM_RESULT) (TPM_BASE + 61))
+#define TPM_READ_ONLY ((TPM_RESULT) (TPM_BASE + 62))
+#define TPM_PER_NOWRITE ((TPM_RESULT) (TPM_BASE + 63))
+#define TPM_FAMILYCOUNT ((TPM_RESULT) (TPM_BASE + 64))
+#define TPM_WRITE_LOCKED ((TPM_RESULT) (TPM_BASE + 65))
+#define TPM_BAD_ATTRIBUTES ((TPM_RESULT) (TPM_BASE + 66))
+#define TPM_INVALID_STRUCTURE ((TPM_RESULT) (TPM_BASE + 67))
+#define TPM_KEY_OWNER_CONTROL ((TPM_RESULT) (TPM_BASE + 68))
+#define TPM_BAD_COUNTER ((TPM_RESULT) (TPM_BASE + 69))
+#define TPM_NOT_FULLWRITE ((TPM_RESULT) (TPM_BASE + 70))
+#define TPM_CONTEXT_GAP ((TPM_RESULT) (TPM_BASE + 71))
+#define TPM_MAXNVWRITES ((TPM_RESULT) (TPM_BASE + 72))
+#define TPM_NOOPERATOR ((TPM_RESULT) (TPM_BASE + 73))
+#define TPM_RESOURCEMISSING ((TPM_RESULT) (TPM_BASE + 74))
+#define TPM_DELEGATE_LOCK ((TPM_RESULT) (TPM_BASE + 75))
+#define TPM_DELEGATE_FAMILY ((TPM_RESULT) (TPM_BASE + 76))
+#define TPM_DELEGATE_ADMIN ((TPM_RESULT) (TPM_BASE + 77))
+#define TPM_TRANSPORT_NOTEXCLUSIVE ((TPM_RESULT) (TPM_BASE + 78))
+#define TPM_OWNER_CONTROL ((TPM_RESULT) (TPM_BASE + 79))
+#define TPM_DAA_RESOURCES ((TPM_RESULT) (TPM_BASE + 80))
+#define TPM_DAA_INPUT_DATA0 ((TPM_RESULT) (TPM_BASE + 81))
+#define TPM_DAA_INPUT_DATA1 ((TPM_RESULT) (TPM_BASE + 82))
+#define TPM_DAA_ISSUER_SETTINGS ((TPM_RESULT) (TPM_BASE + 83))
+#define TPM_DAA_TPM_SETTINGS ((TPM_RESULT) (TPM_BASE + 84))
+#define TPM_DAA_STAGE ((TPM_RESULT) (TPM_BASE + 85))
+#define TPM_DAA_ISSUER_VALIDITY ((TPM_RESULT) (TPM_BASE + 86))
+#define TPM_DAA_WRONG_W ((TPM_RESULT) (TPM_BASE + 87))
+#define TPM_BAD_HANDLE ((TPM_RESULT) (TPM_BASE + 88))
+#define TPM_BAD_DELEGATE ((TPM_RESULT) (TPM_BASE + 89))
+#define TPM_BADCONTEXT ((TPM_RESULT) (TPM_BASE + 90))
+#define TPM_TOOMANYCONTEXTS ((TPM_RESULT) (TPM_BASE + 91))
+#define TPM_MA_TICKET_SIGNATURE ((TPM_RESULT) (TPM_BASE + 92))
+#define TPM_MA_DESTINATION ((TPM_RESULT) (TPM_BASE + 93))
+#define TPM_MA_SOURCE ((TPM_RESULT) (TPM_BASE + 94))
+#define TPM_MA_AUTHORITY ((TPM_RESULT) (TPM_BASE + 95))
+#define TPM_PERMANENTEK ((TPM_RESULT) (TPM_BASE + 97))
+#define TPM_BAD_SIGNATURE ((TPM_RESULT) (TPM_BASE + 98))
+#define TPM_NOCONTEXTSPACE ((TPM_RESULT) (TPM_BASE + 99))
+
+#define TPM_RETRY ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL))
+#define TPM_NEEDS_SELFTEST ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 1))
+#define TPM_DOING_SELFTEST ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 2))
+#define TPM_DEFEND_LOCK_RUNNING ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 3))
+
+//
+// Part 2, section 17: Ordinals
+//
+// Ordinals are 32 bit values. The upper byte contains values that serve as
+// flag indicators, the next byte contains values indicating what committee
+// designated the ordinal, and the final two bytes contain the Command
+// Ordinal Index.
+// 3 2 1
+// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+// |P|C|V| Reserved| Purview | Command Ordinal Index |
+// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+//
+// Where:
+//
+// * P is Protected/Unprotected command. When 0 the command is a Protected
+// command, when 1 the command is an Unprotected command.
+//
+// * C is Non-Connection/Connection related command. When 0 this command
+// passes through to either the protected (TPM) or unprotected (TSS)
+// components.
+//
+// * V is TPM/Vendor command. When 0 the command is TPM defined, when 1 the
+// command is vendor defined.
+//
+// * All reserved area bits are set to 0.
+//
+
+#define TPM_ORD_ActivateIdentity ((TPM_COMMAND_CODE) 0x0000007A)
+#define TPM_ORD_AuthorizeMigrationKey ((TPM_COMMAND_CODE) 0x0000002B)
+#define TPM_ORD_CertifyKey ((TPM_COMMAND_CODE) 0x00000032)
+#define TPM_ORD_CertifyKey2 ((TPM_COMMAND_CODE) 0x00000033)
+#define TPM_ORD_CertifySelfTest ((TPM_COMMAND_CODE) 0x00000052)
+#define TPM_ORD_ChangeAuth ((TPM_COMMAND_CODE) 0x0000000C)
+#define TPM_ORD_ChangeAuthAsymFinish ((TPM_COMMAND_CODE) 0x0000000F)
+#define TPM_ORD_ChangeAuthAsymStart ((TPM_COMMAND_CODE) 0x0000000E)
+#define TPM_ORD_ChangeAuthOwner ((TPM_COMMAND_CODE) 0x00000010)
+#define TPM_ORD_CMK_ApproveMA ((TPM_COMMAND_CODE) 0x0000001D)
+#define TPM_ORD_CMK_ConvertMigration ((TPM_COMMAND_CODE) 0x00000024)
+#define TPM_ORD_CMK_CreateBlob ((TPM_COMMAND_CODE) 0x0000001B)
+#define TPM_ORD_CMK_CreateKey ((TPM_COMMAND_CODE) 0x00000013)
+#define TPM_ORD_CMK_CreateTicket ((TPM_COMMAND_CODE) 0x00000012)
+#define TPM_ORD_CMK_SetRestrictions ((TPM_COMMAND_CODE) 0x0000001C)
+#define TPM_ORD_ContinueSelfTest ((TPM_COMMAND_CODE) 0x00000053)
+#define TPM_ORD_ConvertMigrationBlob ((TPM_COMMAND_CODE) 0x0000002A)
+#define TPM_ORD_CreateCounter ((TPM_COMMAND_CODE) 0x000000DC)
+#define TPM_ORD_CreateEndorsementKeyPair ((TPM_COMMAND_CODE) 0x00000078)
+#define TPM_ORD_CreateMaintenanceArchive ((TPM_COMMAND_CODE) 0x0000002C)
+#define TPM_ORD_CreateMigrationBlob ((TPM_COMMAND_CODE) 0x00000028)
+#define TPM_ORD_CreateRevocableEK ((TPM_COMMAND_CODE) 0x0000007F)
+#define TPM_ORD_CreateWrapKey ((TPM_COMMAND_CODE) 0x0000001F)
+#define TPM_ORD_DAA_JOIN ((TPM_COMMAND_CODE) 0x00000029)
+#define TPM_ORD_DAA_SIGN ((TPM_COMMAND_CODE) 0x00000031)
+#define TPM_ORD_Delegate_CreateKeyDelegation ((TPM_COMMAND_CODE) 0x000000D4)
+#define TPM_ORD_Delegate_CreateOwnerDelegation ((TPM_COMMAND_CODE) 0x000000D5)
+#define TPM_ORD_Delegate_LoadOwnerDelegation ((TPM_COMMAND_CODE) 0x000000D8)
+#define TPM_ORD_Delegate_Manage ((TPM_COMMAND_CODE) 0x000000D2)
+#define TPM_ORD_Delegate_ReadTable ((TPM_COMMAND_CODE) 0x000000DB)
+#define TPM_ORD_Delegate_UpdateVerification ((TPM_COMMAND_CODE) 0x000000D1)
+#define TPM_ORD_Delegate_VerifyDelegation ((TPM_COMMAND_CODE) 0x000000D6)
+#define TPM_ORD_DirRead ((TPM_COMMAND_CODE) 0x0000001A)
+#define TPM_ORD_DirWriteAuth ((TPM_COMMAND_CODE) 0x00000019)
+#define TPM_ORD_DisableForceClear ((TPM_COMMAND_CODE) 0x0000005E)
+#define TPM_ORD_DisableOwnerClear ((TPM_COMMAND_CODE) 0x0000005C)
+#define TPM_ORD_DisablePubekRead ((TPM_COMMAND_CODE) 0x0000007E)
+#define TPM_ORD_DSAP ((TPM_COMMAND_CODE) 0x00000011)
+#define TPM_ORD_EstablishTransport ((TPM_COMMAND_CODE) 0x000000E6)
+#define TPM_ORD_EvictKey ((TPM_COMMAND_CODE) 0x00000022)
+#define TPM_ORD_ExecuteTransport ((TPM_COMMAND_CODE) 0x000000E7)
+#define TPM_ORD_Extend ((TPM_COMMAND_CODE) 0x00000014)
+#define TPM_ORD_FieldUpgrade ((TPM_COMMAND_CODE) 0x000000AA)
+#define TPM_ORD_FlushSpecific ((TPM_COMMAND_CODE) 0x000000BA)
+#define TPM_ORD_ForceClear ((TPM_COMMAND_CODE) 0x0000005D)
+#define TPM_ORD_GetAuditDigest ((TPM_COMMAND_CODE) 0x00000085)
+#define TPM_ORD_GetAuditDigestSigned ((TPM_COMMAND_CODE) 0x00000086)
+#define TPM_ORD_GetAuditEvent ((TPM_COMMAND_CODE) 0x00000082)
+#define TPM_ORD_GetAuditEventSigned ((TPM_COMMAND_CODE) 0x00000083)
+#define TPM_ORD_GetCapability ((TPM_COMMAND_CODE) 0x00000065)
+#define TPM_ORD_GetCapabilityOwner ((TPM_COMMAND_CODE) 0x00000066)
+#define TPM_ORD_GetCapabilitySigned ((TPM_COMMAND_CODE) 0x00000064)
+#define TPM_ORD_GetOrdinalAuditStatus ((TPM_COMMAND_CODE) 0x0000008C)
+#define TPM_ORD_GetPubKey ((TPM_COMMAND_CODE) 0x00000021)
+#define TPM_ORD_GetRandom ((TPM_COMMAND_CODE) 0x00000046)
+#define TPM_ORD_GetTestResult ((TPM_COMMAND_CODE) 0x00000054)
+#define TPM_ORD_GetTicks ((TPM_COMMAND_CODE) 0x000000F1)
+#define TPM_ORD_IncrementCounter ((TPM_COMMAND_CODE) 0x000000DD)
+#define TPM_ORD_Init ((TPM_COMMAND_CODE) 0x00000097)
+#define TPM_ORD_KeyControlOwner ((TPM_COMMAND_CODE) 0x00000023)
+#define TPM_ORD_KillMaintenanceFeature ((TPM_COMMAND_CODE) 0x0000002E)
+#define TPM_ORD_LoadAuthContext ((TPM_COMMAND_CODE) 0x000000B7)
+#define TPM_ORD_LoadContext ((TPM_COMMAND_CODE) 0x000000B9)
+#define TPM_ORD_LoadKey ((TPM_COMMAND_CODE) 0x00000020)
+#define TPM_ORD_LoadKey2 ((TPM_COMMAND_CODE) 0x00000041)
+#define TPM_ORD_LoadKeyContext ((TPM_COMMAND_CODE) 0x000000B5)
+#define TPM_ORD_LoadMaintenanceArchive ((TPM_COMMAND_CODE) 0x0000002D)
+#define TPM_ORD_LoadManuMaintPub ((TPM_COMMAND_CODE) 0x0000002F)
+#define TPM_ORD_MakeIdentity ((TPM_COMMAND_CODE) 0x00000079)
+#define TPM_ORD_MigrateKey ((TPM_COMMAND_CODE) 0x00000025)
+#define TPM_ORD_NV_DefineSpace ((TPM_COMMAND_CODE) 0x000000CC)
+#define TPM_ORD_NV_ReadValue ((TPM_COMMAND_CODE) 0x000000CF)
+#define TPM_ORD_NV_ReadValueAuth ((TPM_COMMAND_CODE) 0x000000D0)
+#define TPM_ORD_NV_WriteValue ((TPM_COMMAND_CODE) 0x000000CD)
+#define TPM_ORD_NV_WriteValueAuth ((TPM_COMMAND_CODE) 0x000000CE)
+#define TPM_ORD_OIAP ((TPM_COMMAND_CODE) 0x0000000A)
+#define TPM_ORD_OSAP ((TPM_COMMAND_CODE) 0x0000000B)
+#define TPM_ORD_OwnerClear ((TPM_COMMAND_CODE) 0x0000005B)
+#define TPM_ORD_OwnerReadInternalPub ((TPM_COMMAND_CODE) 0x00000081)
+#define TPM_ORD_OwnerReadPubek ((TPM_COMMAND_CODE) 0x0000007D)
+#define TPM_ORD_OwnerSetDisable ((TPM_COMMAND_CODE) 0x0000006E)
+#define TPM_ORD_PCR_Reset ((TPM_COMMAND_CODE) 0x000000C8)
+#define TPM_ORD_PcrRead ((TPM_COMMAND_CODE) 0x00000015)
+#define TPM_ORD_PhysicalDisable ((TPM_COMMAND_CODE) 0x00000070)
+#define TPM_ORD_PhysicalEnable ((TPM_COMMAND_CODE) 0x0000006F)
+#define TPM_ORD_PhysicalSetDeactivated ((TPM_COMMAND_CODE) 0x00000072)
+#define TPM_ORD_Quote ((TPM_COMMAND_CODE) 0x00000016)
+#define TPM_ORD_Quote2 ((TPM_COMMAND_CODE) 0x0000003E)
+#define TPM_ORD_ReadCounter ((TPM_COMMAND_CODE) 0x000000DE)
+#define TPM_ORD_ReadManuMaintPub ((TPM_COMMAND_CODE) 0x00000030)
+#define TPM_ORD_ReadPubek ((TPM_COMMAND_CODE) 0x0000007C)
+#define TPM_ORD_ReleaseCounter ((TPM_COMMAND_CODE) 0x000000DF)
+#define TPM_ORD_ReleaseCounterOwner ((TPM_COMMAND_CODE) 0x000000E0)
+#define TPM_ORD_ReleaseTransportSigned ((TPM_COMMAND_CODE) 0x000000E8)
+#define TPM_ORD_Reset ((TPM_COMMAND_CODE) 0x0000005A)
+#define TPM_ORD_ResetLockValue ((TPM_COMMAND_CODE) 0x00000040)
+#define TPM_ORD_RevokeTrust ((TPM_COMMAND_CODE) 0x00000080)
+#define TPM_ORD_SaveAuthContext ((TPM_COMMAND_CODE) 0x000000B6)
+#define TPM_ORD_SaveContext ((TPM_COMMAND_CODE) 0x000000B8)
+#define TPM_ORD_SaveKeyContext ((TPM_COMMAND_CODE) 0x000000B4)
+#define TPM_ORD_SaveState ((TPM_COMMAND_CODE) 0x00000098)
+#define TPM_ORD_Seal ((TPM_COMMAND_CODE) 0x00000017)
+#define TPM_ORD_Sealx ((TPM_COMMAND_CODE) 0x0000003D)
+#define TPM_ORD_SelfTestFull ((TPM_COMMAND_CODE) 0x00000050)
+#define TPM_ORD_SetCapability ((TPM_COMMAND_CODE) 0x0000003F)
+#define TPM_ORD_SetOperatorAuth ((TPM_COMMAND_CODE) 0x00000074)
+#define TPM_ORD_SetOrdinalAuditStatus ((TPM_COMMAND_CODE) 0x0000008D)
+#define TPM_ORD_SetOwnerInstall ((TPM_COMMAND_CODE) 0x00000071)
+#define TPM_ORD_SetOwnerPointer ((TPM_COMMAND_CODE) 0x00000075)
+#define TPM_ORD_SetRedirection ((TPM_COMMAND_CODE) 0x0000009A)
+#define TPM_ORD_SetTempDeactivated ((TPM_COMMAND_CODE) 0x00000073)
+#define TPM_ORD_SHA1Complete ((TPM_COMMAND_CODE) 0x000000A2)
+#define TPM_ORD_SHA1CompleteExtend ((TPM_COMMAND_CODE) 0x000000A3)
+#define TPM_ORD_SHA1Start ((TPM_COMMAND_CODE) 0x000000A0)
+#define TPM_ORD_SHA1Update ((TPM_COMMAND_CODE) 0x000000A1)
+#define TPM_ORD_Sign ((TPM_COMMAND_CODE) 0x0000003C)
+#define TPM_ORD_Startup ((TPM_COMMAND_CODE) 0x00000099)
+#define TPM_ORD_StirRandom ((TPM_COMMAND_CODE) 0x00000047)
+#define TPM_ORD_TakeOwnership ((TPM_COMMAND_CODE) 0x0000000D)
+#define TPM_ORD_Terminate_Handle ((TPM_COMMAND_CODE) 0x00000096)
+#define TPM_ORD_TickStampBlob ((TPM_COMMAND_CODE) 0x000000F2)
+#define TPM_ORD_UnBind ((TPM_COMMAND_CODE) 0x0000001E)
+#define TPM_ORD_Unseal ((TPM_COMMAND_CODE) 0x00000018)
+#define TSC_ORD_PhysicalPresence ((TPM_COMMAND_CODE) 0x4000000A)
+#define TSC_ORD_ResetEstablishmentBit ((TPM_COMMAND_CODE) 0x4000000B)
+
+//
+// Part 2, section 18: Context structures
+//
+
+typedef struct tdTPM_CONTEXT_BLOB
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_RESOURCE_TYPE resourceType;
+ TPM_HANDLE handle;
+ UINT8 label[16];
+ UINT32 contextCount;
+ TPM_DIGEST integrityDigest;
+ UINT32 additionalSize;
+ UINT8 *additionalData;
+ UINT32 sensitiveSize;
+ UINT8 *sensitiveData;
+} TPM_CONTEXT_BLOB;
+
+typedef struct tdTPM_CONTEXT_SENSITIVE
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_NONCE contextNonce;
+ UINT32 internalSize;
+ UINT8 *internalData;
+} TPM_CONTEXT_SENSITIVE;
+
+//
+// Part 2, section 19: NV Structures
+//
+
+#define TPM_NV_INDEX_LOCK ((UINT32)0xffffffff)
+#define TPM_NV_INDEX0 ((UINT32)0x00000000)
+#define TPM_NV_INDEX_DIR ((UINT32)0x10000001)
+#define TPM_NV_INDEX_EKCert ((UINT32)0x0000f000)
+#define TPM_NV_INDEX_TPM_CC ((UINT32)0x0000f001)
+#define TPM_NV_INDEX_PlatformCert ((UINT32)0x0000f002)
+#define TPM_NV_INDEX_Platform_CC ((UINT32)0x0000f003)
+// The following define ranges of reserved indices.
+#define TPM_NV_INDEX_TSS_BASE ((UINT32)0x00011100)
+#define TPM_NV_INDEX_PC_BASE ((UINT32)0x00011200)
+#define TPM_NV_INDEX_SERVER_BASE ((UINT32)0x00011300)
+#define TPM_NV_INDEX_MOBILE_BASE ((UINT32)0x00011400)
+#define TPM_NV_INDEX_PERIPHERAL_BASE ((UINT32)0x00011500)
+#define TPM_NV_INDEX_GROUP_RESV_BASE ((UINT32)0x00010000)
+
+typedef UINT32 TPM_NV_PER_ATTRIBUTES;
+// The typedefs TPM_NV_PER_ATTRIBUTES (not present in TPM 1.2 Spec. have been added
+// and structure fields that were to hold the following values
+#define TPM_NV_PER_READ_STCLEAR (((UINT32)1)<<31)
+#define TPM_NV_PER_AUTHREAD (((UINT32)1)<<18)
+#define TPM_NV_PER_OWNERREAD (((UINT32)1)<<17)
+#define TPM_NV_PER_PPREAD (((UINT32)1)<<16)
+#define TPM_NV_PER_GLOBALLOCK (((UINT32)1)<<15)
+#define TPM_NV_PER_WRITE_STCLEAR (((UINT32)1)<<14)
+#define TPM_NV_PER_WRITEDEFINE (((UINT32)1)<<13)
+#define TPM_NV_PER_WRITEALL (((UINT32)1)<<12)
+#define TPM_NV_PER_AUTHWRITE (((UINT32)1)<<2)
+#define TPM_NV_PER_OWNERWRITE (((UINT32)1)<<1)
+#define TPM_NV_PER_PPWRITE (((UINT32)1)<<0)
+
+typedef struct tdTPM_NV_ATTRIBUTES
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_NV_PER_ATTRIBUTES attributes;
+} TPM_NV_ATTRIBUTES;
+
+
+typedef struct tdTPM_NV_DATA_PUBLIC
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_NV_INDEX nvIndex;
+ TPM_PCR_INFO_SHORT pcrInfoRead;
+ TPM_PCR_INFO_SHORT pcrInfoWrite;
+ TPM_NV_ATTRIBUTES permission;
+ BOOLEAN bReadSTClear;
+ BOOLEAN bWriteSTClear;
+ BOOLEAN bWriteDefine;
+ UINT32 dataSize;
+} TPM_NV_DATA_PUBLIC;
+
+
+
+// Internal to TPM:
+//typedef struct tdTPM_NV_DATA_SENSITIVE
+//{
+// TPM_STRUCTURE_TAG tag;
+// TPM_NV_DATA_PUBLIC pubInfo;
+// TPM_AUTHDATA authValue;
+// UINT8 *data;
+//} TPM_NV_DATA_SENSITIVE;
+
+
+//
+// Part 2, section 20: Delegation
+//
+
+//
+// Part 2, section 20.3: Owner Permissions Settings for per1 bits
+//
+#define TPM_DELEGATE_SetOrdinalAuditStatus (((UINT32)1)<<30)
+#define TPM_DELEGATE_DirWriteAuth (((UINT32)1)<<29)
+#define TPM_DELEGATE_CMK_ApproveMA (((UINT32)1)<<28)
+#define TPM_DELEGATE_CMK_CreateTicket (((UINT32)1)<<26)
+#define TPM_DELEGATE_Delegate_LoadOwnerDelegation (((UINT32)1)<<24)
+#define TPM_DELEGATE_DAA_Join (((UINT32)1)<<23)
+#define TPM_DELEGATE_AuthorizeMigrationKey (((UINT32)1)<<22)
+#define TPM_DELEGATE_CreateMaintenanceArchive (((UINT32)1)<<21)
+#define TPM_DELEGATE_LoadMaintenanceArchive (((UINT32)1)<<20)
+#define TPM_DELEGATE_KillMaintenanceFeature (((UINT32)1)<<19)
+#define TPM_DELEGATE_OwnerReadInteralPub (((UINT32)1)<<18)
+#define TPM_DELEGATE_ResetLockValue (((UINT32)1)<<17)
+#define TPM_DELEGATE_OwnerClear (((UINT32)1)<<16)
+#define TPM_DELEGATE_DisableOwnerClear (((UINT32)1)<<15)
+#define TPM_DELEGATE_OwnerSetDisable (((UINT32)1)<<13)
+#define TPM_DELEGATE_SetCapability (((UINT32)1)<<12)
+#define TPM_DELEGATE_MakeIdentity (((UINT32)1)<<11)
+#define TPM_DELEGATE_ActivateIdentity (((UINT32)1)<<10)
+#define TPM_DELEGATE_OwnerReadPubek (((UINT32)1)<<9)
+#define TPM_DELEGATE_DisablePubekRead (((UINT32)1)<<8)
+#define TPM_DELEGATE_SetRedirection (((UINT32)1)<<7)
+#define TPM_DELEGATE_FieldUpgrade (((UINT32)1)<<6)
+#define TPM_DELEGATE_Delegate_UpdateVerification (((UINT32)1)<<5)
+#define TPM_DELEGATE_CreateCounter (((UINT32)1)<<4)
+#define TPM_DELEGATE_ReleaseCounterOwner (((UINT32)1)<<3)
+#define TPM_DELEGATE_DelegateManage (((UINT32)1)<<2)
+#define TPM_DELEGATE_Delegate_CreateOwnerDelegation (((UINT32)1)<<1)
+#define TPM_DELEGATE_DAA_Sign (((UINT32)1)<<0)
+
+//
+// Part 2, section 20.3: Key Permissions Settings for per1 bits
+//
+#define TPM_KEY_DELEGATE_CMK_ConvertMigration (((UINT32)1)<<28)
+#define TPM_KEY_DELEGATE_TickStampBlob (((UINT32)1)<<27)
+#define TPM_KEY_DELEGATE_ChangeAuthAsymStart (((UINT32)1)<<26)
+#define TPM_KEY_DELEGATE_ChangeAuthAsymFinish (((UINT32)1)<<25)
+#define TPM_KEY_DELEGATE_CMK_CreateKey (((UINT32)1)<<24)
+#define TPM_KEY_DELEGATE_MigrateKey (((UINT32)1)<<23)
+#define TPM_KEY_DELEGATE_LoadKey2 (((UINT32)1)<<22)
+#define TPM_KEY_DELEGATE_EstablishTransport (((UINT32)1)<<21)
+#define TPM_KEY_DELEGATE_ReleaseTransportSigned (((UINT32)1)<<20)
+#define TPM_KEY_DELEGATE_Quote2 (((UINT32)1)<<19)
+#define TPM_KEY_DELEGATE_Sealx (((UINT32)1)<<18)
+#define TPM_KEY_DELEGATE_MakeIdentity (((UINT32)1)<<17)
+#define TPM_KEY_DELEGATE_ActivateIdentity (((UINT32)1)<<16)
+#define TPM_KEY_DELEGATE_GetAuditDigestSigned (((UINT32)1)<<15)
+#define TPM_KEY_DELEGATE_Sign (((UINT32)1)<<14)
+#define TPM_KEY_DELEGATE_CertifyKey2 (((UINT32)1)<<13)
+#define TPM_KEY_DELEGATE_CertifyKey (((UINT32)1)<<12)
+#define TPM_KEY_DELEGATE_CreateWrapKey (((UINT32)1)<<11)
+#define TPM_KEY_DELEGATE_CMK_CreateBlob (((UINT32)1)<<10)
+#define TPM_KEY_DELEGATE_CreateMigrationBlob (((UINT32)1)<<9)
+#define TPM_KEY_DELEGATE_ConvertMigrationBlob (((UINT32)1)<<8)
+#define TPM_KEY_DELEGATE_CreateKeyDelegation (((UINT32)1)<<7)
+#define TPM_KEY_DELEGATE_ChangeAuth (((UINT32)1)<<6)
+#define TPM_KEY_DELEGATE_GetPubKey (((UINT32)1)<<5)
+#define TPM_KEY_DELEGATE_UnBind (((UINT32)1)<<4)
+#define TPM_KEY_DELEGATE_Quote (((UINT32)1)<<3)
+#define TPM_KEY_DELEGATE_Unseal (((UINT32)1)<<2)
+#define TPM_KEY_DELEGATE_Seal (((UINT32)1)<<1)
+#define TPM_KEY_DELEGATE_LoadKey (((UINT32)1)<<0)
+
+#define TPM_FAMILY_CREATE ((UINT32)0x00000001)
+#define TPM_FAMILY_ENABLE ((UINT32)0x00000002)
+#define TPM_FAMILY_ADMIN ((UINT32)0x00000003)
+#define TPM_FAMILY_INVALIDATE ((UINT32)0x00000004)
+
+#define TPM_FAMFLAG_DELEGATE_ADMIN_LOCK (((UINT32)1)<<1)
+#define TPM_FAMFLAG_ENABLE (((UINT32)1)<<0)
+
+typedef struct tdTPM_FAMILY_LABEL
+{
+ UINT8 label;
+} TPM_FAMILY_LABEL;
+
+typedef struct tdTPM_FAMILY_TABLE_ENTRY
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_FAMILY_LABEL label;
+ TPM_FAMILY_ID familyID;
+ TPM_FAMILY_VERIFICATION verificationCount;
+ TPM_FAMILY_FLAGS flags;
+} TPM_FAMILY_TABLE_ENTRY;
+
+#define TPM_FAMILY_TABLE_ENTRY_MIN 8
+//typedef struct tdTPM_FAMILY_TABLE
+//{
+// TPM_FAMILY_TABLE_ENTRY FamTableRow[TPM_NUM_FAMILY_TABLE_ENTRY_MIN];
+//} TPM_FAMILY_TABLE;
+
+
+typedef struct tdTPM_DELEGATE_LABEL
+{
+ UINT8 label;
+} TPM_DELEGATE_LABEL;
+
+
+typedef UINT32 TPM_DELEGATE_TYPE;
+#define TPM_DEL_OWNER_BITS ((UINT32)0x00000001)
+#define TPM_DEL_KEY_BITS ((UINT32)0x00000002)
+
+typedef struct tdTPM_DELEGATIONS
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DELEGATE_TYPE delegateType;
+ UINT32 per1;
+ UINT32 per2;
+} TPM_DELEGATIONS;
+
+typedef struct tdTPM_DELEGATE_PUBLIC
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DELEGATE_LABEL label;
+ TPM_PCR_INFO_SHORT pcrInfo;
+ TPM_DELEGATIONS permissions;
+ TPM_FAMILY_ID familyID;
+ TPM_FAMILY_VERIFICATION verificationCount;
+} TPM_DELEGATE_PUBLIC;
+
+typedef struct tdTPM_DELEGATE_TABLE_ROW
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DELEGATE_PUBLIC pub;
+ TPM_SECRET authValue;
+} TPM_DELEGATE_TABLE_ROW;
+
+
+#define TPM_NUM_DELEGATE_TABLE_ENTRY_MIN 2
+//typedef struct tdTPM_DELEGATE_TABLE
+//{
+// TPM_DELEGATE_TABLE_ROW delRow[TPM_NUM_DELEGATE_TABLE_ENTRY_MIN];
+//} TPM_DELEGATE_TABLE;
+
+typedef struct tdTPM_DELEGATE_SENSITIVE
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_SECRET authValue;
+} TPM_DELEGATE_SENSITIVE;
+
+typedef struct tdTPM_DELEGATE_OWNER_BLOB
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DELEGATE_PUBLIC pub;
+ TPM_DIGEST integrityDigest;
+ UINT32 additionalSize;
+ UINT8 *additionalArea;
+ UINT32 sensitiveSize;
+ UINT8 *sensitiveArea;
+} TPM_DELEGATE_OWNER_BLOB;
+
+typedef struct tdTPM_DELEGATE_KEY_BLOB
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DELEGATE_PUBLIC pub;
+ TPM_DIGEST integrityDigest;
+ TPM_DIGEST pubKeyDigest;
+ UINT32 additionalSize;
+ UINT8 *additionalArea;
+ UINT32 sensitiveSize;
+ UINT8 *sensitiveArea;
+} TPM_DELEGATE_KEY_BLOB;
+
+//
+// Part 2, section 21.1: TPM_CAPABILITY_AREA for GetCapability
+//
+#define TPM_CAP_ORD ((TPM_CAPABILITY_AREA) 0x00000001)
+#define TPM_CAP_ALG ((TPM_CAPABILITY_AREA) 0x00000002)
+#define TPM_CAP_PID ((TPM_CAPABILITY_AREA) 0x00000003)
+#define TPM_CAP_FLAG ((TPM_CAPABILITY_AREA) 0x00000004)
+#define TPM_CAP_PROPERTY ((TPM_CAPABILITY_AREA) 0x00000005)
+#define TPM_CAP_VERSION ((TPM_CAPABILITY_AREA) 0x00000006)
+#define TPM_CAP_KEY_HANDLE ((TPM_CAPABILITY_AREA) 0x00000007)
+#define TPM_CAP_CHECK_LOADED ((TPM_CAPABILITY_AREA) 0x00000008)
+#define TPM_CAP_SYM_MODE ((TPM_CAPABILITY_AREA) 0x00000009)
+#define TPM_CAP_KEY_STATUS ((TPM_CAPABILITY_AREA) 0x0000000C)
+#define TPM_CAP_NV_LIST ((TPM_CAPABILITY_AREA) 0x0000000D)
+#define TPM_CAP_MFR ((TPM_CAPABILITY_AREA) 0x00000010)
+#define TPM_CAP_NV_INDEX ((TPM_CAPABILITY_AREA) 0x00000011)
+#define TPM_CAP_TRANS_ALG ((TPM_CAPABILITY_AREA) 0x00000012)
+#define TPM_CAP_HANDLE ((TPM_CAPABILITY_AREA) 0x00000014)
+#define TPM_CAP_TRANS_ES ((TPM_CAPABILITY_AREA) 0x00000015)
+#define TPM_CAP_AUTH_ENCRYPT ((TPM_CAPABILITY_AREA) 0x00000017)
+#define TPM_CAP_SELECT_SIZE ((TPM_CAPABILITY_AREA) 0x00000018)
+#define TPM_CAP_VERSION_VAL ((TPM_CAPABILITY_AREA) 0x0000001A)
+
+#define TPM_CAP_FLAG_PERMANENT ((TPM_CAPABILITY_AREA) 0x00000108)
+#define TPM_CAP_FLAG_VOLATILE ((TPM_CAPABILITY_AREA) 0x00000109)
+
+//
+// Part 2, section 21.2: CAP_PROPERTY Subcap values for GetCapability
+//
+#define TPM_CAP_PROP_PCR ((TPM_CAPABILITY_AREA) 0x00000101)
+#define TPM_CAP_PROP_DIR ((TPM_CAPABILITY_AREA) 0x00000102)
+#define TPM_CAP_PROP_MANUFACTURER ((TPM_CAPABILITY_AREA) 0x00000103)
+#define TPM_CAP_PROP_KEYS ((TPM_CAPABILITY_AREA) 0x00000104)
+#define TPM_CAP_PROP_MIN_COUNTER ((TPM_CAPABILITY_AREA) 0x00000107)
+#define TPM_CAP_PROP_AUTHSESS ((TPM_CAPABILITY_AREA) 0x0000010A)
+#define TPM_CAP_PROP_TRANSESS ((TPM_CAPABILITY_AREA) 0x0000010B)
+#define TPM_CAP_PROP_COUNTERS ((TPM_CAPABILITY_AREA) 0x0000010C)
+#define TPM_CAP_PROP_MAX_AUTHSESS ((TPM_CAPABILITY_AREA) 0x0000010D)
+#define TPM_CAP_PROP_MAX_TRANSESS ((TPM_CAPABILITY_AREA) 0x0000010E)
+#define TPM_CAP_PROP_MAX_COUNTERS ((TPM_CAPABILITY_AREA) 0x0000010F)
+#define TPM_CAP_PROP_MAX_KEYS ((TPM_CAPABILITY_AREA) 0x00000110)
+#define TPM_CAP_PROP_OWNER ((TPM_CAPABILITY_AREA) 0x00000111)
+#define TPM_CAP_PROP_CONTEXT ((TPM_CAPABILITY_AREA) 0x00000112)
+#define TPM_CAP_PROP_MAX_CONTEXT ((TPM_CAPABILITY_AREA) 0x00000113)
+#define TPM_CAP_PROP_FAMILYROWS ((TPM_CAPABILITY_AREA) 0x00000114)
+#define TPM_CAP_PROP_TIS_TIMEOUT ((TPM_CAPABILITY_AREA) 0x00000115)
+#define TPM_CAP_PROP_STARTUP_EFFECT ((TPM_CAPABILITY_AREA) 0x00000116)
+#define TPM_CAP_PROP_DELEGATE_ROW ((TPM_CAPABILITY_AREA) 0x00000117)
+#define TPM_CAP_PROP_DAA_MAX ((TPM_CAPABILITY_AREA) 0x00000119)
+#define CAP_PROP_SESSION_DAA ((TPM_CAPABILITY_AREA) 0x0000011A)
+#define TPM_CAP_PROP_CONTEXT_DIST ((TPM_CAPABILITY_AREA) 0x0000011B)
+#define TPM_CAP_PROP_DAA_INTERRUPT ((TPM_CAPABILITY_AREA) 0x0000011C)
+#define TPM_CAP_PROP_SESSIONS ((TPM_CAPABILITY_AREA) 0x0000011D)
+#define TPM_CAP_PROP_MAX_SESSIONS ((TPM_CAPABILITY_AREA) 0x0000011E)
+#define TPM_CAP_PROP_CMK_RESTRICTION ((TPM_CAPABILITY_AREA) 0x0000011F)
+#define TPM_CAP_PROP_DURATION ((TPM_CAPABILITY_AREA) 0x00000120)
+#define TPM_CAP_PROP_ACTIVE_COUNTER ((TPM_CAPABILITY_AREA) 0x00000122)
+#define TPM_CAP_PROP_MAX_NV_AVAILABLE ((TPM_CAPABILITY_AREA) 0x00000123)
+#define TPM_CAP_PROP_INPUT_BUFFER ((TPM_CAPABILITY_AREA) 0x00000124)
+
+//
+// Part 2, section 21.6: TPM_CAP_VERSION_INFO
+// [size_is(vendorSpecificSize)] BYTE* vendorSpecific;
+//
+typedef struct tdTPM_CAP_VERSION_INFO {
+ TPM_STRUCTURE_TAG tag;
+ TPM_VERSION version;
+ UINT16 specLevel;
+ UINT8 errataRev;
+ UINT8 tpmVendorID[4];
+ UINT16 vendorSpecificSize;
+ UINT8 *vendorSpecific;
+} TPM_CAP_VERSION_INFO;
+
+//
+// Part 2, section 22: DAA Structures
+//
+
+#define TPM_DAA_SIZE_r0 (43)
+#define TPM_DAA_SIZE_r1 (43)
+#define TPM_DAA_SIZE_r2 (128)
+#define TPM_DAA_SIZE_r3 (168)
+#define TPM_DAA_SIZE_r4 (219)
+#define TPM_DAA_SIZE_NT (20)
+#define TPM_DAA_SIZE_v0 (128)
+#define TPM_DAA_SIZE_v1 (192)
+#define TPM_DAA_SIZE_NE (256)
+#define TPM_DAA_SIZE_w (256)
+#define TPM_DAA_SIZE_issuerModulus (256)
+#define TPM_DAA_power0 (104)
+#define TPM_DAA_power1 (1024)
+
+typedef struct tdTPM_DAA_ISSUER
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST DAA_digest_R0;
+ TPM_DIGEST DAA_digest_R1;
+ TPM_DIGEST DAA_digest_S0;
+ TPM_DIGEST DAA_digest_S1;
+ TPM_DIGEST DAA_digest_n;
+ TPM_DIGEST DAA_digest_gamma;
+ UINT8 DAA_generic_q[26];
+} TPM_DAA_ISSUER;
+
+
+typedef struct tdTPM_DAA_TPM
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST DAA_digestIssuer;
+ TPM_DIGEST DAA_digest_v0;
+ TPM_DIGEST DAA_digest_v1;
+ TPM_DIGEST DAA_rekey;
+ UINT32 DAA_count;
+} TPM_DAA_TPM;
+
+typedef struct tdTPM_DAA_CONTEXT
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST DAA_digestContext;
+ TPM_DIGEST DAA_digest;
+ TPM_DAA_CONTEXT_SEED DAA_contextSeed;
+ UINT8 DAA_scratch[256];
+ UINT8 DAA_stage;
+} TPM_DAA_CONTEXT;
+
+typedef struct tdTPM_DAA_JOINDATA
+{
+ UINT8 DAA_join_u0[128];
+ UINT8 DAA_join_u1[138];
+ TPM_DIGEST DAA_digest_n0;
+} TPM_DAA_JOINDATA;
+
+typedef struct tdTPM_DAA_BLOB
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_RESOURCE_TYPE resourceType;
+ UINT8 label[16];
+ TPM_DIGEST blobIntegrity;
+ UINT32 additionalSize;
+ UINT8 *additionalData;
+ UINT32 sensitiveSize;
+ UINT8 *sensitiveData;
+} TPM_DAA_BLOB;
+
+typedef struct tdTPM_DAA_SENSITIVE
+{
+ TPM_STRUCTURE_TAG tag;
+ UINT32 internalSize;
+ UINT8 *internalData;
+} TPM_DAA_SENSITIVE;
+
+
+//
+// Part 2, section 23: Redirection
+//
+
+// This section of the TPM spec defines exactly one value but does not
+// give it a name. The definition of TPM_SetRedirection in Part3
+// refers to exactly one name but does not give its value. We join
+// them here.
+#define TPM_REDIR_GPIO (0x00000001)
+
+//
+// TPM Command & Response Headers
+//
+typedef struct tdTPM_RQU_COMMAND_HDR {
+ TPM_STRUCTURE_TAG tag;
+ UINT32 paramSize;
+ TPM_COMMAND_CODE ordinal;
+} TPM_RQU_COMMAND_HDR;
+
+typedef struct tdTPM_RSP_COMMAND_HDR {
+ TPM_STRUCTURE_TAG tag;
+ UINT32 paramSize;
+ TPM_RESULT returnCode;
+} TPM_RSP_COMMAND_HDR;
+
+#pragma pack (pop)
+
+#endif // _TPM12_H_
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/WatchdogDescriptionTable.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/WatchdogDescriptionTable.h new file mode 100644 index 0000000000..8a23e7e07e --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/WatchdogDescriptionTable.h @@ -0,0 +1,94 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ WatchdogDescriptionTable.h
+
+Abstract:
+
+ ACPI Watchdog Description Table as defined in Intel
+ ICH Family Watchdog Timer (WDT) Application Note (AP-725)
+
+--*/
+
+#ifndef _WATCH_DOG_DESCRIPTION_TABLE_H_
+#define _WATCH_DOG_DESCRIPTION_TABLE_H_
+
+//
+// Include files
+//
+#include "Acpi2_0.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// WDDT structure
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT16 SpecVersion;
+ UINT16 TableVersion;
+ UINT16 Vid;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;
+ UINT16 TimerMaxCount;
+ UINT16 TimerMinCount;
+ UINT16 TimerCountPeriod;
+ UINT16 Status;
+ UINT16 Capability;
+} EFI_ACPI_1_0_WATCH_DOG_DESCRIPTION_TABLE;
+
+//
+// "WDDT" Watchdog Description Table signatures
+//
+#define EFI_ACPI_1_0_WDDT_SIGNATURE 0x54444457
+
+#pragma pack()
+
+//
+// WDDT Revision
+//
+#define EFI_ACPI_WATCHDOG_DESCRIPTION_1_0_TABLE_REVISION 0x01
+
+//
+// WDDT Spec Version
+//
+#define EFI_ACPI_WDDT_SPEC_1_0_VERSION 0x01
+
+//
+// WDDT Description Table Version
+//
+#define EFI_ACPI_WDDT_TABLE_1_0_VERSION 0x01
+
+//
+// WDT Status
+//
+#define EFI_ACPI_WDDT_STATUS_AVAILABLE 0x0001
+#define EFI_ACPI_WDDT_STATUS_ACTIVE 0x0002
+#define EFI_ACPI_WDDT_STATUS_OWNED_BY_BIOS 0x0000
+#define EFI_ACPI_WDDT_STATUS_OWNED_BY_OS 0x0004
+#define EFI_ACPI_WDDT_STATUS_USER_RESET_EVENT 0x0800
+#define EFI_ACPI_WDDT_STATUS_WDT_EVENT 0x1000
+#define EFI_ACPI_WDDT_STATUS_POWER_FAIL_EVENT 0x2000
+#define EFI_ACPI_WDDT_STATUS_UNKNOWN_RESET_EVENT 0x4000
+
+//
+// WDT Capability
+//
+#define EFI_ACPI_WDDT_CAPABILITY_AUTO_RESET 0x0001
+#define EFI_ACPI_WDDT_CAPABILITY_ALERT_SUPPORT 0x0002
+#define EFI_ACPI_WDDT_CAPABILITY_PLATFORM_SHUTDOWN 0x0004
+#define EFI_ACPI_WDDT_CAPABILITY_IMMEDIATE_SHUTDOWN 0x0008
+#define EFI_ACPI_WDDT_CAPABILITY_BIOS_HANDOFF_SUPPORT 0x0010
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/atapi.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/atapi.h new file mode 100644 index 0000000000..3fcc287a5a --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/atapi.h @@ -0,0 +1,331 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ Atapi.h
+
+Abstract:
+
+
+Revision History
+--*/
+
+#ifndef _ATAPI_H
+#define _ATAPI_H
+
+#include "Tiano.h"
+
+#pragma pack(1)
+
+typedef struct {
+ UINT16 config; /* General Configuration */
+ UINT16 cylinders; /* Number of Cylinders */
+ UINT16 reserved_2;
+ UINT16 heads; /* Number of logical heads */
+ UINT16 vendor_data1;
+ UINT16 vendoe_data2;
+ UINT16 sectors_per_track;
+ UINT16 vendor_specific_7_9[3];
+ CHAR8 SerialNo[20]; /* ASCII */
+ UINT16 vendor_specific_20_21[2];
+ UINT16 ecc_bytes_available;
+ CHAR8 FirmwareVer[8]; /* ASCII */
+ CHAR8 ModelName[40]; /* ASCII */
+ UINT16 multi_sector_cmd_max_sct_cnt;
+ UINT16 reserved_48;
+ UINT16 capabilities;
+ UINT16 reserved_50;
+ UINT16 pio_cycle_timing;
+ UINT16 reserved_52;
+ UINT16 field_validity;
+ UINT16 current_cylinders;
+ UINT16 current_heads;
+ UINT16 current_sectors;
+ UINT16 CurrentCapacityLsb;
+ UINT16 CurrentCapacityMsb;
+ UINT16 reserved_59;
+ UINT16 user_addressable_sectors_lo;
+ UINT16 user_addressable_sectors_hi;
+ UINT16 reserved_62;
+ UINT16 multi_word_dma_mode;
+ UINT16 advanced_pio_modes;
+ UINT16 min_multi_word_dma_cycle_time;
+ UINT16 rec_multi_word_dma_cycle_time;
+ UINT16 min_pio_cycle_time_without_flow_control;
+ UINT16 min_pio_cycle_time_with_flow_control;
+ UINT16 reserved_69_79[11];
+ UINT16 major_version_no;
+ UINT16 minor_version_no;
+ UINT16 reserved_82_127[46];
+ UINT16 security_status;
+ UINT16 vendor_data_129_159[31];
+ UINT16 reserved_160_255[96];
+} IDENTIFY;
+
+typedef struct {
+ UINT8 peripheral_type;
+ UINT8 RMB;
+ UINT8 version;
+ UINT8 response_data_format;
+ UINT8 addnl_length;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 reserved_7;
+ UINT8 vendor_info[8];
+ UINT8 product_id[12];
+ UINT8 eeprom_product_code[4];
+ UINT8 firmware_rev_level[4];
+ UINT8 firmware_sub_rev_level[1];
+ UINT8 reserved_37;
+ UINT8 reserved_38;
+ UINT8 reserved_39;
+ UINT8 max_capacity_hi;
+ UINT8 max_capacity_mid;
+ UINT8 max_capacity_lo;
+ UINT8 reserved_43_95[95 - 43 + 1];
+ UINT8 vendor_id[20];
+ UINT8 eeprom_drive_sno[12];
+} INQUIRY_DATA;
+
+typedef struct {
+ UINT8 error_code : 7;
+ UINT8 valid : 1;
+ UINT8 reserved_1;
+ UINT8 sense_key : 4;
+ UINT8 reserved_21 : 1;
+ UINT8 ILI : 1;
+ UINT8 reserved_22 : 2;
+ UINT8 vendor_specific_3;
+ UINT8 vendor_specific_4;
+ UINT8 vendor_specific_5;
+ UINT8 vendor_specific_6;
+ UINT8 addnl_sense_length; // n - 7
+ UINT8 vendor_specific_8;
+ UINT8 vendor_specific_9;
+ UINT8 vendor_specific_10;
+ UINT8 vendor_specific_11;
+ UINT8 addnl_sense_code; // mandatory
+ UINT8 addnl_sense_code_qualifier; // mandatory
+ UINT8 field_replaceable_unit_code; // optional
+ UINT8 reserved_15;
+ UINT8 reserved_16;
+ UINT8 reserved_17;
+ //
+ // Followed by additional sense bytes : FIXME
+ //
+} REQUEST_SENSE_DATA;
+
+typedef struct {
+ UINT8 LastLba3;
+ UINT8 LastLba2;
+ UINT8 LastLba1;
+ UINT8 LastLba0;
+ UINT8 BlockSize3;
+ UINT8 BlockSize2;
+ UINT8 BlockSize1;
+ UINT8 BlockSize0;
+} READ_CAPACITY_DATA;
+
+typedef struct {
+ UINT8 reserved_0;
+ UINT8 reserved_1;
+ UINT8 reserved_2;
+ UINT8 Capacity_Length;
+ UINT8 LastLba3;
+ UINT8 LastLba2;
+ UINT8 LastLba1;
+ UINT8 LastLba0;
+ UINT8 DesCode : 2;
+ UINT8 reserved_9 : 6;
+ UINT8 BlockSize2;
+ UINT8 BlockSize1;
+ UINT8 BlockSize0;
+} READ_FORMAT_CAPACITY_DATA;
+
+#pragma pack()
+//
+// ATAPI Command
+//
+#define ATAPI_SOFT_RESET_CMD 0x08
+#define PACKET_CMD 0xA0
+#define ATAPI_IDENTIFY_DEVICE_CMD 0xA1
+#define ATAPI_SERVICE_CMD 0xA2
+
+//
+// ATAPI Packet Command
+//
+#pragma pack(1)
+
+typedef struct {
+ UINT8 opcode;
+ UINT8 reserved_1;
+ UINT8 reserved_2;
+ UINT8 reserved_3;
+ UINT8 reserved_4;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 reserved_7;
+ UINT8 reserved_8;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
+} TEST_UNIT_READY_CMD;
+
+typedef struct {
+ UINT8 opcode;
+ UINT8 reserved_1 : 4;
+ UINT8 lun : 4;
+ UINT8 page_code;
+ UINT8 reserved_3;
+ UINT8 allocation_length;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 reserved_7;
+ UINT8 reserved_8;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
+} INQUIRY_CMD;
+
+typedef struct {
+ UINT8 opcode;
+ UINT8 reserved_1 : 4;
+ UINT8 lun : 4;
+ UINT8 reserved_2;
+ UINT8 reserved_3;
+ UINT8 allocation_length;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 reserved_7;
+ UINT8 reserved_8;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
+} REQUEST_SENSE_CMD;
+
+typedef struct {
+ UINT8 opcode;
+ UINT8 reserved_1 : 5;
+ UINT8 lun : 3;
+ UINT8 Lba0;
+ UINT8 Lba1;
+ UINT8 Lba2;
+ UINT8 Lba3;
+ UINT8 reserved_6;
+ UINT8 TranLen0;
+ UINT8 TranLen1;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
+} READ10_CMD;
+
+typedef struct {
+ UINT8 opcode;
+ UINT8 reserved_1;
+ UINT8 reserved_2;
+ UINT8 reserved_3;
+ UINT8 reserved_4;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 allocation_length_hi;
+ UINT8 allocation_length_lo;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
+} READ_FORMAT_CAP_CMD;
+
+typedef struct {
+ UINT8 peripheral_type;
+ UINT8 RMB;
+ UINT8 version;
+ UINT8 response_data_format;
+ UINT8 addnl_length;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 reserved_7;
+ UINT8 vendor_info[8];
+ UINT8 product_id[12];
+ UINT8 eeprom_product_code[4];
+ UINT8 firmware_rev_level[4];
+} USB_INQUIRY_DATA;
+
+typedef union {
+ UINT16 Data16[6];
+ TEST_UNIT_READY_CMD TestUnitReady;
+ READ10_CMD Read10;
+ REQUEST_SENSE_CMD RequestSence;
+ INQUIRY_CMD Inquiry;
+ READ_FORMAT_CAP_CMD ReadFormatCapacity;
+} ATAPI_PACKET_COMMAND;
+
+#pragma pack()
+//
+// Packet Command Code
+//
+#define TEST_UNIT_READY 0x00
+#define REQUEST_SENSE 0x03
+#define INQUIRY 0x12
+#define READ_FORMAT_CAPACITY 0x23
+#define READ_CAPACITY 0x25
+#define READ_10 0x28
+
+#define DEFAULT_CTL (0x0a) // default content of device control register, disable INT
+#define DEFAULT_CMD (0xa0)
+
+#define MAX_ATAPI_BYTE_COUNT (0xfffe)
+
+//
+// Sense Key
+//
+#define REQUEST_SENSE_ERROR (0x70)
+#define SK_NO_SENSE (0x0)
+#define SK_RECOVERY_ERROR (0x1)
+#define SK_NOT_READY (0x2)
+#define SK_MEDIUM_ERROR (0x3)
+#define SK_HARDWARE_ERROR (0x4)
+#define SK_ILLEGAL_REQUEST (0x5)
+#define SK_UNIT_ATTENTION (0x6)
+#define SK_DATA_PROTECT (0x7)
+#define SK_BLANK_CHECK (0x8)
+#define SK_VENDOR_SPECIFIC (0x9)
+#define SK_RESERVED_A (0xA)
+#define SK_ABORT (0xB)
+#define SK_RESERVED_C (0xC)
+#define SK_OVERFLOW (0xD)
+#define SK_MISCOMPARE (0xE)
+#define SK_RESERVED_F (0xF)
+
+//
+// Additional Sense Codes
+//
+#define ASC_NOT_READY (0x04)
+#define ASC_MEDIA_ERR1 (0x10)
+#define ASC_MEDIA_ERR2 (0x11)
+#define ASC_MEDIA_ERR3 (0x14)
+#define ASC_MEDIA_ERR4 (0x30)
+#define ASC_MEDIA_UPSIDE_DOWN (0x06)
+#define ASC_INVALID_CMD (0x20)
+#define ASC_LBA_OUT_OF_RANGE (0x21)
+#define ASC_INVALID_FIELD (0x24)
+#define ASC_WRITE_PROTECTED (0x27)
+#define ASC_MEDIA_CHANGE (0x28)
+#define ASC_RESET (0x29) /* Power On Reset or Bus Reset occurred */
+#define ASC_ILLEGAL_FIELD (0x26)
+#define ASC_NO_MEDIA (0x3A)
+#define ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
+
+//
+// Additional Sense Code Qualifier
+//
+#define ASCQ_IN_PROGRESS (0x01)
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci.h new file mode 100644 index 0000000000..aa0668b9dc --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci.h @@ -0,0 +1,31 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ pci.h
+
+Abstract:
+ Support for PCI standard.
+
+Revision History
+
+--*/
+
+#ifndef _PCI_H
+#define _PCI_H
+
+#include "pci22.h"
+#include "pci23.h"
+#include "pci30.h"
+#include "EfiPci.h"
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci22.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci22.h new file mode 100644 index 0000000000..77aebb69e6 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci22.h @@ -0,0 +1,555 @@ +/*++
+
+Copyright (c) 2004 - 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ pci22.h
+
+Abstract:
+ Support for PCI 2.2 standard.
+
+Revision History
+
+--*/
+
+#ifndef _PCI22_H
+#define _PCI22_H
+
+#define PCI_MAX_SEGMENT 0
+
+#define PCI_MAX_BUS 255
+
+#define PCI_MAX_DEVICE 31
+#define PCI_MAX_FUNC 7
+
+//
+// Command
+//
+#define PCI_VGA_PALETTE_SNOOP_DISABLED 0x20
+
+#pragma pack(push, 1)
+typedef struct {
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT16 Command;
+ UINT16 Status;
+ UINT8 RevisionID;
+ UINT8 ClassCode[3];
+ UINT8 CacheLineSize;
+ UINT8 LatencyTimer;
+ UINT8 HeaderType;
+ UINT8 BIST;
+} PCI_DEVICE_INDEPENDENT_REGION;
+
+typedef struct {
+ UINT32 Bar[6];
+ UINT32 CISPtr;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemID;
+ UINT32 ExpansionRomBar;
+ UINT8 CapabilityPtr;
+ UINT8 Reserved1[3];
+ UINT32 Reserved2;
+ UINT8 InterruptLine;
+ UINT8 InterruptPin;
+ UINT8 MinGnt;
+ UINT8 MaxLat;
+} PCI_DEVICE_HEADER_TYPE_REGION;
+
+typedef struct {
+ PCI_DEVICE_INDEPENDENT_REGION Hdr;
+ PCI_DEVICE_HEADER_TYPE_REGION Device;
+} PCI_TYPE00;
+
+typedef struct {
+ UINT32 Bar[2];
+ UINT8 PrimaryBus;
+ UINT8 SecondaryBus;
+ UINT8 SubordinateBus;
+ UINT8 SecondaryLatencyTimer;
+ UINT8 IoBase;
+ UINT8 IoLimit;
+ UINT16 SecondaryStatus;
+ UINT16 MemoryBase;
+ UINT16 MemoryLimit;
+ UINT16 PrefetchableMemoryBase;
+ UINT16 PrefetchableMemoryLimit;
+ UINT32 PrefetchableBaseUpper32;
+ UINT32 PrefetchableLimitUpper32;
+ UINT16 IoBaseUpper16;
+ UINT16 IoLimitUpper16;
+ UINT8 CapabilityPtr;
+ UINT8 Reserved[3];
+ UINT32 ExpansionRomBAR;
+ UINT8 InterruptLine;
+ UINT8 InterruptPin;
+ UINT16 BridgeControl;
+} PCI_BRIDGE_CONTROL_REGISTER;
+
+typedef struct {
+ PCI_DEVICE_INDEPENDENT_REGION Hdr;
+ PCI_BRIDGE_CONTROL_REGISTER Bridge;
+} PCI_TYPE01;
+
+typedef union {
+ PCI_TYPE00 Device;
+ PCI_TYPE01 Bridge;
+} PCI_TYPE_GENERIC;
+
+typedef struct {
+ UINT32 CardBusSocketReg; // Cardus Socket/ExCA Base
+ // Address Register
+ //
+ UINT16 Reserved;
+ UINT16 SecondaryStatus; // Secondary Status
+ UINT8 PciBusNumber; // PCI Bus Number
+ UINT8 CardBusBusNumber; // CardBus Bus Number
+ UINT8 SubordinateBusNumber; // Subordinate Bus Number
+ UINT8 CardBusLatencyTimer; // CardBus Latency Timer
+ UINT32 MemoryBase0; // Memory Base Register 0
+ UINT32 MemoryLimit0; // Memory Limit Register 0
+ UINT32 MemoryBase1;
+ UINT32 MemoryLimit1;
+ UINT32 IoBase0;
+ UINT32 IoLimit0; // I/O Base Register 0
+ UINT32 IoBase1; // I/O Limit Register 0
+ UINT32 IoLimit1;
+ UINT8 InterruptLine; // Interrupt Line
+ UINT8 InterruptPin; // Interrupt Pin
+ UINT16 BridgeControl; // Bridge Control
+} PCI_CARDBUS_CONTROL_REGISTER;
+
+//
+// Definitions of PCI class bytes and manipulation macros.
+//
+#define PCI_CLASS_OLD 0x00
+#define PCI_CLASS_OLD_OTHER 0x00
+#define PCI_CLASS_OLD_VGA 0x01
+
+#define PCI_CLASS_MASS_STORAGE 0x01
+#define PCI_CLASS_MASS_STORAGE_SCSI 0x00
+#define PCI_CLASS_MASS_STORAGE_IDE 0x01 // obsolete
+#define PCI_CLASS_IDE 0x01
+#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
+#define PCI_CLASS_MASS_STORAGE_IPI 0x03
+#define PCI_CLASS_MASS_STORAGE_RAID 0x04
+#define PCI_CLASS_MASS_STORAGE_OTHER 0x80
+
+#define PCI_CLASS_NETWORK 0x02
+#define PCI_CLASS_NETWORK_ETHERNET 0x00
+#define PCI_CLASS_ETHERNET 0x00 // obsolete
+#define PCI_CLASS_NETWORK_TOKENRING 0x01
+#define PCI_CLASS_NETWORK_FDDI 0x02
+#define PCI_CLASS_NETWORK_ATM 0x03
+#define PCI_CLASS_NETWORK_ISDN 0x04
+#define PCI_CLASS_NETWORK_OTHER 0x80
+
+#define PCI_CLASS_DISPLAY 0x03
+#define PCI_CLASS_DISPLAY_CTRL 0x03 // obsolete
+#define PCI_CLASS_DISPLAY_VGA 0x00
+#define PCI_CLASS_VGA 0x00 // obsolete
+#define PCI_CLASS_DISPLAY_XGA 0x01
+#define PCI_CLASS_DISPLAY_3D 0x02
+#define PCI_CLASS_DISPLAY_OTHER 0x80
+#define PCI_CLASS_DISPLAY_GFX 0x80
+#define PCI_CLASS_GFX 0x80 // obsolete
+
+#define PCI_CLASS_BRIDGE 0x06
+#define PCI_CLASS_BRIDGE_HOST 0x00
+#define PCI_CLASS_BRIDGE_ISA 0x01
+#define PCI_CLASS_ISA 0x01 // obsolete
+#define PCI_CLASS_BRIDGE_EISA 0x02
+#define PCI_CLASS_BRIDGE_MCA 0x03
+#define PCI_CLASS_BRIDGE_P2P 0x04
+#define PCI_CLASS_BRIDGE_PCMCIA 0x05
+#define PCI_CLASS_BRIDGE_NUBUS 0x06
+#define PCI_CLASS_BRIDGE_CARDBUS 0x07
+#define PCI_CLASS_BRIDGE_RACEWAY 0x08
+#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
+#define PCI_CLASS_ISA_POSITIVE_DECODE 0x80 // obsolete
+
+#define PCI_CLASS_SCC 0x07 // Simple communications controllers
+#define PCI_SUBCLASS_SERIAL 0x00
+#define PCI_IF_GENERIC_XT 0x00
+#define PCI_IF_16450 0x01
+#define PCI_IF_16550 0x02
+#define PCI_IF_16650 0x03
+#define PCI_IF_16750 0x04
+#define PCI_IF_16850 0x05
+#define PCI_IF_16950 0x06
+#define PCI_SUBCLASS_PARALLEL 0x01
+#define PCI_IF_PARALLEL_PORT 0x00
+#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
+#define PCI_IF_ECP_PARALLEL_PORT 0x02
+#define PCI_IF_1284_CONTROLLER 0x03
+#define PCI_IF_1284_DEVICE 0xFE
+#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
+#define PCI_SUBCLASS_MODEM 0x03
+#define PCI_IF_GENERIC_MODEM 0x00
+#define PCI_IF_16450_MODEM 0x01
+#define PCI_IF_16550_MODEM 0x02
+#define PCI_IF_16650_MODEM 0x03
+#define PCI_IF_16750_MODEM 0x04
+#define PCI_SUBCLASS_OTHER 0x80
+
+#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
+#define PCI_SUBCLASS_PIC 0x00
+#define PCI_IF_8259_PIC 0x00
+#define PCI_IF_ISA_PIC 0x01
+#define PCI_IF_EISA_PIC 0x02
+#define PCI_IF_APIC_CONTROLLER 0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory.
+#define PCI_IF_APIC_CONTROLLER2 0x20
+#define PCI_SUBCLASS_TIMER 0x02
+#define PCI_IF_8254_TIMER 0x00
+#define PCI_IF_ISA_TIMER 0x01
+#define PCI_EISA_TIMER 0x02
+#define PCI_SUBCLASS_RTC 0x03
+#define PCI_IF_GENERIC_RTC 0x00
+#define PCI_IF_ISA_RTC 0x00
+#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 // HotPlug Controller
+
+#define PCI_CLASS_INPUT_DEVICE 0x09
+#define PCI_SUBCLASS_KEYBOARD 0x00
+#define PCI_SUBCLASS_PEN 0x01
+#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
+#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
+#define PCI_SUBCLASS_GAMEPORT 0x04
+
+#define PCI_CLASS_DOCKING_STATION 0x0A
+
+#define PCI_CLASS_PROCESSOR 0x0B
+#define PCI_SUBCLASS_PROC_386 0x00
+#define PCI_SUBCLASS_PROC_486 0x01
+#define PCI_SUBCLASS_PROC_PENTIUM 0x02
+#define PCI_SUBCLASS_PROC_ALPHA 0x10
+#define PCI_SUBCLASS_PROC_POWERPC 0x20
+#define PCI_SUBCLASS_PROC_MIPS 0x30
+#define PCI_SUBCLASS_PROC_CO_PORC 0x40 // Co-Processor
+
+#define PCI_CLASS_SERIAL 0x0C
+#define PCI_CLASS_SERIAL_FIREWIRE 0x00
+#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
+#define PCI_CLASS_SERIAL_SSA 0x02
+#define PCI_CLASS_SERIAL_USB 0x03
+#define PCI_IF_EHCI 0x20
+#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
+#define PCI_CLASS_SERIAL_SMB 0x05
+
+#define PCI_CLASS_WIRELESS 0x0D
+#define PCI_SUBCLASS_IRDA 0x00
+#define PCI_SUBCLASS_IR 0x01
+#define PCI_SUBCLASS_RF 0x02
+
+#define PCI_CLASS_INTELLIGENT_IO 0x0E
+
+#define PCI_CLASS_SATELLITE 0x0F
+#define PCI_SUBCLASS_TV 0x01
+#define PCI_SUBCLASS_AUDIO 0x02
+#define PCI_SUBCLASS_VOICE 0x03
+#define PCI_SUBCLASS_DATA 0x04
+
+#define PCI_SECURITY_CONTROLLER 0x10 // Encryption and decryption controller
+#define PCI_SUBCLASS_NET_COMPUT 0x00
+#define PCI_SUBCLASS_ENTERTAINMENT 0x10
+
+#define PCI_CLASS_DPIO 0x11
+
+#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
+#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
+#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
+
+#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
+#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)
+#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)
+#define IS_PCI_GFX(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)
+#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
+#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
+#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
+#define IS_PCI_SCSI(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)
+#define IS_PCI_RAID(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)
+#define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)
+#define IS_PCI_ISA_PDECODE(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE, 0)
+#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)
+#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)
+#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
+#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
+
+#define HEADER_TYPE_DEVICE 0x00
+#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
+#define HEADER_TYPE_CARDBUS_BRIDGE 0x02
+
+#define HEADER_TYPE_MULTI_FUNCTION 0x80
+#define HEADER_LAYOUT_CODE 0x7f
+
+#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
+#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
+#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
+
+#define PCI_DEVICE_ROMBAR 0x30
+#define PCI_BRIDGE_ROMBAR 0x38
+
+#define PCI_MAX_BAR 0x0006
+#define PCI_MAX_CONFIG_OFFSET 0x0100
+
+#define PCI_VENDOR_ID_OFFSET 0x00
+#define PCI_DEVICE_ID_OFFSET 0x02
+#define PCI_COMMAND_OFFSET 0x04
+#define PCI_PRIMARY_STATUS_OFFSET 0x06
+#define PCI_REVISION_ID_OFFSET 0x08
+#define PCI_CLASSCODE_OFFSET 0x09
+#define PCI_SUBCLASSCODE_OFFSET 0x0A
+#define PCI_CACHELINE_SIZE_OFFSET 0x0C
+#define PCI_LATENCY_TIMER_OFFSET 0x0D
+#define PCI_HEADER_TYPE_OFFSET 0x0E
+#define PCI_BIST_OFFSET 0x0F
+#define PCI_BASE_ADDRESSREG_OFFSET 0x10
+#define PCI_CARDBUS_CIS_OFFSET 0x28
+#define PCI_SVID_OFFSET 0x2C // SubSystem Vendor id
+#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
+#define PCI_SID_OFFSET 0x2E // SubSystem ID
+#define PCI_SUBSYSTEM_ID_OFFSET 0x2E
+#define PCI_EXPANSION_ROM_BASE 0x30
+#define PCI_CAPBILITY_POINTER_OFFSET 0x34
+#define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line Register
+#define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin Register
+#define PCI_MAXGNT_OFFSET 0x3E // Max Grant Register
+#define PCI_MAXLAT_OFFSET 0x3F // Max Latency Register
+
+#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
+#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
+
+#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
+#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
+#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
+
+//
+// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
+//
+#define PCI_INT_LINE_UNKNOWN 0xFF
+
+
+typedef struct {
+ UINT32 Reg : 8;
+ UINT32 Func : 3;
+ UINT32 Dev : 5;
+ UINT32 Bus : 8;
+ UINT32 Reserved : 7;
+ UINT32 Enable : 1;
+} PCI_CONFIG_ACCESS_CF8;
+
+#pragma pack()
+
+#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
+#define PCI_DATA_STRUCTURE_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'I', 'R')
+#define PCI_CODE_TYPE_PCAT_IMAGE 0x00
+#define PCI_CODE_TYPE_EFI_IMAGE 0x03
+#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001
+
+#define EFI_PCI_COMMAND_IO_SPACE 0x0001
+#define EFI_PCI_COMMAND_MEMORY_SPACE 0x0002
+#define EFI_PCI_COMMAND_BUS_MASTER 0x0004
+#define EFI_PCI_COMMAND_SPECIAL_CYCLE 0x0008
+#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE 0x0010
+#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP 0x0020
+#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND 0x0040
+#define EFI_PCI_COMMAND_STEPPING_CONTROL 0x0080
+#define EFI_PCI_COMMAND_SERR 0x0100
+#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK 0x0200
+
+#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE 0x0001
+#define EFI_PCI_BRIDGE_CONTROL_SERR 0x0002
+#define EFI_PCI_BRIDGE_CONTROL_ISA 0x0004
+#define EFI_PCI_BRIDGE_CONTROL_VGA 0x0008
+#define EFI_PCI_BRIDGE_CONTROL_VGA_16 0x0010
+#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT 0x0020
+#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS 0x0040
+#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK 0x0080
+#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER 0x0100
+#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER 0x0200
+#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS 0x0400
+#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR 0x0800
+
+//
+// Following are the PCI-CARDBUS bridge control bit
+//
+#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE 0x0080
+#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE 0x0100
+#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE 0x0200
+#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400
+
+//
+// Following are the PCI status control bit
+//
+#define EFI_PCI_STATUS_CAPABILITY 0x0010
+#define EFI_PCI_STATUS_66MZ_CAPABLE 0x0020
+#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE 0x0080
+#define EFI_PCI_MASTER_DATA_PARITY_ERROR 0x0100
+
+#define EFI_PCI_CAPABILITY_PTR 0x34
+#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
+
+#pragma pack(1)
+typedef struct {
+ UINT16 Signature; // 0xaa55
+ UINT8 Reserved[0x16];
+ UINT16 PcirOffset;
+} PCI_EXPANSION_ROM_HEADER;
+
+typedef struct {
+ UINT16 Signature; // 0xaa55
+ UINT8 Size512;
+ UINT8 InitEntryPoint[3];
+ UINT8 Reserved[0x12];
+ UINT16 PcirOffset;
+} EFI_LEGACY_EXPANSION_ROM_HEADER;
+
+typedef struct {
+ UINT32 Signature; // "PCIR"
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT16 Reserved0;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT8 ClassCode[3];
+ UINT16 ImageLength;
+ UINT16 CodeRevision;
+ UINT8 CodeType;
+ UINT8 Indicator;
+ UINT16 Reserved1;
+} PCI_DATA_STRUCTURE;
+
+//
+// PCI Capability List IDs and records
+//
+#define EFI_PCI_CAPABILITY_ID_PMI 0x01
+#define EFI_PCI_CAPABILITY_ID_AGP 0x02
+#define EFI_PCI_CAPABILITY_ID_VPD 0x03
+#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
+#define EFI_PCI_CAPABILITY_ID_MSI 0x05
+#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
+#define EFI_PCI_CAPABILITY_ID_PCIX 0x07
+
+typedef struct {
+ UINT8 CapabilityID;
+ UINT8 NextItemPtr;
+} EFI_PCI_CAPABILITY_HDR;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_PMI
+//
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 PMC;
+ UINT16 PMCSR;
+ UINT8 BridgeExtention;
+ UINT8 Data;
+} EFI_PCI_CAPABILITY_PMI;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_AGP
+//
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT8 Rev;
+ UINT8 Reserved;
+ UINT32 Status;
+ UINT32 Command;
+} EFI_PCI_CAPABILITY_AGP;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_VPD
+//
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 AddrReg;
+ UINT32 DataReg;
+} EFI_PCI_CAPABILITY_VPD;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_SLOTID
+//
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT8 ExpnsSlotReg;
+ UINT8 ChassisNo;
+} EFI_PCI_CAPABILITY_SLOTID;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_MSI
+//
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 MsgCtrlReg;
+ UINT32 MsgAddrReg;
+ UINT16 MsgDataReg;
+} EFI_PCI_CAPABILITY_MSI32;
+
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 MsgCtrlReg;
+ UINT32 MsgAddrRegLsdw;
+ UINT32 MsgAddrRegMsdw;
+ UINT16 MsgDataReg;
+} EFI_PCI_CAPABILITY_MSI64;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG
+//
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ //
+ // not finished - fields need to go here
+ //
+} EFI_PCI_CAPABILITY_HOTPLUG;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_PCIX
+//
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 CommandReg;
+ UINT32 StatusReg;
+} EFI_PCI_CAPABILITY_PCIX;
+
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 SecStatusReg;
+ UINT32 StatusReg;
+ UINT32 SplitTransCtrlRegUp;
+ UINT32 SplitTransCtrlRegDn;
+} EFI_PCI_CAPABILITY_PCIX_BRDG;
+
+#define DEVICE_ID_NOCARE 0xFFFF
+
+#define PCI_ACPI_UNUSED 0
+#define PCI_BAR_NOCHANGE 0
+#define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFF
+#define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFE
+#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFD
+#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFC
+
+#define PCI_BAR_IDX0 0x00
+#define PCI_BAR_IDX1 0x01
+#define PCI_BAR_IDX2 0x02
+#define PCI_BAR_IDX3 0x03
+#define PCI_BAR_IDX4 0x04
+#define PCI_BAR_IDX5 0x05
+#define PCI_BAR_ALL 0xFF
+
+#pragma pack(pop)
+
+//
+// NOTE: The following header files are included here for
+// compatibility consideration.
+//
+#include "EfiPci.h"
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci23.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci23.h new file mode 100644 index 0000000000..c42991f38c --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci23.h @@ -0,0 +1,31 @@ +/*++
+
+Copyright (c) 2006 - 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ pci23.h
+
+Abstract:
+ Support for PCI 2.3 standard.
+
+Revision History
+
+--*/
+
+#ifndef _PCI23_H
+#define _PCI23_H
+
+#include "pci22.h"
+
+#define PCI_EXP_MAX_CONFIG_OFFSET 0x1000
+#define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci30.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci30.h new file mode 100644 index 0000000000..1a9219b377 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci30.h @@ -0,0 +1,52 @@ +/*++
+
+Copyright (c) 2006 - 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ pci30.h
+
+Abstract:
+ Support for PCI 3.0 standard.
+
+Revision History
+
+--*/
+
+#ifndef _PCI30_H
+#define _PCI30_H
+
+#include "pci23.h"
+
+#define PCI_CLASS_MASS_STORAGE_SATADPA 0x06
+#define PCI_CLASS_MASS_STORAGE_AHCI PCI_CLASS_MASS_STORAGE_SATADPA
+
+#pragma pack(push, 1)
+
+typedef struct {
+ UINT32 Signature; // "PCIR"
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT16 DeviceListOffset;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT8 ClassCode[3];
+ UINT16 ImageLength;
+ UINT16 CodeRevision;
+ UINT8 CodeType;
+ UINT8 Indicator;
+ UINT16 MaxRuntimeImageLength;
+ UINT16 ConfigUtilityCodeHeaderOffset;
+ UINT16 DMTFCLPEntryPointOffset;
+} PCI_3_0_DATA_STRUCTURE;
+
+#pragma pack(pop)
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/scsi.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/scsi.h new file mode 100644 index 0000000000..70a6b23833 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/scsi.h @@ -0,0 +1,292 @@ +/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ scsi.h
+
+Abstract:
+ support for SCSI standard
+
+Revision History
+--*/
+
+#ifndef _SCSI_H
+#define _SCSI_H
+
+//
+// SCSI command OP Code
+//
+//
+// Commands for all device types
+//
+#define EFI_SCSI_OP_CHANGE_DEFINITION 0x40
+#define EFI_SCSI_OP_COMPARE 0x39
+#define EFI_SCSI_OP_COPY 0x18
+#define EFI_SCSI_OP_COPY_VERIFY 0x3a
+#define EFI_SCSI_OP_INQUIRY 0x12
+#define EFI_SCSI_OP_LOG_SELECT 0x4c
+#define EFI_SCSI_OP_LOG_SENSE 0x4d
+#define EFI_SCSI_OP_MODE_SEL6 0x15
+#define EFI_SCSI_OP_MODE_SEL10 0x55
+#define EFI_SCSI_OP_MODE_SEN6 0x1a
+#define EFI_SCSI_OP_MODE_SEN10 0x5a
+#define EFI_SCSI_OP_READ_BUFFER 0x3c
+#define EFI_SCSI_OP_REQUEST_SENSE 0x03
+#define EFI_SCSI_OP_SEND_DIAG 0x1d
+#define EFI_SCSI_OP_TEST_UNIT_READY 0x00
+#define EFI_SCSI_OP_WRITE_BUFF 0x3b
+
+//
+// Commands unique to Direct Access Devices
+//
+#define EFI_SCSI_OP_COMPARE 0x39
+#define EFI_SCSI_OP_FORMAT 0x04
+#define EFI_SCSI_OP_LOCK_UN_CACHE 0x36
+#define EFI_SCSI_OP_PREFETCH 0x34
+#define EFI_SCSI_OP_MEDIA_REMOVAL 0x1e
+#define EFI_SCSI_OP_READ6 0x08
+#define EFI_SCSI_OP_READ10 0x28
+#define EFI_SCSI_OP_READ_CAPACITY 0x25
+#define EFI_SCSI_OP_READ_DEFECT 0x37
+#define EFI_SCSI_OP_READ_LONG 0x3e
+#define EFI_SCSI_OP_REASSIGN_BLK 0x07
+#define EFI_SCSI_OP_RECEIVE_DIAG 0x1c
+#define EFI_SCSI_OP_RELEASE 0x17
+#define EFI_SCSI_OP_REZERO 0x01
+#define EFI_SCSI_OP_SEARCH_DATA_E 0x31
+#define EFI_SCSI_OP_SEARCH_DATA_H 0x30
+#define EFI_SCSI_OP_SEARCH_DATA_L 0x32
+#define EFI_SCSI_OP_SEEK6 0x0b
+#define EFI_SCSI_OP_SEEK10 0x2b
+#define EFI_SCSI_OP_SEND_DIAG 0x1d
+#define EFI_SCSI_OP_SET_LIMIT 0x33
+#define EFI_SCSI_OP_START_STOP_UNIT 0x1b
+#define EFI_SCSI_OP_SYNC_CACHE 0x35
+#define EFI_SCSI_OP_VERIFY 0x2f
+#define EFI_SCSI_OP_WRITE6 0x0a
+#define EFI_SCSI_OP_WRITE10 0x2a
+#define EFI_SCSI_OP_WRITE_VERIFY 0x2e
+#define EFI_SCSI_OP_WRITE_LONG 0x3f
+#define EFI_SCSI_OP_WRITE_SAME 0x41
+
+//
+// Commands unique to Sequential Access Devices
+//
+#define EFI_SCSI_OP_ERASE 0x19
+#define EFI_SCSI_OP_LOAD_UNLOAD 0x1b
+#define EFI_SCSI_OP_LOCATE 0x2b
+#define EFI_SCSI_OP_READ_BLOCK_LIMIT 0x05
+#define EFI_SCSI_OP_READ_POS 0x34
+#define EFI_SCSI_OP_READ_REVERSE 0x0f
+#define EFI_SCSI_OP_RECOVER_BUF_DATA 0x14
+#define EFI_SCSI_OP_RESERVE_UNIT 0x16
+#define EFI_SCSI_OP_REWIND 0x01
+#define EFI_SCSI_OP_SPACE 0x11
+#define EFI_SCSI_OP_VERIFY_TAPE 0x13
+#define EFI_SCSI_OP_WRITE_FILEMARK 0x10
+
+//
+// Commands unique to Printer Devices
+//
+#define EFI_SCSI_OP_PRINT 0x0a
+#define EFI_SCSI_OP_SLEW_PRINT 0x0b
+#define EFI_SCSI_OP_STOP_PRINT 0x1b
+#define EFI_SCSI_OP_SYNC_BUFF 0x10
+
+//
+// Commands unique to Processor Devices
+//
+#define EFI_SCSI_OP_RECEIVE 0x08
+#define EFI_SCSI_OP_SEND 0x0a
+
+//
+// Commands unique to Write-Once Devices
+//
+#define EFI_SCSI_OP_MEDIUM_SCAN 0x38
+#define EFI_SCSI_OP_SEARCH_DAT_E10 0x31
+#define EFI_SCSI_OP_SEARCH_DAT_E12 0xb1
+#define EFI_SCSI_OP_SEARCH_DAT_H10 0x30
+#define EFI_SCSI_OP_SEARCH_DAT_H12 0xb0
+#define EFI_SCSI_OP_SEARCH_DAT_L10 0x32
+#define EFI_SCSI_OP_SEARCH_DAT_L12 0xb2
+#define EFI_SCSI_OP_SET_LIMIT10 0x33
+#define EFI_SCSI_OP_SET_LIMIT12 0xb3
+#define EFI_SCSI_OP_VERIFY10 0x2f
+#define EFI_SCSI_OP_VERIFY12 0xaf
+#define EFI_SCSI_OP_WRITE12 0xaa
+#define EFI_SCSI_OP_WRITE_VERIFY10 0x2e
+#define EFI_SCSI_OP_WRITE_VERIFY12 0xae
+
+//
+// Commands unique to CD-ROM Devices
+//
+#define EFI_SCSI_OP_PLAY_AUD_10 0x45
+#define EFI_SCSI_OP_PLAY_AUD_12 0xa5
+#define EFI_SCSI_OP_PLAY_AUD_MSF 0x47
+#define EFI_SCSI_OP_PLAY_AUD_TKIN 0x48
+#define EFI_SCSI_OP_PLAY_TK_REL10 0x49
+#define EFI_SCSI_OP_PLAY_TK_REL12 0xa9
+#define EFI_SCSI_OP_READ_CD_CAPACITY 0x25
+#define EFI_SCSI_OP_READ_HEADER 0x44
+#define EFI_SCSI_OP_READ_SUB_CHANNEL 0x42
+#define EFI_SCSI_OP_READ_TOC 0x43
+
+//
+// Commands unique to Scanner Devices
+//
+#define EFI_SCSI_OP_GET_DATABUFF_STAT 0x34
+#define EFI_SCSI_OP_GET_WINDOW 0x25
+#define EFI_SCSI_OP_OBJECT_POS 0x31
+#define EFI_SCSI_OP_SCAN 0x1b
+#define EFI_SCSI_OP_SET_WINDOW 0x24
+
+//
+// Commands unique to Optical Memory Devices
+//
+#define EFI_SCSI_OP_UPDATE_BLOCK 0x3d
+
+//
+// Commands unique to Medium Changer Devices
+//
+#define EFI_SCSI_OP_EXCHANGE_MEDIUM 0xa6
+#define EFI_SCSI_OP_INIT_ELEMENT_STAT 0x07
+#define EFI_SCSI_OP_POS_TO_ELEMENT 0x2b
+#define EFI_SCSI_OP_REQUEST_VE_ADDR 0xb5
+#define EFI_SCSI_OP_SEND_VOL_TAG 0xb6
+
+//
+// Commands unique to Communition Devices
+//
+#define EFI_SCSI_OP_GET_MESSAGE6 0x08
+#define EFI_SCSI_OP_GET_MESSAGE10 0x28
+#define EFI_SCSI_OP_GET_MESSAGE12 0xa8
+#define EFI_SCSI_OP_SEND_MESSAGE6 0x0a
+#define EFI_SCSI_OP_SEND_MESSAGE10 0x2a
+#define EFI_SCSI_OP_SEND_MESSAGE12 0xaa
+
+//
+// SCSI Data Transfer Direction
+//
+#define EFI_SCSI_DATA_IN 0
+#define EFI_SCSI_DATA_OUT 1
+
+//
+// Peripheral Device Type Definitions
+//
+#define EFI_SCSI_TYPE_DISK 0x00 // Disk device
+#define EFI_SCSI_TYPE_TAPE 0x01 // Tape device
+#define EFI_SCSI_TYPE_PRINTER 0x02 // Printer
+#define EFI_SCSI_TYPE_PROCESSOR 0x03 // Processor
+#define EFI_SCSI_TYPE_WORM 0x04 // Write-once read-multiple
+#define EFI_SCSI_TYPE_CDROM 0x05 // CD-ROM device
+#define EFI_SCSI_TYPE_SCANNER 0x06 // Scanner device
+#define EFI_SCSI_TYPE_OPTICAL 0x07 // Optical memory device
+#define EFI_SCSI_TYPE_MEDIUMCHANGER 0x08 // Medium Changer device
+#define EFI_SCSI_TYPE_COMMUNICATION 0x09 // Communications device
+#define EFI_SCSI_TYPE_RESERVED_LOW 0x0A // Reserved (low)
+#define EFI_SCSI_TYPE_RESERVED_HIGH 0x1E // Reserved (high)
+#define EFI_SCSI_TYPE_UNKNOWN 0x1F // Unknown or no device type
+#pragma pack(1)
+//
+// Data structures for scsi command use
+//
+typedef struct {
+ UINT8 Peripheral_Type : 5;
+ UINT8 Peripheral_Qualifier : 3;
+ UINT8 DeviceType_Modifier : 7;
+ UINT8 RMB : 1;
+ UINT8 Version;
+ UINT8 Response_Data_Format;
+ UINT8 Addnl_Length;
+ UINT8 Reserved_5_95[95 - 5 + 1];
+} EFI_SCSI_INQUIRY_DATA;
+
+typedef struct {
+ UINT8 Error_Code : 7;
+ UINT8 Valid : 1;
+ UINT8 Segment_Number;
+ UINT8 Sense_Key : 4;
+ UINT8 Reserved_21 : 1;
+ UINT8 ILI : 1;
+ UINT8 Reserved_22 : 2;
+ UINT8 Information_3_6[4];
+ UINT8 Addnl_Sense_Length; // n - 7
+ UINT8 Vendor_Specific_8_11[4];
+ UINT8 Addnl_Sense_Code; // mandatory
+ UINT8 Addnl_Sense_Code_Qualifier; // mandatory
+ UINT8 Field_Replaceable_Unit_Code; // optional
+ UINT8 Reserved_15_17[3];
+} EFI_SCSI_SENSE_DATA;
+
+typedef struct {
+ UINT8 LastLba3;
+ UINT8 LastLba2;
+ UINT8 LastLba1;
+ UINT8 LastLba0;
+ UINT8 BlockSize3;
+ UINT8 BlockSize2;
+ UINT8 BlockSize1;
+ UINT8 BlockSize0;
+} EFI_SCSI_DISK_CAPACITY_DATA;
+
+#pragma pack()
+//
+// Sense Key
+//
+#define EFI_SCSI_REQUEST_SENSE_ERROR (0x70)
+#define EFI_SCSI_SK_NO_SENSE (0x0)
+#define EFI_SCSI_SK_RECOVERY_ERROR (0x1)
+#define EFI_SCSI_SK_NOT_READY (0x2)
+#define EFI_SCSI_SK_MEDIUM_ERROR (0x3)
+#define EFI_SCSI_SK_HARDWARE_ERROR (0x4)
+#define EFI_SCSI_SK_ILLEGAL_REQUEST (0x5)
+#define EFI_SCSI_SK_UNIT_ATTENTION (0x6)
+#define EFI_SCSI_SK_DATA_PROTECT (0x7)
+#define EFI_SCSI_SK_BLANK_CHECK (0x8)
+#define EFI_SCSI_SK_VENDOR_SPECIFIC (0x9)
+#define EFI_SCSI_SK_RESERVED_A (0xA)
+#define EFI_SCSI_SK_ABORT (0xB)
+#define EFI_SCSI_SK_RESERVED_C (0xC)
+#define EFI_SCSI_SK_OVERFLOW (0xD)
+#define EFI_SCSI_SK_MISCOMPARE (0xE)
+#define EFI_SCSI_SK_RESERVED_F (0xF)
+
+//
+// Additional Sense Codes
+//
+#define EFI_SCSI_ASC_NOT_READY (0x04)
+#define EFI_SCSI_ASC_MEDIA_ERR1 (0x10)
+#define EFI_SCSI_ASC_MEDIA_ERR2 (0x11)
+#define EFI_SCSI_ASC_MEDIA_ERR3 (0x14)
+#define EFI_SCSI_ASC_MEDIA_ERR4 (0x30)
+#define EFI_SCSI_ASC_MEDIA_UPSIDE_DOWN (0x06)
+#define EFI_SCSI_ASC_INVALID_CMD (0x20)
+#define EFI_SCSI_ASC_LBA_OUT_OF_RANGE (0x21)
+#define EFI_SCSI_ASC_INVALID_FIELD (0x24)
+#define EFI_SCSI_ASC_WRITE_PROTECTED (0x27)
+#define EFI_SCSI_ASC_MEDIA_CHANGE (0x28)
+#define EFI_SCSI_ASC_RESET (0x29) /* Power On Reset or Bus Reset occurred */
+#define EFI_SCSI_ASC_ILLEGAL_FIELD (0x26)
+#define EFI_SCSI_ASC_NO_MEDIA (0x3A)
+#define EFI_SCSI_ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
+
+//
+// Additional Sense Code Qualifier
+//
+#define EFI_SCSI_ASCQ_IN_PROGRESS (0x01)
+
+//
+// Max bytes needed to represent ID of a SCSI device
+//
+#define EFI_SCSI_TARGET_MAX_BYTES (0x10)
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/usb.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/usb.h new file mode 100644 index 0000000000..8ccfd11ea8 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/usb.h @@ -0,0 +1,293 @@ +/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ usb.h
+
+Abstract:
+ Support for USB 1.1 standard.
+
+
+
+
+Revision History
+
+--*/
+
+#ifndef _USB_H
+#define _USB_H
+//
+// USB Descriptor types
+//
+#define USB_DT_DEVICE 0x01
+#define USB_DT_CONFIG 0x02
+#define USB_DT_STRING 0x03
+#define USB_DT_INTERFACE 0x04
+#define USB_DT_ENDPOINT 0x05
+#define USB_DT_HUB 0x29
+#define USB_DT_HID 0x21
+
+//
+// USB request type
+//
+#define USB_TYPE_STANDARD (0x00 << 5)
+#define USB_TYPE_CLASS (0x01 << 5)
+#define USB_TYPE_VENDOR (0x02 << 5)
+#define USB_TYPE_RESERVED (0x03 << 5)
+
+//
+// USB request targer device
+//
+#define USB_RECIP_DEVICE 0x00
+#define USB_RECIP_INTERFACE 0x01
+#define USB_RECIP_ENDPOINT 0x02
+#define USB_RECIP_OTHER 0x03
+
+//
+// Request target types.
+//
+#define USB_RT_DEVICE 0x00
+#define USB_RT_INTERFACE 0x01
+#define USB_RT_ENDPOINT 0x02
+#define USB_RT_HUB (USB_TYPE_CLASS | USB_RECIP_DEVICE)
+#define USB_RT_PORT (USB_TYPE_CLASS | USB_RECIP_OTHER)
+
+//
+// USB Transfer Results
+//
+#define EFI_USB_NOERROR 0x00
+#define EFI_USB_ERR_NOTEXECUTE 0x01
+#define EFI_USB_ERR_STALL 0x02
+#define EFI_USB_ERR_BUFFER 0x04
+#define EFI_USB_ERR_BABBLE 0x08
+#define EFI_USB_ERR_NAK 0x10
+#define EFI_USB_ERR_CRC 0x20
+#define EFI_USB_ERR_TIMEOUT 0x40
+#define EFI_USB_ERR_BITSTUFF 0x80
+#define EFI_USB_ERR_SYSTEM 0x100
+
+//
+//Use 200 ms to increase the error handling response time
+//
+#define EFI_USB_INTERRUPT_DELAY 2000000
+
+//
+// USB transation direction
+//
+typedef enum {
+ EfiUsbDataIn,
+ EfiUsbDataOut,
+ EfiUsbNoData
+} EFI_USB_DATA_DIRECTION;
+
+//
+// Usb Data recipient type
+//
+typedef enum {
+ EfiUsbDevice,
+ EfiUsbInterface,
+ EfiUsbEndpoint
+} EFI_USB_RECIPIENT;
+
+typedef enum {
+ EfiUsbEndpointHalt,
+ EfiUsbDeviceRemoteWakeup
+} EFI_USB_STANDARD_FEATURE_SELECTOR;
+
+#pragma pack(1)
+//
+// Usb device request structure
+//
+typedef struct {
+ UINT8 RequestType;
+ UINT8 Request;
+ UINT16 Value;
+ UINT16 Index;
+ UINT16 Length;
+} EFI_USB_DEVICE_REQUEST;
+
+//
+// Standard USB request
+//
+#define USB_DEV_GET_STATUS 0x00
+
+#define USB_DEV_CLEAR_FEATURE 0x01
+
+#define USB_DEV_SET_FEATURE 0x03
+
+#define USB_DEV_SET_ADDRESS 0x05
+#define USB_DEV_SET_ADDRESS_REQ_TYPE 0x00
+
+#define USB_DEV_GET_DESCRIPTOR 0x06
+#define USB_DEV_GET_DESCRIPTOR_REQ_TYPE 0x80
+
+#define USB_DEV_SET_DESCRIPTOR 0x07
+#define USB_DEV_SET_DESCRIPTOR_REQ_TYPE 0x00
+
+#define USB_DEV_GET_CONFIGURATION 0x08
+#define USB_DEV_GET_CONFIGURATION_REQ_TYPE 0x80
+
+#define USB_DEV_SET_CONFIGURATION 0x09
+#define USB_DEV_SET_CONFIGURATION_REQ_TYPE 0x00
+
+#define USB_DEV_GET_INTERFACE 0x0A
+#define USB_DEV_GET_INTERFACE_REQ_TYPE 0x81
+
+#define USB_DEV_SET_INTERFACE 0x0B
+#define USB_DEV_SET_INTERFACE_REQ_TYPE 0x01
+
+#define USB_DEV_SYNCH_FRAME 0x0C
+#define USB_DEV_SYNCH_FRAME_REQ_TYPE 0x82
+
+//
+// Device descriptor. refer USB1.1
+//
+typedef struct usb_device_descriptor {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT16 BcdUSB;
+ UINT8 DeviceClass;
+ UINT8 DeviceSubClass;
+ UINT8 DeviceProtocol;
+ UINT8 MaxPacketSize0;
+ UINT16 IdVendor;
+ UINT16 IdProduct;
+ UINT16 BcdDevice;
+ UINT8 StrManufacturer;
+ UINT8 StrProduct;
+ UINT8 StrSerialNumber;
+ UINT8 NumConfigurations;
+} EFI_USB_DEVICE_DESCRIPTOR;
+
+//
+// Endpoint descriptor
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT8 EndpointAddress;
+ UINT8 Attributes;
+ UINT16 MaxPacketSize;
+ UINT8 Interval;
+} EFI_USB_ENDPOINT_DESCRIPTOR;
+
+//
+// Interface descriptor
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT8 InterfaceNumber;
+ UINT8 AlternateSetting;
+ UINT8 NumEndpoints;
+ UINT8 InterfaceClass;
+ UINT8 InterfaceSubClass;
+ UINT8 InterfaceProtocol;
+ UINT8 Interface;
+} EFI_USB_INTERFACE_DESCRIPTOR;
+
+//
+// USB alternate setting
+//
+typedef struct {
+ EFI_USB_INTERFACE_DESCRIPTOR *Interface;
+} USB_ALT_SETTING;
+
+//
+// Configuration descriptor
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT16 TotalLength;
+ UINT8 NumInterfaces;
+ UINT8 ConfigurationValue;
+ UINT8 Configuration;
+ UINT8 Attributes;
+ UINT8 MaxPower;
+} EFI_USB_CONFIG_DESCRIPTOR;
+
+//
+// Supported String Languages
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT16 SupportedLanID[1];
+} EFI_USB_SUPPORTED_LANGUAGES;
+
+//
+// String descriptor
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ CHAR16 String[1];
+} EFI_USB_STRING_DESCRIPTOR;
+
+//
+// Hub descriptor
+//
+#define MAXBYTES 8
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT8 NbrPorts;
+ UINT8 HubCharacteristics[2];
+ UINT8 PwrOn2PwrGood;
+ UINT8 HubContrCurrent;
+ UINT8 Filler[MAXBYTES];
+} EFI_USB_HUB_DESCRIPTOR;
+
+typedef struct {
+ UINT16 PortStatus;
+ UINT16 PortChangeStatus;
+} EFI_USB_PORT_STATUS;
+
+//
+// Constant value for Port Status & Port Change Status
+//
+#define USB_PORT_STAT_CONNECTION 0x0001
+#define USB_PORT_STAT_ENABLE 0x0002
+#define USB_PORT_STAT_SUSPEND 0x0004
+#define USB_PORT_STAT_OVERCURRENT 0x0008
+#define USB_PORT_STAT_RESET 0x0010
+#define USB_PORT_STAT_POWER 0x0100
+#define USB_PORT_STAT_LOW_SPEED 0x0200
+#define USB_PORT_STAT_HIGH_SPEED 0x0400
+#define USB_PORT_STAT_OWNER 0x0800
+
+#define USB_PORT_STAT_C_CONNECTION 0x0001
+#define USB_PORT_STAT_C_ENABLE 0x0002
+#define USB_PORT_STAT_C_SUSPEND 0x0004
+#define USB_PORT_STAT_C_OVERCURRENT 0x0008
+#define USB_PORT_STAT_C_RESET 0x0010
+
+//
+// Used for set/clear port feature request
+//
+typedef enum {
+ EfiUsbPortEnable = 1,
+ EfiUsbPortSuspend = 2,
+ EfiUsbPortReset = 4,
+ EfiUsbPortPower = 8,
+ EfiUsbPortOwner = 13,
+ EfiUsbPortConnectChange = 16,
+ EfiUsbPortEnableChange = 17,
+ EfiUsbPortSuspendChange = 18,
+ EfiUsbPortOverCurrentChange = 19,
+ EfiUsbPortResetChange = 20
+} EFI_USB_PORT_FEATURE;
+
+#pragma pack()
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/Ipf/EfiBind.h b/EdkCompatibilityPkg/Foundation/Include/Ipf/EfiBind.h new file mode 100644 index 0000000000..cad7ca1de8 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/Ipf/EfiBind.h @@ -0,0 +1,247 @@ +/*++
+
+Copyright (c) 2004 - 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ EfiBind.h
+
+Abstract:
+
+ Processor or Compiler specific defines and types for Intel Itanium(TM).
+ We are using the ANSI C 2000 _t type definitions for basic types.
+ This it technically a violation of the coding standard, but they
+ are used to make EfiTypes.h portable. Code other than EfiTypes.h
+ should never use any ANSI C 2000 _t integer types.
+
+--*/
+
+#ifndef _EFI_BIND_H_
+#define _EFI_BIND_H_
+
+
+#define EFI_DRIVER_ENTRY_POINT(InitFunction)
+
+#define EFI_APPLICATION_ENTRY_POINT EFI_DRIVER_ENTRY_POINT
+
+
+
+
+//
+// Make sure we are useing the correct packing rules per EFI specification
+//
+#pragma pack()
+
+
+#if _MSC_EXTENSIONS
+
+//
+// Disable warning that make it impossible to compile at /W4
+// This only works for Microsoft tools. Copied from the
+// IA-32 version of efibind.h
+//
+
+//
+// Disabling bitfield type checking warnings.
+//
+#pragma warning ( disable : 4214 )
+
+
+// Disabling the unreferenced formal parameter warnings.
+//
+#pragma warning ( disable : 4100 )
+
+//
+// Disable slightly different base types warning as CHAR8 * can not be set
+// to a constant string.
+//
+#pragma warning ( disable : 4057 )
+
+//
+// ASSERT(FALSE) or while (TRUE) are legal constructes so supress this warning
+//
+#pragma warning ( disable : 4127 )
+
+//
+// Can not cast a function pointer to a data pointer. We need to do this on
+// IPF to get access to the PLABEL.
+//
+#pragma warning ( disable : 4514 )
+
+//
+// Int64ShllMod32 unreferenced inline function
+//
+#pragma warning ( disable : 4054 )
+
+//
+// Unreferenced formal parameter - We are object oriented, so we pass This even
+// if we don't need them.
+//
+#pragma warning ( disable : 4100 )
+
+//
+// This warning is caused by empty (after preprocessing) souce file.
+//
+#pragma warning ( disable : 4206 )
+
+//
+// Warning: The result of the unary '&' operator may be unaligned. Ignore it.
+//
+#pragma warning ( disable : 4366 )
+
+#endif
+
+
+#if (__STDC_VERSION__ < 199901L)
+ //
+ // No ANSI C 2000 stdint.h integer width declarations, so define equivalents
+ //
+
+ #if _MSC_EXTENSIONS
+
+
+ //
+ // use Microsoft C complier dependent interger width types
+ //
+ typedef unsigned __int64 uint64_t;
+ typedef __int64 int64_t;
+ typedef unsigned __int32 uint32_t;
+ typedef __int32 int32_t;
+ typedef unsigned short uint16_t;
+ typedef short int16_t;
+ typedef unsigned char uint8_t;
+ typedef char int8_t;
+ #else
+ #ifdef _EFI_P64
+ //
+ // P64 - is Intel Itanium(TM) speak for pointers being 64-bit and longs and ints
+ // are 32-bits
+ //
+ typedef unsigned long long uint64_t;
+ typedef long long int64_t;
+ typedef unsigned int uint32_t;
+ typedef int int32_t;
+ typedef unsigned short uint16_t;
+ typedef short int16_t;
+ typedef unsigned char uint8_t;
+ typedef char int8_t;
+ #else
+ //
+ // Assume LP64 - longs and pointers are 64-bit. Ints are 32-bit.
+ //
+ typedef unsigned long uint64_t;
+ typedef long int64_t;
+ typedef unsigned int uint32_t;
+ typedef int int32_t;
+ typedef unsigned short uint16_t;
+ typedef short int16_t;
+ typedef unsigned char uint8_t;
+ typedef char int8_t;
+ #endif
+ #endif
+#else
+ //
+ // Use ANSI C 2000 stdint.h integer width declarations
+ //
+ #include "stdint.h"
+#endif
+
+//
+// Native integer size in stdint.h
+//
+typedef uint64_t uintn_t;
+typedef int64_t intn_t;
+
+//
+// Processor specific defines
+//
+#define EFI_MAX_BIT 0x8000000000000000
+#define MAX_2_BITS 0xC000000000000000
+
+//
+// Maximum legal Itanium-based address
+//
+#define EFI_MAX_ADDRESS 0xFFFFFFFFFFFFFFFF
+
+//
+// Bad pointer value to use in check builds.
+// if you see this value you are using uninitialized or free'ed data
+//
+#define EFI_BAD_POINTER 0xAFAFAFAFAFAFAFAF
+#define EFI_BAD_POINTER_AS_BYTE 0xAF
+
+//
+// Inject a break point in the code to assist debugging.
+//
+#pragma intrinsic (__break)
+#define EFI_BREAKPOINT() __break(0)
+#define EFI_DEADLOOP() while(TRUE)
+
+//
+// Memory Fence forces serialization, and is needed to support out of order
+// memory transactions. The Memory Fence is mainly used to make sure IO
+// transactions complete in a deterministic sequence, and to syncronize locks
+// an other MP code. Intel Itanium(TM) processors require explicit memory fence instructions
+// after every IO. Need to find a way of doing that in the function _mf.
+//
+void __mfa (void);
+#pragma intrinsic (__mfa)
+#define MEMORY_FENCE() __mfa()
+
+
+//
+// Some compilers don't support the forward reference construct:
+// typedef struct XXXXX. The forward reference is required for
+// ANSI compatibility.
+//
+// The following macro provide a workaround for such cases.
+//
+
+
+#ifdef EFI_NO_INTERFACE_DECL
+ #define EFI_FORWARD_DECLARATION(x)
+#else
+ #define EFI_FORWARD_DECLARATION(x) typedef struct _##x x
+#endif
+
+//
+// Some C compilers optimize the calling conventions to increase performance.
+// _EFIAPI is used to make all public APIs follow the standard C calling
+// convention.
+//
+
+#if _MSC_EXTENSIONS
+ #define _EFIAPI __cdecl
+#else
+ #define _EFIAPI
+#endif
+
+
+#ifdef _EFI_WINNT
+
+ #define EFI_SUPPRESS_BENIGN_REDEFINITION_OF_TYPE_WARNING() \
+ warning ( disable : 4142 )
+
+ #define EFI_DEFAULT_BENIGN_REDEFINITION_OF_TYPE_WARNING() \
+ warning ( default : 4142 )
+#else
+
+ #define EFI_SUPPRESS_BENIGN_REDEFINITION_OF_TYPE_WARNING() \
+ warning ( disable : 4068 )
+
+ #define EFI_DEFAULT_BENIGN_REDEFINITION_OF_TYPE_WARNING() \
+ warning ( default : 4068 )
+
+
+#endif
+
+
+#endif
+
diff --git a/EdkCompatibilityPkg/Foundation/Include/Ipf/EfiPeOptionalHeader.h b/EdkCompatibilityPkg/Foundation/Include/Ipf/EfiPeOptionalHeader.h new file mode 100644 index 0000000000..53de8aaa7e --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/Ipf/EfiPeOptionalHeader.h @@ -0,0 +1,37 @@ +/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ EfiPeOptionalHeader.h
+
+Abstract:
+ Defines the optional header in the PE image per the PE specification. This
+ file must be included only from within EfiImage.h since
+ EFI_IMAGE_DATA_DIRECTORY and EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES are defined
+ there.
+
+--*/
+
+#ifndef _EFI_PE_OPTIONAL_HEADER_H_
+#define _EFI_PE_OPTIONAL_HEADER_H_
+
+#define EFI_IMAGE_MACHINE_TYPE (EFI_IMAGE_MACHINE_IA64)
+
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
+ (((Machine) == EFI_IMAGE_MACHINE_IA64) || ((Machine) == EFI_IMAGE_MACHINE_EBC))
+
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
+
+#define EFI_IMAGE_NT_OPTIONAL_HDR_MAGIC EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC
+typedef EFI_IMAGE_OPTIONAL_HEADER64 EFI_IMAGE_OPTIONAL_HEADER;
+typedef EFI_IMAGE_NT_HEADERS64 EFI_IMAGE_NT_HEADERS;
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/Ipf/IpfDefines.h b/EdkCompatibilityPkg/Foundation/Include/Ipf/IpfDefines.h new file mode 100644 index 0000000000..0fe1407525 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/Ipf/IpfDefines.h @@ -0,0 +1,556 @@ +// ++
+
+// TODO: fix comment to start with /*++
+//
+// Copyright (c) 2004, Intel Corporation
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Module Name:
+//
+// IpfDefines.h
+//
+// Abstract:
+//
+// IPF Processor Defines.
+// NOTE: This file is included by assembly files as well.
+//
+// --
+//
+#ifndef _IPFDEFINES_H
+#define _IPFDEFINES_H
+
+//
+// IPI DElivery Methods
+//
+#define IPI_INT_DELIVERY 0x0
+#define IPI_PMI_DELIVERY 0x2
+#define IPI_NMI_DELIVERY 0x4
+#define IPI_INIT_DELIVERY 0x5
+#define IPI_ExtINT_DELIVERY 0x7
+
+//
+// Define Itanium-based system registers.
+//
+// Define Itanium-based system register bit field offsets.
+//
+// Processor Status Register (PSR) Bit positions
+//
+// User / System mask
+//
+#define PSR_RV0 0
+#define PSR_BE 1
+#define PSR_UP 2
+#define PSR_AC 3
+#define PSR_MFL 4
+#define PSR_MFH 5
+
+//
+// PSR bits 6-12 reserved (must be zero)
+//
+#define PSR_MBZ0 6
+#define PSR_MBZ0_V 0x1ffUL L
+
+//
+// System only mask
+//
+#define PSR_IC 13
+#define PSR_IC_MASK (1 << 13)
+#define PSR_I 14
+#define PSR_PK 15
+#define PSR_MBZ1 16
+#define PSR_MBZ1_V 0x1UL L
+#define PSR_DT 17
+#define PSR_DFL 18
+#define PSR_DFH 19
+#define PSR_SP 20
+#define PSR_PP 21
+#define PSR_DI 22
+#define PSR_SI 23
+#define PSR_DB 24
+#define PSR_LP 25
+#define PSR_TB 26
+#define PSR_RT 27
+
+//
+// PSR bits 28-31 reserved (must be zero)
+//
+#define PSR_MBZ2 28
+#define PSR_MBZ2_V 0xfUL L
+
+//
+// Neither mask
+//
+#define PSR_CPL 32
+#define PSR_CPL_LEN 2
+#define PSR_IS 34
+#define PSR_MC 35
+#define PSR_IT 36
+#define PSR_IT_MASK 0x1000000000
+#define PSR_ID 37
+#define PSR_DA 38
+#define PSR_DD 39
+#define PSR_SS 40
+#define PSR_RI 41
+#define PSR_RI_LEN 2
+#define PSR_ED 43
+#define PSR_BN 44
+
+//
+// PSR bits 45-63 reserved (must be zero)
+//
+#define PSR_MBZ3 45
+#define PSR_MBZ3_V 0xfffffUL L
+
+//
+// Floating Point Status Register (FPSR) Bit positions
+//
+//
+// Traps
+//
+#define FPSR_VD 0
+#define FPSR_DD 1
+#define FPSR_ZD 2
+#define FPSR_OD 3
+#define FPSR_UD 4
+#define FPSR_ID 5
+
+//
+// Status Field 0 - Controls
+//
+#define FPSR0_FTZ0 6
+#define FPSR0_WRE0 7
+#define FPSR0_PC0 8
+#define FPSR0_RC0 10
+#define FPSR0_TD0 12
+
+//
+// Status Field 0 - Flags
+//
+#define FPSR0_V0 13
+#define FPSR0_D0 14
+#define FPSR0_Z0 15
+#define FPSR0_O0 16
+#define FPSR0_U0 17
+#define FPSR0_I0 18
+
+//
+// Status Field 1 - Controls
+//
+#define FPSR1_FTZ0 19
+#define FPSR1_WRE0 20
+#define FPSR1_PC0 21
+#define FPSR1_RC0 23
+#define FPSR1_TD0 25
+
+//
+// Status Field 1 - Flags
+//
+#define FPSR1_V0 26
+#define FPSR1_D0 27
+#define FPSR1_Z0 28
+#define FPSR1_O0 29
+#define FPSR1_U0 30
+#define FPSR1_I0 31
+
+//
+// Status Field 2 - Controls
+//
+#define FPSR2_FTZ0 32
+#define FPSR2_WRE0 33
+#define FPSR2_PC0 34
+#define FPSR2_RC0 36
+#define FPSR2_TD0 38
+
+//
+// Status Field 2 - Flags
+//
+#define FPSR2_V0 39
+#define FPSR2_D0 40
+#define FPSR2_Z0 41
+#define FPSR2_O0 42
+#define FPSR2_U0 43
+#define FPSR2_I0 44
+
+//
+// Status Field 3 - Controls
+//
+#define FPSR3_FTZ0 45
+#define FPSR3_WRE0 46
+#define FPSR3_PC0 47
+#define FPSR3_RC0 49
+#define FPSR3_TD0 51
+
+//
+// Status Field 0 - Flags
+//
+#define FPSR3_V0 52
+#define FPSR3_D0 53
+#define FPSR3_Z0 54
+#define FPSR3_O0 55
+#define FPSR3_U0 56
+#define FPSR3_I0 57
+
+//
+// FPSR bits 58-63 Reserved -- Must be zero
+//
+#define FPSR_MBZ0 58
+#define FPSR_MBZ0_V 0x3fUL L
+
+//
+// For setting up FPSR on kernel entry
+// All traps are disabled.
+//
+#define FPSR_FOR_KERNEL 0x3f
+
+#define FP_REG_SIZE 16 // 16 byte spill size
+#define HIGHFP_REGS_LENGTH (96 * 16)
+
+//
+// Define hardware Task Priority Register (TPR)
+//
+//
+// TPR bit positions
+//
+#define TPR_MIC 4 // Bits 0 - 3 ignored
+#define TPR_MIC_LEN 4
+#define TPR_MMI 16 // Mask Maskable Interrupt
+//
+// Define hardware Interrupt Status Register (ISR)
+//
+//
+// ISR bit positions
+//
+#define ISR_CODE 0
+#define ISR_CODE_LEN 16
+#define ISR_CODE_MASK 0xFFFF
+#define ISR_IA_VECTOR 16
+#define ISR_IA_VECTOR_LEN 8
+#define ISR_MBZ0 24
+#define ISR_MBZ0_V 0xff
+#define ISR_X 32
+#define ISR_W 33
+#define ISR_R 34
+#define ISR_NA 35
+#define ISR_SP 36
+#define ISR_RS 37
+#define ISR_IR 38
+#define ISR_NI 39
+#define ISR_MBZ1 40
+#define ISR_EI 41
+#define ISR_ED 43
+#define ISR_MBZ2 44
+#define ISR_MBZ2_V 0xfffff
+
+//
+// ISR codes
+//
+// For General exceptions: ISR{3:0}
+//
+#define ISR_ILLEGAL_OP 0 // Illegal operation fault
+#define ISR_PRIV_OP 1 // Privileged operation fault
+#define ISR_PRIV_REG 2 // Privileged register fauls
+#define ISR_RESVD_REG 3 // Reserved register/field flt
+#define ISR_ILLEGAL_ISA 4 // Disabled instruction set transition fault
+//
+// Define hardware Default Control Register (DCR)
+//
+//
+// DCR bit positions
+//
+#define DCR_PP 0
+#define DCR_BE 1
+#define DCR_LC 2
+#define DCR_MBZ0 4
+#define DCR_MBZ0_V 0xf
+#define DCR_DM 8
+#define DCR_DP 9
+#define DCR_DK 10
+#define DCR_DX 11
+#define DCR_DR 12
+#define DCR_DA 13
+#define DCR_DD 14
+#define DCR_DEFER_ALL 0x7f00
+#define DCR_MBZ1 2
+#define DCR_MBZ1_V 0xffffffffffffUL L
+
+//
+// Define hardware RSE Configuration Register
+//
+// RS Configuration (RSC) bit field positions
+//
+#define RSC_MODE 0
+#define RSC_PL 2
+#define RSC_BE 4
+#define RSC_MBZ0 5
+#define RSC_MBZ0_V 0x3ff
+#define RSC_LOADRS 16
+#define RSC_LOADRS_LEN 14
+#define RSC_MBZ1 30
+#define RSC_MBZ1_V 0x3ffffffffUL L
+
+//
+// RSC modes
+//
+#define RSC_MODE_LY (0x0) // Lazy
+#define RSC_MODE_SI (0x1) // Store intensive
+#define RSC_MODE_LI (0x2) // Load intensive
+#define RSC_MODE_EA (0x3) // Eager
+//
+// RSC Endian bit values
+//
+#define RSC_BE_LITTLE 0
+#define RSC_BE_BIG 1
+
+//
+// Define Interruption Function State (IFS) Register
+//
+// IFS bit field positions
+//
+#define IFS_IFM 0
+#define IFS_IFM_LEN 38
+#define IFS_MBZ0 38
+#define IFS_MBZ0_V 0x1ffffff
+#define IFS_V 63
+#define IFS_V_LEN 1
+
+//
+// IFS is valid when IFS_V = IFS_VALID
+//
+#define IFS_VALID 1
+
+//
+// Define Page Table Address (PTA)
+//
+#define PTA_VE 0
+#define PTA_VF 8
+#define PTA_SIZE 2
+#define PTA_SIZE_LEN 6
+#define PTA_BASE 15
+
+//
+// Define Region Register (RR)
+//
+//
+// RR bit field positions
+//
+#define RR_VE 0
+#define RR_MBZ0 1
+#define RR_PS 2
+#define RR_PS_LEN 6
+#define RR_RID 8
+#define RR_RID_LEN 24
+#define RR_MBZ1 32
+
+//
+// SAL uses region register 0 and RID of 1000
+//
+#define SAL_RID 0x1000
+#define SAL_RR_REG 0x0
+#define SAL_TR 0x0
+
+//
+// Total number of region registers
+//
+#define RR_SIZE 8
+
+//
+// Define Protection Key Register (PKR)
+//
+// PKR bit field positions
+//
+#define PKR_V 0
+#define PKR_WD 1
+#define PKR_RD 2
+#define PKR_XD 3
+#define PKR_MBZ0 4
+#define PKR_KEY 8
+#define PKR_KEY_LEN 24
+#define PKR_MBZ1 32
+
+#define PKR_VALID (1 << PKR_V)
+
+//
+// Number of protection key registers
+//
+#define PKRNUM 8
+
+//
+// Define Interruption TLB Insertion register (ITIR)
+//
+//
+// Define Translation Insertion Format (TR)
+//
+// PTE0 bit field positions
+//
+#define PTE0_P 0
+#define PTE0_MBZ0 1
+#define PTE0_MA 2
+#define PTE0_A 5
+#define PTE0_D 6
+#define PTE0_PL 7
+#define PTE0_AR 9
+#define PTE0_PPN 12
+#define PTE0_MBZ1 48
+#define PTE0_ED 52
+#define PTE0_IGN0 53
+
+//
+// ITIR bit field positions
+//
+#define ITIR_MBZ0 0
+#define ITIR_PS 2
+#define ITIR_PS_LEN 6
+#define ITIR_KEY 8
+#define ITIR_KEY_LEN 24
+#define ITIR_MBZ1 32
+#define ITIR_MBZ1_LEN 16
+#define ITIR_PPN 48
+#define ITIR_PPN_LEN 15
+#define ITIR_MBZ2 63
+
+#define ATTR_IPAGE 0x661 // Access Rights = RWX (bits 11-9=011), PL 0(8-7=0)
+#define ATTR_DEF_BITS 0x661 // Access Rights = RWX (bits 11-9=010), PL 0(8-7=0)
+// Dirty (bit 6=1), Accessed (bit 5=1),
+// MA WB (bits 4-2=000), Present (bit 0=1)
+//
+// Memory access rights
+//
+#define AR_UR_KR 0x0 // user/kernel read
+#define AR_URX_KRX 0x1 // user/kernel read and execute
+#define AR_URW_KRW 0x2 // user/kernel read & write
+#define AR_URWX_KRWX 0x3 // user/kernel read,write&execute
+#define AR_UR_KRW 0x4 // user read/kernel read,write
+#define AR_URX_KRWX 0x5 // user read/execute, kernel all
+#define AR_URWX_KRW 0x6 // user all, kernel read & write
+#define AR_UX_KRX 0x7 // user execute only, kernel read and execute
+//
+// Memory attribute values
+//
+//
+// The next 4 are all cached, non-sequential & speculative, coherent
+//
+#define MA_WBU 0x0 // Write back, unordered
+//
+// The next 3 are all non-cached, sequential & non-speculative
+//
+#define MA_UC 0x4 // Non-coalescing, sequential & non-speculative
+#define MA_UCE 0x5 // Non-coalescing, sequential, non-speculative
+// & fetchadd exported
+//
+#define MA_WC 0x6 // Non-cached, Coalescing, non-seq., spec.
+#define MA_NAT 0xf // NaT page
+//
+// Definition of the offset of TRAP/INTERRUPT/FAULT handlers from the
+// base of IVA (Interruption Vector Address)
+//
+#define IVT_SIZE 0x8000
+#define EXTRA_ALIGNMENT 0x1000
+
+#define OFF_VHPTFLT 0x0000 // VHPT Translation fault
+#define OFF_ITLBFLT 0x0400 // Instruction TLB fault
+#define OFF_DTLBFLT 0x0800 // Data TLB fault
+#define OFF_ALTITLBFLT 0x0C00 // Alternate ITLB fault
+#define OFF_ALTDTLBFLT 0x1000 // Alternate DTLB fault
+#define OFF_NESTEDTLBFLT 0x1400 // Nested TLB fault
+#define OFF_IKEYMISSFLT 0x1800 // Inst Key Miss fault
+#define OFF_DKEYMISSFLT 0x1C00 // Data Key Miss fault
+#define OFF_DIRTYBITFLT 0x2000 // Dirty-Bit fault
+#define OFF_IACCESSBITFLT 0x2400 // Inst Access-Bit fault
+#define OFF_DACCESSBITFLT 0x2800 // Data Access-Bit fault
+#define OFF_BREAKFLT 0x2C00 // Break Inst fault
+#define OFF_EXTINT 0x3000 // External Interrupt
+//
+// Offset 0x3400 to 0x0x4C00 are reserved
+//
+#define OFF_PAGENOTPFLT 0x5000 // Page Not Present fault
+#define OFF_KEYPERMFLT 0x5100 // Key Permission fault
+#define OFF_IACCESSRTFLT 0x5200 // Inst Access-Rights flt
+#define OFF_DACCESSRTFLT 0x5300 // Data Access-Rights fault
+#define OFF_GPFLT 0x5400 // General Exception fault
+#define OFF_FPDISFLT 0x5500 // Disable-FP fault
+#define OFF_NATFLT 0x5600 // NAT Consumption fault
+#define OFF_SPECLNFLT 0x5700 // Speculation fault
+#define OFF_DBGFLT 0x5900 // Debug fault
+#define OFF_ALIGNFLT 0x5A00 // Unaligned Reference fault
+#define OFF_LOCKDREFFLT 0x5B00 // Locked Data Reference fault
+#define OFF_FPFLT 0x5C00 // Floating Point fault
+#define OFF_FPTRAP 0x5D00 // Floating Point Trap
+#define OFF_LOPRIVTRAP 0x5E00 // Lower-Privilege Transfer Trap
+#define OFF_TAKENBRTRAP 0x5F00 // Taken Branch Trap
+#define OFF_SSTEPTRAP 0x6000 // Single Step Trap
+//
+// Offset 0x6100 to 0x6800 are reserved
+//
+#define OFF_IA32EXCEPTN 0x6900 // iA32 Exception
+#define OFF_IA32INTERCEPT 0x6A00 // iA32 Intercept
+#define OFF_IA32INT 0x6B00 // iA32 Interrupt
+#define NUMBER_OF_VECTORS 0x100
+//
+// Privilege levels
+//
+#define PL_KERNEL 0
+#define PL_USER 3
+
+//
+// Instruction set (IS) bits
+//
+#define IS_IA64 0
+#define IS_IA 1
+
+//
+// RSC while in kernel: enabled, little endian, PL = 0, eager mode
+//
+#define RSC_KERNEL ((RSC_MODE_EA << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
+
+//
+// Lazy RSC in kernel: enabled, little endian, pl = 0, lazy mode
+//
+#define RSC_KERNEL_LAZ ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
+
+//
+// RSE disabled: disabled, PL = 0, little endian, eager mode
+//
+#define RSC_KERNEL_DISABLED ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
+
+#define NAT_BITS_PER_RNAT_REG 63
+
+//
+// Macros for generating PTE0 and PTE1 value
+//
+#define PTE0(ed, ppn12_47, ar, pl, d, a, ma, p) \
+ ( ( ed << PTE0_ED ) | \
+ ( ppn12_47 << PTE0_PPN ) | \
+ ( ar << PTE0_AR ) | \
+ ( pl << PTE0_PL ) | \
+ ( d << PTE0_D ) | \
+ ( a << PTE0_A ) | \
+ ( ma << PTE0_MA ) | \
+ ( p << PTE0_P ) \
+ )
+
+#define ITIR(ppn48_63, key, ps) \
+ ( ( ps << ITIR_PS ) | \
+ ( key << ITIR_KEY ) | \
+ ( ppn48_63 << ITIR_PPN ) \
+ )
+
+//
+// Macro to generate mask value from bit position. The result is a
+// 64-bit.
+//
+#define BITMASK(bp, value) (value << bp)
+
+#define BUNDLE_SIZE 16
+#define SPURIOUS_INT 0xF
+
+#define FAST_DISABLE_INTERRUPTS rsm BITMASK (PSR_I, 1);;
+
+#define FAST_ENABLE_INTERRUPTS ssm BITMASK (PSR_I, 1);;
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/Ipf/IpfMacro.i b/EdkCompatibilityPkg/Foundation/Include/Ipf/IpfMacro.i new file mode 100644 index 0000000000..68c5f8c540 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/Ipf/IpfMacro.i @@ -0,0 +1,66 @@ +//++
+// Copyright (c) 2004, Intel Corporation
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Module Name:
+//
+// IpfMacro.i
+//
+// Abstract:
+//
+// Contains the macros needed for calling procedures in Itanium-based assembly code.
+//
+//
+// Revision History:
+//
+//--
+
+#ifndef _IA64PROC_I
+#define _IA64PROC_I
+
+
+#define PROCEDURE_ENTRY(name) .##text; \
+ .##type name, @function; \
+ .##proc name; \
+name::
+
+#define PROCEDURE_EXIT(name) .##endp name
+
+// Note: use of NESTED_SETUP requires number of locals (l) >= 3
+
+#define NESTED_SETUP(i,l,o,r) \
+ alloc loc1=ar##.##pfs,i,l,o,r ;\
+ mov loc0=b0
+
+#define NESTED_RETURN \
+ mov b0=loc0 ;\
+ mov ar##.##pfs=loc1 ;;\
+ br##.##ret##.##dpnt b0;;
+
+
+#define INTERRUPT_HANDLER_BEGIN(name) \
+PROCEDURE_ENTRY(name##HandlerBegin) \
+;; \
+PROCEDURE_EXIT(name##HandlerBegin)
+
+#define INTERRUPT_HANDLER_END(name) \
+PROCEDURE_ENTRY(name##HandlerEnd) \
+;; \
+PROCEDURE_EXIT(name##HandlerEnd)
+
+
+#define INTERRUPT_HANDLER_BLOCK_BEGIN \
+INTERRUPT_HANDLER_BEGIN(First)
+
+#define INTERRUPT_HANDLER_BLOCK_END \
+INTERRUPT_HANDLER_END(Last)
+
+
+
+#endif // _IA64PROC_I
diff --git a/EdkCompatibilityPkg/Foundation/Include/Ipf/PalApi.h b/EdkCompatibilityPkg/Foundation/Include/Ipf/PalApi.h new file mode 100644 index 0000000000..aaa6a64022 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/Ipf/PalApi.h @@ -0,0 +1,133 @@ +/*++
+
+Copyright (c) 2004, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ PalApi.h
+
+Abstract:
+
+ Main PAL API's defined in PAL specification.
+
+
+Revision History:
+
+--*/
+
+#ifndef _PALPROC_H
+#define _PALPROC_H
+
+#include "Tiano.h"
+
+#define PAL_CACHE_FLUSH 0x0001
+#define PAL_CACHE_INFO 0x0002
+#define PAL_CACHE_INIT 0x0003
+#define PAL_CACHE_SUMMARY 0x0004
+#define PAL_MEM_ATTRIB 0x0005
+#define PAL_PTCE_INFO 0x0006
+#define PAL_VM_INFO 0x0007
+#define PAL_VM_SUMMARY 0x0008
+#define PAL_BUS_GET_FEATURES 0x0009
+#define PAL_BUS_SET_FEATURES 0x000a
+#define PAL_DEBUG_INFO 0x000b
+#define PAL_FIXED_ADDR 0x000c
+#define PAL_FREQ_BASE 0x000d
+#define PAL_FREQ_RATIOS 0x000e
+#define PAL_PERF_MON_INFO 0x000f
+#define PAL_PLATFORM_ADDR 0x0010
+#define PAL_PROC_GET_FEATURES 0x0011
+#define PAL_PROC_SET_FEATURES 0x0012
+#define PAL_RSE_INFO 0x0013
+#define PAL_VERSION 0x0014
+
+#define PAL_MC_CLEAR_LOG 0x0015
+#define PAL_MC_DRAIN 0x0016
+#define PAL_MC_EXPECTED 0x0017
+#define PAL_MC_DYNAMIC_STATE 0x0018
+#define PAL_MC_ERROR_INFO 0x0019
+#define PAL_MC_RESUME 0x001a
+#define PAL_MC_REGISTER_MEM 0x001b
+#define PAL_HALT 0x001c
+#define PAL_HALT_LIGHT 0x001d
+#define PAL_COPY_INFO 0x001e
+#define PAL_SHUTDOWN 0x002c
+#define PAL_AUTH 0x0209
+#define PAL_SINGL_DISPERSAL 0x0226 // dec. 550
+#define PAL_HALT_INFO 0x0101
+#define PAL_CACHE_LINE_INIT 0x001f
+#define PAL_PMI_ENTRYPOINT 0x0020
+#define PAL_ENTER_IA_32_ENV 0x0021
+#define PAL_VM_PAGE_SIZE 0x0022
+#define PAL_MEM_FOR_TEST 0x0025
+#define PAL_CACHE_PROT_INFO 0x0026
+
+#define PAL_COPY_PAL 0x0100
+#define PAL_CACHE_READ 0x0103
+#define PAL_CACHE_WRITE 0x0104
+#define PAL_TEST_PROC 0x0102
+
+#define PAL_DEBUG_FEATURE 0x0063 // vp1
+typedef UINT64 EFI_PAL_STATUS;
+
+//
+// Return values from PAL
+//
+typedef struct {
+ EFI_PAL_STATUS Status; // register r8
+ UINT64 r9;
+ UINT64 r10;
+ UINT64 r11;
+} PAL_RETURN_REGS;
+
+//
+// PAL equates for other parameters.
+//
+#define PAL_SUCCESS 0x0
+#define PAL_CALL_ERROR 0xfffffffffffffffd
+#define PAL_CALL_UNIMPLEMENTED 0xffffffffffffffff
+#define PAL_CACHE_TYPE_I 0x1
+#define PAL_CACHE_TYPE_D 0x2
+#define PAL_CACHE_TYPE_I_AND_D 0x3
+#define PAL_CACHE_NO_INT 0x0
+#define PAL_CACHE_INT 0x2
+//
+// #define PAL_CACHE_PLAT_ACK 0x4
+//
+#define PAL_CACHE_NO_PLAT_ACK 0x0
+#define PAL_CACHE_INVALIDATE 0x1
+#define PAL_CACHE_NO_INVALIDATE 0x0
+#define PAL_CACHE_ALL_LEVELS - 0x1
+
+#define PAL_FEATURE_ENABLE 0x1
+#define PAL_ENABLE_BERR_BIT 63
+#define PAL_ENABLE_MCA_BINIT_BIT 61
+#define PAL_ENABLE_CMCI_MCA_BIT 60
+#define PAL_CACHE_DISABLE_BIT 59
+#define PAL_DISABLE_COHERENCY_BIT 58
+
+#define PAL_DIS_BUS_DATA_ERR_CHECK_BIT 63
+#define PAL_DIS_BUS_ADDR_ERR_CHECK_BIT 61
+#define PAL_DIS_BUS_INIT_EVENT_SIGNAL_BIT 60
+#define PAL_DIS_BUS_REQ_ERR_SIGNAL_BIT 58
+#define PAL_DIS_BUS_REQ_INT_ERR_SIGNAL_BIT 57
+#define PAL_DIS_BUS_REQ_ERR_CHECK_BIT 56
+#define PAL_DIS_BUS_RESP_ERR_CHECK_BIT 55
+
+#define PAL_COPY_BSP_TOKEN 0x0
+#define PAL_COPY_AP_TOKEN 0x1
+
+#define PAL_CODE_TOKEN 0x0
+#define PAL_IA32EMU_CODE_TOKEN 0x1
+
+#define PAL_INTERRUPT_BLOCK_TOKEN 0x0
+#define PAL_IO_BLOCK_TOKEN 0x1
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/Ipf/SalApi.h b/EdkCompatibilityPkg/Foundation/Include/Ipf/SalApi.h new file mode 100644 index 0000000000..a6a7e4d838 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/Ipf/SalApi.h @@ -0,0 +1,724 @@ +/*++
+
+Copyright (c) 2004, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ SalApi.h
+
+Abstract:
+
+ Main SAL API's defined in SAL 3.0 specification.
+
+
+Revision History:
+
+--*/
+
+#ifndef _SAL_API_H_
+#define _SAL_API_H_
+
+typedef UINTN EFI_SAL_STATUS;
+
+//
+// EFI_SAL_STATUS defines
+//
+#define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)
+#define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)
+#define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)
+#define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)
+#define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)
+#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)
+#define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)
+#define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)
+
+//
+// Delivery Mode of IPF CPU.
+//
+typedef enum {
+ INT,
+ MPreserved1,
+ PMI,
+ MPreserved2,
+ NMI,
+ INIT,
+ MPreserved3,
+ ExtINT
+} EFI_DELIVERY_MODE;
+
+//
+// Return values from SAL
+//
+typedef struct {
+ EFI_SAL_STATUS Status; // register r8
+ UINTN r9;
+ UINTN r10;
+ UINTN r11;
+} SAL_RETURN_REGS;
+
+typedef SAL_RETURN_REGS (EFIAPI *SAL_PROC)
+ (
+ IN UINT64 FunctionId,
+ IN UINT64 Arg2,
+ IN UINT64 Arg3,
+ IN UINT64 Arg4,
+ IN UINT64 Arg5,
+ IN UINT64 Arg6,
+ IN UINT64 Arg7,
+ IN UINT64 Arg8
+ );
+
+//
+// SAL Procedure FunctionId definition
+//
+#define EFI_SAL_SET_VECTORS 0x01000000
+#define EFI_SAL_GET_STATE_INFO 0x01000001
+#define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002
+#define EFI_SAL_CLEAR_STATE_INFO 0x01000003
+#define EFI_SAL_MC_RENDEZ 0x01000004
+#define EFI_SAL_MC_SET_PARAMS 0x01000005
+#define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006
+#define EFI_SAL_CACHE_FLUSH 0x01000008
+#define EFI_SAL_CACHE_INIT 0x01000009
+#define EFI_SAL_PCI_CONFIG_READ 0x01000010
+#define EFI_SAL_PCI_CONFIG_WRITE 0x01000011
+#define EFI_SAL_FREQ_BASE 0x01000012
+#define EFI_SAL_UPDATE_PAL 0x01000020
+
+#define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff
+#define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021
+
+//
+// SAL Procedure parameter definitions
+// Not much point in using typedefs or enums because all params
+// are UINT64 and the entry point is common
+//
+// EFI_SAL_SET_VECTORS
+//
+#define EFI_SAL_SET_MCA_VECTOR 0x0
+#define EFI_SAL_SET_INIT_VECTOR 0x1
+#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2
+
+typedef struct {
+ UINT64 Length : 32;
+ UINT64 ChecksumValid : 1;
+ UINT64 Reserved1 : 7;
+ UINT64 ByteChecksum : 8;
+ UINT64 Reserved2 : 16;
+} SAL_SET_VECTORS_CS_N;
+
+//
+// EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,
+// EFI_SAL_CLEAR_STATE_INFO
+//
+#define EFI_SAL_MCA_STATE_INFO 0x0
+#define EFI_SAL_INIT_STATE_INFO 0x1
+#define EFI_SAL_CMC_STATE_INFO 0x2
+#define EFI_SAL_CP_STATE_INFO 0x3
+
+//
+// EFI_SAL_MC_SET_PARAMS
+//
+#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1
+#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2
+#define EFI_SAL_MC_SET_CPE_PARAM 0x3
+
+#define EFI_SAL_MC_SET_INTR_PARAM 0x1
+#define EFI_SAL_MC_SET_MEM_PARAM 0x2
+
+//
+// EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR
+//
+#define EFI_SAL_REGISTER_PAL_ADDR 0x0
+
+//
+// EFI_SAL_CACHE_FLUSH
+//
+#define EFI_SAL_FLUSH_I_CACHE 0x01
+#define EFI_SAL_FLUSH_D_CACHE 0x02
+#define EFI_SAL_FLUSH_BOTH_CACHE 0x03
+#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04
+
+//
+// EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE
+//
+#define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1
+#define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2
+#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4
+
+typedef struct {
+ UINT64 Register : 8;
+ UINT64 Function : 3;
+ UINT64 Device : 5;
+ UINT64 Bus : 8;
+ UINT64 Segment : 8;
+ UINT64 Reserved : 32;
+} SAL_PCI_ADDRESS;
+
+//
+// EFI_SAL_FREQ_BASE
+//
+#define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0
+#define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1
+#define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2
+
+//
+// EFI_SAL_UPDATE_PAL
+//
+#define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)
+#define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)
+#define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3)
+#define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4)
+#define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10)
+#define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)
+#define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)
+#define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)
+
+typedef struct {
+ UINT32 Size;
+ UINT32 MmddyyyyDate;
+ UINT16 Version;
+ UINT8 Type;
+ UINT8 Reserved[5];
+ UINT64 FwVendorId;
+} SAL_UPDATE_PAL_DATA_BLOCK;
+
+typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {
+ struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;
+ struct SAL_UPDATE_PAL_DATA_BLOCK *DataBlock;
+ UINT8 StoreChecksum;
+ UINT8 Reserved[15];
+} SAL_UPDATE_PAL_INFO_BLOCK;
+
+//
+// SAL System Table Definitions
+//
+#pragma pack(1)
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT16 SalRevision;
+ UINT16 EntryCount;
+ UINT8 CheckSum;
+ UINT8 Reserved[7];
+ UINT16 SalAVersion;
+ UINT16 SalBVersion;
+ UINT8 OemId[32];
+ UINT8 ProductId[32];
+ UINT8 Reserved2[8];
+} SAL_SYSTEM_TABLE_HEADER;
+#pragma pack()
+
+#define EFI_SAL_ST_HEADER_SIGNATURE "SST_"
+#define EFI_SAL_REVISION 0x0300
+//
+// SAL System Types
+//
+#define EFI_SAL_ST_ENTRY_POINT 0
+#define EFI_SAL_ST_MEMORY_DESCRIPTOR 1
+#define EFI_SAL_ST_PLATFORM_FEATURES 2
+#define EFI_SAL_ST_TR_USAGE 3
+#define EFI_SAL_ST_PTC 4
+#define EFI_SAL_ST_AP_WAKEUP 5
+
+#pragma pack(1)
+typedef struct {
+ UINT8 Type; // Type == 0
+ UINT8 Reserved[7];
+ UINT64 PalProcEntry;
+ UINT64 SalProcEntry;
+ UINT64 SalGlobalDataPointer;
+ UINT64 Reserved2[2];
+} SAL_ST_ENTRY_POINT_DESCRIPTOR;
+
+//
+// Not needed for Itanium-based OS boot
+//
+typedef struct {
+ UINT8 Type; // Type == 1
+ UINT8 NeedVirtualRegistration;
+ UINT8 MemoryAttributes;
+ UINT8 PageAccessRights;
+ UINT8 SupportedAttributes;
+ UINT8 Reserved;
+ UINT8 MemoryType;
+ UINT8 MemoryUsage;
+ UINT64 PhysicalMemoryAddress;
+ UINT32 Length;
+ UINT32 Reserved1;
+ UINT64 OemReserved;
+} SAL_ST_MEMORY_DESCRIPTOR_ENTRY;
+
+#pragma pack()
+//
+// Memory Attributes
+//
+#define SAL_MDT_ATTRIB_WB 0x00
+//
+// #define SAL_MDT_ATTRIB_UC 0x02
+//
+#define SAL_MDT_ATTRIB_UC 0x04
+#define SAL_MDT_ATTRIB_UCE 0x05
+#define SAL_MDT_ATTRIB_WC 0x06
+
+//
+// Supported memory Attributes
+//
+#define SAL_MDT_SUPPORT_WB 0x1
+#define SAL_MDT_SUPPORT_UC 0x2
+#define SAL_MDT_SUPPORT_UCE 0x4
+#define SAL_MDT_SUPPORT_WC 0x8
+
+//
+// Virtual address registration
+//
+#define SAL_MDT_NO_VA 0x00
+#define SAL_MDT_NEED_VA 0x01
+//
+// MemoryType info
+//
+#define SAL_REGULAR_MEMORY 0x0000
+#define SAL_MMIO_MAPPING 0x0001
+#define SAL_SAPIC_IPI_BLOCK 0x0002
+#define SAL_IO_PORT_MAPPING 0x0003
+#define SAL_FIRMWARE_MEMORY 0x0004
+#define SAL_BLACK_HOLE 0x000A
+//
+// Memory Usage info
+//
+#define SAL_MDT_USAGE_UNSPECIFIED 0x00
+#define SAL_PAL_CODE 0x01
+#define SAL_BOOTSERVICE_CODE 0x02
+#define SAL_BOOTSERVICE_DATA 0x03
+#define SAL_RUNTIMESERVICE_CODE 0x04
+#define SAL_RUNTIMESERVICE_DATA 0x05
+#define SAL_IA32_OPTIONROM 0x06
+#define SAL_IA32_SYSTEMROM 0x07
+#define SAL_PMI_CODE 0x0a
+#define SAL_PMI_DATA 0x0b
+
+#pragma pack(1)
+typedef struct {
+ UINT8 Type; // Type == 2
+ UINT8 PlatformFeatures;
+ UINT8 Reserved[14];
+} SAL_ST_PLATFORM_FEATURES;
+#pragma pack()
+
+#define SAL_PLAT_FEAT_BUS_LOCK 0x01
+#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02
+#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04
+
+#pragma pack(1)
+typedef struct {
+ UINT8 Type; // Type == 3
+ UINT8 TRType;
+ UINT8 TRNumber;
+ UINT8 Reserved[5];
+ UINT64 VirtualAddress;
+ UINT64 EncodedPageSize;
+ UINT64 Reserved1;
+} SAL_ST_TR_DECRIPTOR;
+#pragma pack()
+
+#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00
+#define EFI_SAL_ST_TR_USAGE_DATA 01
+
+#pragma pack(1)
+typedef struct {
+ UINT64 NumberOfProcessors;
+ UINT64 LocalIDRegister;
+} SAL_COHERENCE_DOMAIN_INFO;
+#pragma pack()
+
+#pragma pack(1)
+typedef struct {
+ UINT8 Type; // Type == 4
+ UINT8 Reserved[3];
+ UINT32 NumberOfDomains;
+ SAL_COHERENCE_DOMAIN_INFO *DomainInformation;
+} SAL_ST_CACHE_COHERENCE_DECRIPTOR;
+#pragma pack()
+
+#pragma pack(1)
+typedef struct {
+ UINT8 Type; // Type == 5
+ UINT8 WakeUpType;
+ UINT8 Reserved[6];
+ UINT64 ExternalInterruptVector;
+} SAL_ST_AP_WAKEUP_DECRIPTOR;
+#pragma pack()
+//
+// FIT Entry
+//
+#define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24
+#define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32
+#define EFI_SAL_FIT_PALB_TYPE 01
+
+typedef struct {
+ UINT64 Address;
+ UINT8 Size[3];
+ UINT8 Reserved;
+ UINT16 Revision;
+ UINT8 Type : 7;
+ UINT8 CheckSumValid : 1;
+ UINT8 CheckSum;
+} EFI_SAL_FIT_ENTRY;
+
+//
+// SAL Common Record Header
+//
+typedef struct {
+ UINT16 Length;
+ UINT8 Data[1024];
+} SAL_OEM_DATA;
+
+typedef struct {
+ UINT8 Seconds;
+ UINT8 Minutes;
+ UINT8 Hours;
+ UINT8 Reserved;
+ UINT8 Day;
+ UINT8 Month;
+ UINT8 Year;
+ UINT8 Century;
+} SAL_TIME_STAMP;
+
+typedef struct {
+ UINT64 RecordId;
+ UINT16 Revision;
+ UINT8 ErrorSeverity;
+ UINT8 ValidationBits;
+ UINT32 RecordLength;
+ SAL_TIME_STAMP TimeStamp;
+ UINT8 OemPlatformId[16];
+} SAL_RECORD_HEADER;
+
+typedef struct {
+ EFI_GUID Guid;
+ UINT16 Revision;
+ UINT8 ErrorRecoveryInfo;
+ UINT8 Reserved;
+ UINT32 SectionLength;
+} SAL_SEC_HEADER;
+
+//
+// SAL Processor Record
+//
+#define SAL_PROCESSOR_ERROR_RECORD_INFO \
+ { \
+ 0xe429faf1, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 \
+ }
+
+#define CHECK_INFO_VALID_BIT_MASK 0x1
+#define REQUESTOR_ID_VALID_BIT_MASK 0x2
+#define RESPONDER_ID_VALID_BIT_MASK 0x4
+#define TARGER_ID_VALID_BIT_MASK 0x8
+#define PRECISE_IP_VALID_BIT_MASK 0x10
+
+typedef struct {
+ UINT64 InfoValid : 1;
+ UINT64 ReqValid : 1;
+ UINT64 RespValid : 1;
+ UINT64 TargetValid : 1;
+ UINT64 IpValid : 1;
+ UINT64 Reserved : 59;
+ UINT64 Info;
+ UINT64 Req;
+ UINT64 Resp;
+ UINT64 Target;
+ UINT64 Ip;
+} MOD_ERROR_INFO;
+
+typedef struct {
+ UINT8 CpuidInfo[40];
+ UINT8 Reserved;
+} CPUID_INFO;
+
+typedef struct {
+ UINT64 FrLow;
+ UINT64 FrHigh;
+} FR_STRUCT;
+
+#define MIN_STATE_VALID_BIT_MASK 0x1
+#define BR_VALID_BIT_MASK 0x2
+#define CR_VALID_BIT_MASK 0x4
+#define AR_VALID_BIT_MASK 0x8
+#define RR_VALID_BIT_MASK 0x10
+#define FR_VALID_BIT_MASK 0x20
+
+typedef struct {
+ UINT64 ValidFieldBits;
+ UINT8 MinStateInfo[1024];
+ UINT64 Br[8];
+ UINT64 Cr[128];
+ UINT64 Ar[128];
+ UINT64 Rr[8];
+ FR_STRUCT Fr[128];
+} PSI_STATIC_STRUCT;
+
+#define PROC_ERROR_MAP_VALID_BIT_MASK 0x1
+#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2
+#define PROC_CR_LID_VALID_BIT_MASK 0x4
+#define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8
+#define CPU_INFO_VALID_BIT_MASK 0x1000000
+
+typedef struct {
+ SAL_SEC_HEADER SectionHeader;
+ UINT64 ValidationBits;
+ UINT64 ProcErrorMap;
+ UINT64 ProcStateParameter;
+ UINT64 ProcCrLid;
+ MOD_ERROR_INFO CacheError[15];
+ MOD_ERROR_INFO TlbError[15];
+ MOD_ERROR_INFO BusError[15];
+ MOD_ERROR_INFO RegFileCheck[15];
+ MOD_ERROR_INFO MsCheck[15];
+ CPUID_INFO CpuInfo;
+ PSI_STATIC_STRUCT PsiValidData;
+} SAL_PROCESSOR_ERROR_RECORD;
+
+//
+// Sal Platform memory Error Record
+//
+#define SAL_MEMORY_ERROR_RECORD_INFO \
+ { \
+ 0xe429faf2, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 \
+ }
+
+#define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1
+#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2
+#define MEMORY_ADDR_BIT_MASK 0x4
+#define MEMORY_NODE_VALID_BIT_MASK 0x8
+#define MEMORY_CARD_VALID_BIT_MASK 0x10
+#define MEMORY_MODULE_VALID_BIT_MASK 0x20
+#define MEMORY_BANK_VALID_BIT_MASK 0x40
+#define MEMORY_DEVICE_VALID_BIT_MASK 0x80
+#define MEMORY_ROW_VALID_BIT_MASK 0x100
+#define MEMORY_COLUMN_VALID_BIT_MASK 0x200
+#define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400
+#define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800
+#define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000
+#define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000
+#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000
+#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000
+#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000
+
+typedef struct {
+ SAL_SEC_HEADER SectionHeader;
+ UINT64 ValidationBits;
+ UINT64 MemErrorStatus;
+ UINT64 MemPhysicalAddress;
+ UINT64 MemPhysicalAddressMask;
+ UINT16 MemNode;
+ UINT16 MemCard;
+ UINT16 MemModule;
+ UINT16 MemBank;
+ UINT16 MemDevice;
+ UINT16 MemRow;
+ UINT16 MemColumn;
+ UINT16 MemBitPosition;
+ UINT64 ModRequestorId;
+ UINT64 ModResponderId;
+ UINT64 ModTargetId;
+ UINT64 BusSpecificData;
+ UINT8 MemPlatformOemId[16];
+} SAL_MEMORY_ERROR_RECORD;
+
+//
+// PCI BUS Errors
+//
+#define SAL_PCI_BUS_ERROR_RECORD_INFO \
+ { \
+ 0xe429faf4, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 \
+ }
+
+#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1
+#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2
+#define PCI_BUS_ID_VALID_BIT_MASK 0x4
+#define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8
+#define PCI_BUS_DATA_VALID_BIT_MASK 0x10
+#define PCI_BUS_CMD_VALID_BIT_MASK 0x20
+#define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40
+#define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80
+#define PCI_BUS_TARGET_VALID_BIT_MASK 0x100
+#define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200
+#define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400
+
+typedef enum {
+ Unknown,
+ DataParityError,
+ SystemError,
+ MasterAbort,
+ BusTimeout,
+ MasterDataParityError,
+ AddressParityError,
+ CommandParityError
+} PCI_BUS_ERROR_TYPE;
+
+typedef struct {
+ UINT8 BusNumber;
+ UINT8 SegmentNumber;
+} PCI_BUS_ID;
+
+typedef struct {
+ SAL_SEC_HEADER SectionHeader;
+ UINT64 ValidationBits;
+ UINT64 PciBusErrorStatus;
+ UINT16 PciBusErrorType;
+ PCI_BUS_ID PciBusId;
+ UINT32 Reserved;
+ UINT64 PciBusAddress;
+ UINT64 PciBusData;
+ UINT64 PciBusCommand;
+ UINT64 PciBusRequestorId;
+ UINT64 PciBusResponderId;
+ UINT64 PciBusTargetId;
+ UINT8 PciBusOemId[16];
+} SAL_PCI_BUS_ERROR_RECORD;
+
+//
+// PCI Component Errors
+//
+#define SAL_PCI_COMP_ERROR_RECORD_INFO \
+ { \
+ 0xe429faf6, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 \
+ }
+
+#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1
+#define PCI_COMP_INFO_VALID_BIT_MASK 0x2
+#define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4
+#define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8
+#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10
+#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20
+
+typedef struct {
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT8 ClassCode[3];
+ UINT8 FunctionNumber;
+ UINT8 DeviceNumber;
+ UINT8 BusNumber;
+ UINT8 SegmentNumber;
+ UINT8 Reserved[5];
+} PCI_COMP_INFO;
+
+typedef struct {
+ SAL_SEC_HEADER SectionHeader;
+ UINT64 ValidationBits;
+ UINT64 PciComponentErrorStatus;
+ PCI_COMP_INFO PciComponentInfo;
+ UINT32 PciComponentMemNum;
+ UINT32 PciComponentIoNum;
+ UINT8 PciBusOemId[16];
+} SAL_PCI_COMPONENT_ERROR_RECORD;
+
+//
+// Sal Device Errors Info.
+//
+#define SAL_DEVICE_ERROR_RECORD_INFO \
+ { \
+ 0xe429faf3, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 \
+ }
+
+#define SEL_RECORD_ID_VALID_BIT_MASK 0x1;
+#define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;
+#define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;
+#define SEL_EVM_REV_VALID_BIT_MASK 0x8;
+#define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10;
+#define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20;
+#define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;
+#define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;
+#define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;
+#define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;
+
+typedef struct {
+ SAL_SEC_HEADER SectionHeader;
+ UINT64 ValidationBits;
+ UINT16 SelRecordId;
+ UINT8 SelRecordType;
+ UINT32 TimeStamp;
+ UINT16 GeneratorId;
+ UINT8 EvmRevision;
+ UINT8 SensorType;
+ UINT8 SensorNum;
+ UINT8 EventDirType;
+ UINT8 Data1;
+ UINT8 Data2;
+ UINT8 Data3;
+} SAL_DEVICE_ERROR_RECORD;
+
+//
+// Sal SMBIOS Device Errors Info.
+//
+#define SAL_SMBIOS_ERROR_RECORD_INFO \
+ { \
+ 0xe429faf5, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 \
+ }
+
+#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1
+#define SMBIOS_LENGTH_VALID_BIT_MASK 0x2
+#define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4
+#define SMBIOS_DATA_VALID_BIT_MASK 0x8
+
+typedef struct {
+ SAL_SEC_HEADER SectionHeader;
+ UINT64 ValidationBits;
+ UINT8 SmbiosEventType;
+ UINT8 SmbiosLength;
+ UINT8 SmbiosBcdTimeStamp[6];
+} SAL_SMBIOS_DEVICE_ERROR_RECORD;
+
+//
+// Sal Platform Specific Errors Info.
+//
+#define SAL_PLATFORM_ERROR_RECORD_INFO \
+ { \
+ 0xe429faf7, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 \
+ }
+
+#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1
+#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2
+#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4
+#define PLATFORM_TARGET_VALID_BIT_MASK 0x8
+#define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10
+#define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20
+#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40
+#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80
+
+typedef struct {
+ SAL_SEC_HEADER SectionHeader;
+ UINT64 ValidationBits;
+ UINT64 PlatformErrorStatus;
+ UINT64 PlatformRequestorId;
+ UINT64 PlatformResponderId;
+ UINT64 PlatformTargetId;
+ UINT64 PlatformBusSpecificData;
+ UINT8 OemComponentId[16];
+} SAL_PLATFORM_SPECIFIC_ERROR_RECORD;
+
+//
+// Union of all the possible Sal Record Types
+//
+typedef union {
+ SAL_RECORD_HEADER *RecordHeader;
+ SAL_PROCESSOR_ERROR_RECORD *SalProcessorRecord;
+ SAL_PCI_BUS_ERROR_RECORD *SalPciBusRecord;
+ SAL_PCI_COMPONENT_ERROR_RECORD *SalPciComponentRecord;
+ SAL_DEVICE_ERROR_RECORD *ImpiRecord;
+ SAL_SMBIOS_DEVICE_ERROR_RECORD *SmbiosRecord;
+ SAL_PLATFORM_SPECIFIC_ERROR_RECORD *PlatformRecord;
+ SAL_MEMORY_ERROR_RECORD *MemoryRecord;
+ UINT8 *Raw;
+} SAL_ERROR_RECORDS_POINTERS;
+
+#pragma pack()
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/Ipf/TianoBind.h b/EdkCompatibilityPkg/Foundation/Include/Ipf/TianoBind.h new file mode 100644 index 0000000000..dc51e1d37e --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/Ipf/TianoBind.h @@ -0,0 +1,30 @@ +/*++
+
+Copyright (c) 2004, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ TianoBind.h
+
+Abstract:
+
+ Tiano's Processor or Compiler specific defines and types for Intel?Itanium(TM)
+ besides EfiBind.h.
+
+--*/
+
+#ifndef _TIANO_BIND_H_
+#define _TIANO_BIND_H_
+
+#include "EfiBind.h"
+
+#define EFI_DXE_ENTRY_POINT(InitFunction)
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/Pei/Pei.h b/EdkCompatibilityPkg/Foundation/Include/Pei/Pei.h new file mode 100644 index 0000000000..cef364b1bf --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/Pei/Pei.h @@ -0,0 +1,58 @@ +/*++
+
+Copyright (c) 2004 - 2005, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ Pei.h
+
+Abstract:
+
+ Framework PEI master include file.
+
+ This is the main include file for Framework PEI components. There should be
+ no defines or macros added to this file, other than the EFI version
+ information already in this file.
+
+ Don't add include files to the list for convenience, only add things
+ that are architectural. Don't add Protocols or GUID include files here
+
+--*/
+
+#ifndef _PEI_H_
+#define _PEI_H_
+
+//
+// PEI Specification Revision information
+//
+#include "TianoCommon.h"
+
+#include "PeiBind.h"
+#include "PeiApi.h"
+#include "EfiDebug.h"
+#include "PeiDebug.h"
+
+//
+// Enable code sharing with DXE by removing ASSERT and DEBUG
+//
+// #define ASSERT(a)
+// #define DEBUG (a)
+//
+
+#ifdef EFI_PEI_REPORT_STATUS_CODE_ON
+#define PEI_REPORT_STATUS_CODE_CODE(Code) Code
+#define PEI_REPORT_STATUS_CODE(PeiServices, CodeType, Value, Instance, CallerId, Data) \
+ (*PeiServices)->PeiReportStatusCode (PeiServices, CodeType, Value, Instance, CallerId, Data)
+#else
+#define PEI_REPORT_STATUS_CODE_CODE(Code)
+#define PEI_REPORT_STATUS_CODE(PeiServices, CodeType, Value, Instance, CallerId, Data)
+#endif
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/Pei/PeiBind.h b/EdkCompatibilityPkg/Foundation/Include/Pei/PeiBind.h new file mode 100644 index 0000000000..a3cdb7b776 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/Pei/PeiBind.h @@ -0,0 +1,160 @@ +/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ PeiBind.h
+
+Abstract:
+
+ Tiano PEI core and PEIM binding macros
+
+--*/
+
+#ifndef _PEI_BIND_H_
+#define _PEI_BIND_H_
+
+#ifdef EFI_DEBUG
+
+#ifdef EFI_NT_EMULATOR
+
+#if (PI_SPECIFICATION_VERSION < 0x00010000)
+
+#define EFI_PEI_CORE_ENTRY_POINT(InitFunction) \
+ UINTN \
+ __stdcall \
+ _DllMainCRTStartup ( \
+ UINTN Inst, \
+ UINTN reason_for_call, \
+ VOID *rserved \
+ ) \
+ { \
+ return 1; \
+ } \
+ \
+ EFI_STATUS \
+ __declspec( dllexport ) \
+ __cdecl \
+ InitializeDriver ( \
+ IN EFI_PEI_STARTUP_DESCRIPTOR *PeiStartup \
+ ) \
+ { \
+ return InitFunction(PeiStartup); \
+ }
+
+#else
+#define EFI_PEI_CORE_ENTRY_POINT(InitFunction) \
+ UINTN \
+ __stdcall \
+ _DllMainCRTStartup ( \
+ UINTN Inst, \
+ UINTN reason_for_call, \
+ VOID *rserved \
+ ) \
+ { \
+ return 1; \
+ } \
+ \
+ EFI_STATUS \
+ __declspec( dllexport ) \
+ __cdecl \
+ InitializeDriver ( \
+ IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData, \
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList \
+ ) \
+ { \
+ return InitFunction(SecCoreData, PpiList); \
+ }
+
+#endif
+
+#define EFI_PEIM_ENTRY_POINT(InitFunction) \
+ UINTN \
+ __stdcall \
+ _DllMainCRTStartup ( \
+ UINTN Inst, \
+ UINTN reason_for_call, \
+ VOID *rserved \
+ ) \
+ { \
+ return 1; \
+ } \
+ \
+ EFI_STATUS \
+ __declspec( dllexport ) \
+ __cdecl \
+ InitializeDriver ( \
+ IN EFI_FFS_FILE_HEADER *FfsHeader, \
+ IN EFI_PEI_SERVICES **PeiServices \
+ ) \
+ { \
+ return InitFunction(FfsHeader, PeiServices); \
+ }
+
+#else
+
+#define EFI_PEI_CORE_ENTRY_POINT(InitFunction)
+#define EFI_PEIM_ENTRY_POINT(InitFunction)
+
+#endif
+
+#else
+
+#ifdef EFI_NT_EMULATOR
+
+#if (PI_SPECIFICATION_VERSION < 0x00010000)
+
+#define EFI_PEI_CORE_ENTRY_POINT(InitFunction) \
+ EFI_STATUS \
+ __declspec( dllexport ) \
+ __cdecl \
+ InitializeDriver ( \
+ IN EFI_PEI_STARTUP_DESCRIPTOR *PeiStartup \
+ ) \
+ { \
+ return InitFunction(PeiStartup); \
+ }
+
+#else
+#define EFI_PEI_CORE_ENTRY_POINT(InitFunction) \
+ EFI_STATUS \
+ __declspec( dllexport ) \
+ __cdecl \
+ InitializeDriver ( \
+ IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData, \
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList \
+ ) \
+ { \
+ return InitFunction(SecCoreData, PpiList); \
+ }
+
+#endif
+
+
+#define EFI_PEIM_ENTRY_POINT(InitFunction) \
+ EFI_STATUS \
+ __declspec( dllexport ) \
+ __cdecl \
+ InitializeDriver ( \
+ IN EFI_FFS_FILE_HEADER *FfsHeader, \
+ IN EFI_PEI_SERVICES **PeiServices \
+ ) \
+ { \
+ return InitFunction(FfsHeader, PeiServices); \
+ }
+#else
+
+#define EFI_PEI_CORE_ENTRY_POINT(InitFunction)
+#define EFI_PEIM_ENTRY_POINT(InitFunction)
+
+#endif
+#endif
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/Pei/PeiDebug.h b/EdkCompatibilityPkg/Foundation/Include/Pei/PeiDebug.h new file mode 100644 index 0000000000..a957c2b521 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/Pei/PeiDebug.h @@ -0,0 +1,104 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ PeiDebug.h
+
+Abstract:
+
+ PEI Debug macros. The work needs to be done in library. The Debug
+ macros them selves are standard for all files, including the core.
+
+ There needs to be code linked in that produces the following macros:
+
+ PeiDebugAssert(file, linenumber, assertion string) - worker function for
+ ASSERT. filename and line number of where this ASSERT() is located
+ is passed in along with the stringized version of the assertion.
+
+ PeiDebugPrint - Worker function for debug print
+
+ _DEBUG_SET_MEM(address, length, value) - Set memory at address to value
+ for legnth bytes. This macro is used to initialzed uninitialized memory
+ or memory that is free'ed, so it will not be used by mistake.
+
+--*/
+
+#ifndef _PEIDEBUG_H_
+#define _PEIDEBUG_H_
+
+#ifdef EFI_DEBUG
+
+ VOID
+ PeiDebugAssert (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CHAR8 *FileName,
+ IN INTN LineNumber,
+ IN CHAR8 *Description
+ );
+
+ VOID
+ PeiDebugPrint (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN UINTN ErrorLevel,
+ IN CHAR8 *Format,
+ ...
+ );
+
+ #define _PEI_DEBUG_ASSERT(PeiST, assertion) \
+ PeiDebugAssert (PeiST, __FILE__, __LINE__, #assertion)
+
+ #define _PEI_DEBUG(PeiST, arg) PeiDebugPrint (PeiST, arg)
+
+ //
+ // Define ASSERT() macro, if assertion is FALSE trigger the ASSERT
+ //
+ #define PEI_ASSERT(PeiST, assertion) if(!(assertion)) \
+ _PEI_DEBUG_ASSERT(PeiST, assertion)
+
+ #define PEI_ASSERT_LOCKED(PeiST, l) if(!(l)->Lock) _PEI_DEBUG_ASSERT(PeiST, l not locked)
+
+ //
+ // DEBUG((DebugLevel, "format string", ...)) - if DebugLevel is active do
+ // the a debug print.
+ //
+
+ #define PEI_DEBUG(arg) PeiDebugPrint arg
+
+ #define PEI_DEBUG_CODE(code) code
+
+ #define PEI_CR(Record, TYPE, Field, Signature) \
+ _CR(Record, TYPE, Field)
+
+
+ #define _PEI_DEBUG_SET_MEM(address, length, data) SetMem(address, length, data)
+
+#else
+ #define PEI_ASSERT(PeiST, a)
+ #define PEI_ASSERT_LOCKED(PeiST, l)
+ #define PEI_DEBUG(arg)
+ #define PEI_DEBUG_CODE(code)
+ #define PEI_CR(Record, TYPE, Field, Signature) \
+ _CR(Record, TYPE, Field)
+ #define _PEI_DEBUG_SET_MEM(address, length, data)
+#endif
+
+#define ASSERT_PEI_ERROR(PeiST, status) PEI_ASSERT(PeiST, !EFI_ERROR(status))
+
+#ifdef EFI_DEBUG_CLEAR_MEMORY
+ #define PEI_DEBUG_SET_MEMORY(address,length) \
+ _PEI_DEBUG_SET_MEM(address, length, EFI_BAD_POINTER_AS_BYTE)
+#else
+ #define PEI_DEBUG_SET_MEMORY(address,length)
+#endif
+
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/Tiano.h b/EdkCompatibilityPkg/Foundation/Include/Tiano.h new file mode 100644 index 0000000000..55790c2eab --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/Tiano.h @@ -0,0 +1,56 @@ +/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ Tiano.h
+
+Abstract:
+
+ Tiano master include file.
+
+ This is the main include file for Tiano components.
+
+ Don't add include files to the list for convenience, only add things
+ that are architectural. Don't add Protocols or GUID include files here
+
+--*/
+
+#ifndef _TIANO_H_
+#define _TIANO_H_
+
+//
+// Check to make sure EFI_SPECIFICATION_VERSION and TIANO_RELEASE_VERSION are defined.
+//
+#if !defined(EFI_SPECIFICATION_VERSION)
+ #error EFI_SPECIFICATION_VERSION not defined
+#elif !defined(TIANO_RELEASE_VERSION)
+ #error TIANO_RELEASE_VERSION not defined
+#elif (TIANO_RELEASE_VERSION == 0)
+ #error TIANO_RELEASE_VERSION can not be zero
+#elif (EFI_SPECIFICATION_VERSION <= 0x00020000)
+ #define TIANO_EXTENSION_FLAG
+#endif
+
+#include "TianoCommon.h"
+#include "TianoApi.h"
+#include "EfiDebug.h"
+#include "TianoDevicePath.h"
+#include "EfiSpec.h"
+
+//
+// EFI Revision information
+//
+#define EFI_FIRMWARE_MAJOR_REVISION 0x1000
+#define EFI_FIRMWARE_MINOR_REVISION 1
+#define EFI_FIRMWARE_REVISION ((EFI_FIRMWARE_MAJOR_REVISION << 16) | (EFI_FIRMWARE_MINOR_REVISION))
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/TianoApi.h b/EdkCompatibilityPkg/Foundation/Include/TianoApi.h new file mode 100644 index 0000000000..da1ca7c912 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/TianoApi.h @@ -0,0 +1,46 @@ +/*++
+
+Copyright (c) 2004, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ TianoApi.h
+
+Abstract:
+
+ Tiano intrinsic definitions.
+
+
+--*/
+
+#ifndef _TIANO_API_H_
+#define _TIANO_API_H_
+
+#include "EfiApi.h"
+#include "TianoSpecApi.h"
+
+//
+// Pointer to internal runtime function
+//
+#define EFI_INTERNAL_FUNCTION 0x00000002
+
+//
+// Pointer to internal runtime pointer
+//
+#define EFI_INTERNAL_POINTER 0x00000004
+
+//
+// Pointer to internal runtime pointer
+//
+#define EFI_IPF_GP_POINTER 0x00000008
+
+#define EFI_TPL_DRIVER 6
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/TianoCommon.h b/EdkCompatibilityPkg/Foundation/Include/TianoCommon.h new file mode 100644 index 0000000000..c2a87c73dd --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/TianoCommon.h @@ -0,0 +1,51 @@ +/*++
+
+Copyright (c) 2004, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ TianoCommon.h
+
+Abstract:
+
+ Tiano specific common definitions besides EfiCommon.h
+
+--*/
+
+#ifndef _TIANO_COMMON_H_
+#define _TIANO_COMMON_H_
+
+#include "TianoBind.h"
+#include "TianoTypes.h"
+#include "EfiStdArg.h"
+#include "TianoError.h"
+#include "EfiStatusCode.h"
+#include "EfiCommon.h"
+
+//
+// Define macros for including Architectural Protocols and PPIs
+//
+#define EFI_ARCH_PROTOCOL_DEFINITION(a) EFI_STRINGIZE (ArchProtocol/a/a.h)
+#define EFI_PPI_DEFINITION(a) EFI_STRINGIZE (Ppi/a/a.h)
+
+//
+// These should be used to include protocols. If they are followed,
+// intelligent build tools can be created to check dependencies at build
+// time.
+//
+#define EFI_ARCH_PROTOCOL_PRODUCER(a) EFI_ARCH_PROTOCOL_DEFINITION (a)
+#define EFI_ARCH_PROTOCOL_CONSUMER(a) EFI_ARCH_PROTOCOL_DEFINITION (a)
+#define EFI_ARCH_PROTOCOL_DEPENDENCY(a) EFI_ARCH_PROTOCOL_DEFINITION (a)
+
+#define EFI_PPI_PRODUCER(a) EFI_PPI_DEFINITION (a)
+#define EFI_PPI_CONSUMER(a) EFI_PPI_DEFINITION (a)
+#define EFI_PPI_DEPENDENCY(a) EFI_PPI_DEFINITION (a)
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/TianoDevicePath.h b/EdkCompatibilityPkg/Foundation/Include/TianoDevicePath.h new file mode 100644 index 0000000000..445a075c13 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/TianoDevicePath.h @@ -0,0 +1,130 @@ +/*++
+
+Copyright (c) 2004, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ TianoDevicePath.h
+
+Abstract:
+
+ Tiano Device Path definitions
+
+--*/
+
+#ifndef _TIANO_DEVICE_PATH_H
+#define _TIANO_DEVICE_PATH_H
+
+#include "EfiDevicePath.h"
+#include "TianoSpecDevicePath.h"
+
+#pragma pack(1)
+
+typedef struct _USB_PORT_DEVICE_PATH {
+ ACPI_HID_DEVICE_PATH PciRootBridgeDevicePath;
+ PCI_DEVICE_PATH PciBusDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} USB_PORT_DEVICE_PATH;
+
+//
+// IDE
+//
+typedef struct _IDE_DEVICE_PATH {
+ ACPI_HID_DEVICE_PATH PciRootBridgeDevicePath;
+ PCI_DEVICE_PATH PciBusDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} IDE_DEVICE_PATH;
+
+//
+// RMC Connector
+//
+typedef struct _RMC_CONN_DEVICE_PATH {
+ ACPI_HID_DEVICE_PATH PciRootBridgeDevicePath;
+ PCI_DEVICE_PATH PciBridgeDevicePath;
+ PCI_DEVICE_PATH PciBusDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} RMC_CONN_DEVICE_PATH;
+
+//
+// RIDE
+//
+typedef struct _RIDE_DEVICE_PATH {
+ ACPI_HID_DEVICE_PATH PciRootBridgeDevicePath;
+ PCI_DEVICE_PATH PciBridgeDevicePath;
+ PCI_DEVICE_PATH PciBusDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} RIDE_DEVICE_PATH;
+
+//
+// Gigabit NIC
+//
+typedef struct _GB_NIC_DEVICE_PATH {
+ ACPI_HID_DEVICE_PATH PciRootBridgeDevicePath;
+ PCI_DEVICE_PATH PciBridgeDevicePath;
+ PCI_DEVICE_PATH PciXBridgeDevicePath;
+ PCI_DEVICE_PATH PciXBusDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} GB_NIC_DEVICE_PATH;
+
+//
+// P/S2 Connector
+//
+typedef struct _PS2_CONN_DEVICE_PATH {
+ ACPI_HID_DEVICE_PATH PciRootBridgeDevicePath;
+ PCI_DEVICE_PATH LpcBridgeDevicePath;
+ ACPI_HID_DEVICE_PATH LpcBusDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} PS2_CONN_DEVICE_PATH;
+
+//
+// Serial Port Connector
+//
+typedef struct _SERIAL_CONN_DEVICE_PATH {
+ ACPI_HID_DEVICE_PATH PciRootBridgeDevicePath;
+ PCI_DEVICE_PATH LpcBridgeDevicePath;
+ ACPI_HID_DEVICE_PATH LpcBusDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} SERIAL_CONN_DEVICE_PATH;
+
+//
+// Parallel Port Connector
+//
+typedef struct _PARALLEL_CONN_DEVICE_PATH {
+ ACPI_HID_DEVICE_PATH PciRootBridgeDevicePath;
+ PCI_DEVICE_PATH LpcBridgeDevicePath;
+ ACPI_HID_DEVICE_PATH LpcBusDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} PARALLEL_CONN_DEVICE_PATH;
+
+//
+// Floopy Connector
+//
+typedef struct _FLOOPY_CONN_DEVICE_PATH {
+ ACPI_HID_DEVICE_PATH PciRootBridgeDevicePath;
+ PCI_DEVICE_PATH LpcBridgeDevicePath;
+ ACPI_HID_DEVICE_PATH LpcBusDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} FLOOPY_CONN_DEVICE_PATH;
+
+typedef union _EFI_MISC_PORT_DEVICE_PATH {
+ USB_PORT_DEVICE_PATH UsbDevicePath;
+ IDE_DEVICE_PATH IdeDevicePath;
+ RMC_CONN_DEVICE_PATH RmcConnDevicePath;
+ RIDE_DEVICE_PATH RideDevicePath;
+ GB_NIC_DEVICE_PATH GbNicDevicePath;
+ PS2_CONN_DEVICE_PATH Ps2ConnDevicePath;
+ SERIAL_CONN_DEVICE_PATH SerialConnDevicePath;
+ PARALLEL_CONN_DEVICE_PATH ParallelConnDevicePath;
+ FLOOPY_CONN_DEVICE_PATH FloppyConnDevicePath;
+} EFI_MISC_PORT_DEVICE_PATH;
+
+#pragma pack()
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/TianoError.h b/EdkCompatibilityPkg/Foundation/Include/TianoError.h new file mode 100644 index 0000000000..93cccf7ea9 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/TianoError.h @@ -0,0 +1,30 @@ +/*++
+
+Copyright (c) 2004, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ TianoError.h
+
+Abstract:
+
+ Tiano error levels and their associated defines
+
+--*/
+
+#ifndef _TIANO_ERROR_H_
+#define _TIANO_ERROR_H_
+
+#include "EfiError.h"
+#include "TianoSpecError.h"
+
+#define EFI_WARN_RETURN_FROM_LONG_JUMP EFIWARN (5)
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/TianoTypes.h b/EdkCompatibilityPkg/Foundation/Include/TianoTypes.h new file mode 100644 index 0000000000..de52e4fde8 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/TianoTypes.h @@ -0,0 +1,48 @@ +/*++
+
+Copyright (c) 2004, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ TianoTypes.h
+
+Abstract:
+
+ Tiano specific part besides EfiTypes.h
+
+--*/
+
+#ifndef _TIANO_TYPES_H_
+#define _TIANO_TYPES_H_
+
+#include "EfiTypes.h"
+#include "TianoSpecTypes.h"
+
+//
+// attributes for reserved memory before it is promoted to system memory
+//
+#define EFI_MEMORY_PRESENT 0x0100000000000000
+#define EFI_MEMORY_INITIALIZED 0x0200000000000000
+#define EFI_MEMORY_TESTED 0x0400000000000000
+
+//
+// range for memory mapped port I/O on IPF
+//
+#define EFI_MEMORY_PORT_IO 0x4000000000000000
+
+//
+// A pointer to a function in IPF points to a plabel.
+//
+typedef struct {
+ UINT64 EntryPoint;
+ UINT64 GP;
+} EFI_PLABEL;
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/x64/EfiBind.h b/EdkCompatibilityPkg/Foundation/Include/x64/EfiBind.h new file mode 100644 index 0000000000..2b51b66948 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/x64/EfiBind.h @@ -0,0 +1,222 @@ +/*++
+
+Copyright (c) 2005 - 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ EfiBind.h
+
+Abstract:
+
+ Processor or Compiler specific defines and types for x64.
+ We are using the ANSI C 2000 _t type definitions for basic types.
+ This it technically a violation of the coding standard, but they
+ are used to make EfiTypes.h portable. Code other than EfiTypes.h
+ should never use any ANSI C 2000 _t integer types.
+
+--*/
+
+#ifndef _EFI_BIND_H_
+#define _EFI_BIND_H_
+
+
+#define EFI_DRIVER_ENTRY_POINT(InitFunction)
+#define EFI_APPLICATION_ENTRY_POINT EFI_DRIVER_ENTRY_POINT
+
+
+
+//
+// Make sure we are useing the correct packing rules per EFI specification
+//
+#pragma pack()
+
+#if _MSC_EXTENSIONS
+
+//
+// Disable warning that make it impossible to compile at /W4
+// This only works for Microsoft* tools
+//
+
+//
+// Disabling bitfield type checking warnings.
+//
+#pragma warning ( disable : 4214 )
+
+//
+// Disabling the unreferenced formal parameter warnings.
+//
+#pragma warning ( disable : 4100 )
+
+//
+// Disable slightly different base types warning as CHAR8 * can not be set
+// to a constant string.
+//
+#pragma warning ( disable : 4057 )
+
+//
+// ASSERT(FALSE) or while (TRUE) are legal constructes so supress this warning
+//
+#pragma warning ( disable : 4127 )
+
+//
+// Int64ShllMod32 unreferenced inline function
+//
+#pragma warning ( disable : 4514 )
+
+//
+// Unreferenced formal parameter - We are object oriented, so we pass This even
+// if we don't need them.
+//
+#pragma warning ( disable : 4100 )
+
+//
+// This warning is caused by empty (after preprocessing) souce file.
+//
+#pragma warning ( disable : 4206 )
+
+//
+// Warning: The result of the unary '&' operator may be unaligned. Ignore it.
+//
+#pragma warning ( disable : 4366 )
+
+#endif
+
+
+#if (__STDC_VERSION__ < 199901L)
+ //
+ // No ANSI C 2000 stdint.h integer width declarations, so define equivalents
+ //
+
+ #if _MSC_EXTENSIONS
+
+ //
+ // use Microsoft* C complier dependent interger width types
+ //
+ typedef unsigned __int64 uint64_t;
+ typedef __int64 int64_t;
+ typedef unsigned __int32 uint32_t;
+ typedef __int32 int32_t;
+ typedef unsigned short uint16_t;
+ typedef short int16_t;
+ typedef unsigned char uint8_t;
+ typedef char int8_t;
+ #else
+
+ //
+ // Assume standard IA-32 alignment.
+ // BugBug: Need to check portability of long long
+ //
+ typedef unsigned long long uint64_t;
+ typedef long long int64_t;
+ typedef unsigned int uint32_t;
+ typedef int int32_t;
+ typedef unsigned short uint16_t;
+ typedef short int16_t;
+ typedef unsigned char uint8_t;
+ typedef char int8_t;
+ #endif
+#else
+ //
+ // Use ANSI C 2000 stdint.h integer width declarations
+ //
+ #include "stdint.h"
+#endif
+
+//
+// Native integer size in stdint.h
+//
+typedef uint64_t uintn_t;
+typedef int64_t intn_t;
+
+//
+// Processor specific defines
+//
+#define EFI_MAX_BIT 0x8000000000000000
+#define MAX_2_BITS 0xC000000000000000
+
+//
+// Maximum legal IA-32 address
+//
+#define EFI_MAX_ADDRESS 0xFFFFFFFFFFFFFFFF
+
+//
+// Bad pointer value to use in check builds.
+// if you see this value you are using uninitialized or free'ed data
+//
+#define EFI_BAD_POINTER 0xAFAFAFAFAFAFAFAF
+#define EFI_BAD_POINTER_AS_BYTE 0xAF
+
+//
+// Inject a break point in the code to assist debugging.
+//
+#define EFI_DEADLOOP() { volatile int __iii; __iii = 1; while (__iii); }
+#define EFI_BREAKPOINT() __debugbreak()
+
+//
+// Memory Fence forces serialization, and is needed to support out of order
+// memory transactions. The Memory Fence is mainly used to make sure IO
+// transactions complete in a deterministic sequence, and to syncronize locks
+// an other MP code. Currently no memory fencing is required.
+//
+#define MEMORY_FENCE()
+
+//
+// Some compilers don't support the forward reference construct:
+// typedef struct XXXXX. The forward reference is required for
+// ANSI compatibility.
+//
+// The following macro provide a workaround for such cases.
+//
+
+
+#ifdef EFI_NO_INTERFACE_DECL
+ #define EFI_FORWARD_DECLARATION(x)
+#else
+ #define EFI_FORWARD_DECLARATION(x) typedef struct _##x x
+#endif
+
+
+//
+// Some C compilers optimize the calling conventions to increase performance.
+// _EFIAPI is used to make all public APIs follow the standard C calling
+// convention.
+//
+#if _MSC_EXTENSIONS
+ //
+ // Microsoft* compiler requires _EFIAPI useage, __cdecl is Microsoft* specific C.
+ //
+
+ #define _EFIAPI __cdecl
+#else
+ #define _EFIAPI
+#endif
+
+
+#ifdef _EFI_WINNT
+
+ #define EFI_SUPPRESS_BENIGN_REDEFINITION_OF_TYPE_WARNING() \
+ warning ( disable : 4142 )
+
+ #define EFI_DEFAULT_BENIGN_REDEFINITION_OF_TYPE_WARNING() \
+ warning ( default : 4142 )
+#else
+
+ #define EFI_SUPPRESS_BENIGN_REDEFINITION_OF_TYPE_WARNING() \
+ warning ( disable : 4068 )
+
+ #define EFI_DEFAULT_BENIGN_REDEFINITION_OF_TYPE_WARNING() \
+ warning ( default : 4068 )
+
+#endif
+
+
+
+#endif
+
diff --git a/EdkCompatibilityPkg/Foundation/Include/x64/EfiPeOptionalHeader.h b/EdkCompatibilityPkg/Foundation/Include/x64/EfiPeOptionalHeader.h new file mode 100644 index 0000000000..03d1dc2957 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/x64/EfiPeOptionalHeader.h @@ -0,0 +1,42 @@ +/*++
+
+Copyright (c) 2005 - 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ EfiPeOptionalHeader.h
+
+Abstract:
+ Defines the optional header in the PE image per the PE specification. This
+ file must be included only from within EfiImage.h since
+ EFI_IMAGE_DATA_DIRECTORY and EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES are defined
+ there.
+
+--*/
+
+#ifndef _EFI_PE_OPTIONAL_HEADER_H_
+#define _EFI_PE_OPTIONAL_HEADER_H_
+
+#define EFI_IMAGE_MACHINE_TYPE (EFI_IMAGE_MACHINE_X64)
+
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
+ (((Machine) == EFI_IMAGE_MACHINE_X64) || ((Machine) == EFI_IMAGE_MACHINE_EBC))
+
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_IA32)
+
+//
+// Assume we can use IPF values
+//
+#define EFI_IMAGE_NT_OPTIONAL_HDR_MAGIC EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC
+typedef EFI_IMAGE_OPTIONAL_HEADER64 EFI_IMAGE_OPTIONAL_HEADER;
+typedef EFI_IMAGE_NT_HEADERS64 EFI_IMAGE_NT_HEADERS;
+
+#endif
+
diff --git a/EdkCompatibilityPkg/Foundation/Include/x64/TianoBind.h b/EdkCompatibilityPkg/Foundation/Include/x64/TianoBind.h new file mode 100644 index 0000000000..45fe2119ac --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/x64/TianoBind.h @@ -0,0 +1,30 @@ +/*++
+
+Copyright (c) 2005, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ TianoBind.h
+
+Abstract:
+
+ Tiano's Processor or Compiler specific defines and types for Intel?Itanium(TM)
+ besides EfiBind.h.
+
+--*/
+
+#ifndef _TIANO_BIND_H_
+#define _TIANO_BIND_H_
+
+#include "EfiBind.h"
+
+#define EFI_DXE_ENTRY_POINT(InitFunction)
+
+#endif
|