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authorhfang <hfang@6f19259b-4bc3-4df7-8a09-765794883524>2009-01-13 07:28:52 +0000
committerhfang <hfang@6f19259b-4bc3-4df7-8a09-765794883524>2009-01-13 07:28:52 +0000
commit5326528b2f74b3b737c6bafb6d87d98c11947006 (patch)
treea14b7f64a6c97aa1561911085dd77dcf35885f5a /IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe
parent46231010bd25ce55917c4bfc88a3d445596a1b1d (diff)
downloadedk2-platforms-5326528b2f74b3b737c6bafb6d87d98c11947006.tar.xz
Fixed For Review
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@7253 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe')
-rw-r--r--IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/Ata.c4
-rw-r--r--IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeData.h6
2 files changed, 5 insertions, 5 deletions
diff --git a/IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/Ata.c b/IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/Ata.c
index a91eb174c1..4a57f11bfe 100644
--- a/IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/Ata.c
+++ b/IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/Ata.c
@@ -2493,9 +2493,9 @@ DoAtaUdma (
);
if (UdmaOp == AtaUdmaReadExtOp || UdmaOp == AtaUdmaReadOp) {
- RegisterValue |= BMIC_nREAD;
+ RegisterValue |= BMIC_NREAD;
} else {
- RegisterValue &= ~((UINT8) BMIC_nREAD);
+ RegisterValue &= ~((UINT8) BMIC_NREAD);
}
IdeDev->PciIo->Io.Write (
diff --git a/IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeData.h b/IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeData.h
index e4bc4f71fd..47385c71a4 100644
--- a/IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeData.h
+++ b/IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeData.h
@@ -75,7 +75,7 @@ typedef union {
typedef union {
UINT16 AltStatus; /* when read */
UINT16 DeviceControl; /* when write */
-} IDE_AltStatus_OR_DeviceControl;
+} IDE_ALTSTATUS_OR_DEVICECONTROL;
//
// IDE registers set
@@ -90,7 +90,7 @@ typedef struct {
UINT16 Head;
IDE_CMD_OR_STATUS Reg;
- IDE_AltStatus_OR_DeviceControl Alt;
+ IDE_ALTSTATUS_OR_DEVICECONTROL Alt;
UINT16 DriveAddress;
UINT16 MasterSlave;
@@ -119,7 +119,7 @@ typedef struct {
//
// Bus Master Reg
//
-#define BMIC_nREAD BIT3
+#define BMIC_NREAD BIT3
#define BMIC_START BIT0
#define BMIS_INTERRUPT BIT2
#define BMIS_ERROR BIT1