diff options
| author | htao <htao@6f19259b-4bc3-4df7-8a09-765794883524> | 2009-09-16 09:32:06 +0000 |
|---|---|---|
| committer | htao <htao@6f19259b-4bc3-4df7-8a09-765794883524> | 2009-09-16 09:32:06 +0000 |
| commit | 7fc72ecb0d6db6699d9b3e2d3c7b059eb1b53a14 (patch) | |
| tree | 5507b5dd68e6ba4abfa685a52cef6e95a9df90ce /IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.c | |
| parent | fd53905e69bb94a5175125a32ffbaa9cae718cef (diff) | |
| download | edk2-platforms-7fc72ecb0d6db6699d9b3e2d3c7b059eb1b53a14.tar.xz | |
add SR-IOV support in EDK II.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9269 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.c')
| -rw-r--r-- | IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.c | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.c index 39f5271e9b..601af309b7 100644 --- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.c +++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.c @@ -179,3 +179,70 @@ LocateCapabilityRegBlock ( return EFI_NOT_FOUND;
}
+/**
+ Locate PciExpress capability register block per capability ID.
+
+ @param PciIoDevice A pointer to the PCI_IO_DEVICE.
+ @param CapId The capability ID.
+ @param Offset A pointer to the offset returned.
+ @param NextRegBlock A pointer to the next block returned.
+
+ @retval EFI_SUCCESS Successfuly located capability register block.
+ @retval EFI_UNSUPPORTED Pci device does not support capability.
+ @retval EFI_NOT_FOUND Pci device support but can not find register block.
+
+**/
+EFI_STATUS
+LocatePciExpressCapabilityRegBlock (
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINT16 CapId,
+ IN OUT UINT32 *Offset,
+ OUT UINT32 *NextRegBlock OPTIONAL
+ )
+{
+ UINT32 CapabilityPtr;
+ UINT32 CapabilityEntry;
+ UINT16 CapabilityID;
+
+ //
+ // To check the capability of this device supports
+ //
+ if (!PciIoDevice->IsPciExp) {
+ return EFI_UNSUPPORTED;
+ }
+
+ if (*Offset != 0) {
+ CapabilityPtr = *Offset;
+ } else {
+ CapabilityPtr = EFI_PCIE_CAPABILITY_BASE_OFFSET;
+ }
+
+ while (CapabilityPtr != 0) {
+ //
+ // Mask it to DWORD alignment per PCI spec
+ //
+ CapabilityPtr &= 0xFFC;
+ PciIoDevice->PciIo.Pci.Read (
+ &PciIoDevice->PciIo,
+ EfiPciIoWidthUint32,
+ CapabilityPtr,
+ 1,
+ &CapabilityEntry
+ );
+
+ CapabilityID = (UINT16) CapabilityEntry;
+
+ if (CapabilityID == CapId) {
+ *Offset = CapabilityPtr;
+ if (NextRegBlock != NULL) {
+ *NextRegBlock = (CapabilityEntry >> 20) & 0xFFF;
+ }
+
+ return EFI_SUCCESS;
+ }
+
+ CapabilityPtr = (CapabilityEntry >> 20) & 0xFFF;
+ }
+
+ return EFI_NOT_FOUND;
+}
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