1. used PciPlatfromProtocolGuid to get VgaIo and IsaIo supported capability.

2. Fixed ECC issues.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8591 6f19259b-4bc3-4df7-8a09-765794883524

6 files changed, 150 insertions, 69 deletions

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
index 101bce18d5..6808cfd53c 100644
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
@@ -100,11 +100,9 @@
   gEfiLoadFile2ProtocolGuid						          # SOMETIMES_CONSUMED

 

 [FeaturePcd.common]

-  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciVgaEnable

   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport

-  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciIsaEnable

 

-[FixedPcd.common]

+[Pcd.common]

   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciIncompatibleDeviceSupportMask

 

 

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.h b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.h
index c69f05b53d..73c8c2cb77 100644
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.h
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.h
@@ -1,6 +1,6 @@
 /** @file

 

-Copyright (c) 2006, Intel Corporation                                                         

+Copyright (c) 2006 - 2009, Intel Corporation                                                         

 All rights reserved. This program and the accompanying materials                          

 are licensed and made available under the terms and conditions of the BSD License         

 which accompanies this distribution.  The full text of the license may be found at        

@@ -114,29 +114,100 @@ LocateCapabilityRegBlock (
   OUT UINT8         *NextRegBlock OPTIONAL

   );

 

+/**  

+  Macro that reads command register.

 

-#define PciReadCommandRegister(a,b) \

-        PciOperateRegister (a,0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)

-

-#define PciSetCommandRegister(a,b) \

-        PciOperateRegister (a,b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)

-        

-#define PciEnableCommandRegister(a,b) \

-        PciOperateRegister (a,b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)

-        

-#define PciDisableCommandRegister(a,b) \

-        PciOperateRegister (a,b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)

-

-#define PciReadBridgeControlRegister(a,b) \

-        PciOperateRegister (a,0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)

-        

-#define PciSetBridgeControlRegister(a,b) \

-        PciOperateRegister (a,b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)

-

-#define PciEnableBridgeControlRegister(a,b) \

-        PciOperateRegister (a,b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)

-        

-#define PciDisableBridgeControlRegister(a,b) \

-        PciOperateRegister (a,b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)

+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.

+  @param b[out]           Pointer to the 16-bit value read from command register.

+  

+  @return status of PciIo operation

+

+**/

+#define PCI_READ_COMMAND_REGISTER(a,b) \

+        PciOperateRegister (a, 0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)

+

+/**  

+  Macro that writes command register.

+

+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.

+  @param b[in]            The 16-bit value written into command register.

+  

+  @return status of PciIo operation

+

+**/

+#define PCI_SET_COMMAND_REGISTER(a,b) \

+        PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)

+

+/**  

+  Macro that enables command register.

+

+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.

+  @param b[in]            The enabled value written into command register.

+  

+  @return status of PciIo operation

+

+**/        

+#define PCI_ENABLE_COMMAND_REGISTER(a,b) \

+        PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)

+

+/**  

+  Macro that disalbes command register.

+

+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.

+  @param b[in]            The disabled value written into command register.

+  

+  @return status of PciIo operation

+

+**/        

+#define PCI_DISABLE_COMMAND_REGISTER(a,b) \

+        PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)

+

+/**  

+  Macro that reads PCI bridge control register.

+

+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.

+  @param b[out]           The 16-bit value read from control register.

+  

+  @return status of PciIo operation

+

+**/

+#define PCI_READ_BRIDGE_CONTROL_REGISTER(a,b) \

+        PciOperateRegister (a, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)

+

+/**  

+  Macro that writes PCI bridge control register.

+

+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.

+  @param b[in]            The 16-bit value written into control register.

+  

+  @return status of PciIo operation

+

+**/        

+#define PCI_SET_BRIDGE_CONTROL_REGISTER(a,b) \

+        PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)

+

+/**  

+  Macro that enables PCI bridge control register.

+

+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.

+  @param b[in]            The enabled value written into command register.

+  

+  @return status of PciIo operation

+

+**/

+#define PCI_ENABLE_BRIDGE_CONTROL_REGISTER(a,b) \

+        PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)

+

+/**  

+ Macro that disalbes PCI bridge control register.

+

+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.

+  @param b[in]            The disabled value written into command register.

+  

+  @return status of PciIo operation

+

+**/        

+#define PCI_DISABLE_BRIDGE_CONTROL_REGISTER(a,b) \

+        PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)

 

 #endif

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
index a75460fa97..08c785a23b 100644
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
@@ -355,7 +355,7 @@ GatherDeviceInfo (
   //

   if (gFullEnumeration) {

 

-    PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);

+    PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);

 

   }

 

@@ -418,12 +418,12 @@ GatherPpbInfo (
     );

 

   if (gFullEnumeration) {

-    PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);

+    PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);

 

     //

     // Initalize the bridge control register

     //

-    PciDisableBridgeControlRegister (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED);

+    PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED);

 

   }

 

@@ -537,12 +537,12 @@ GatherP2CInfo (
     );

 

   if (gFullEnumeration) {

-    PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);

+    PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);

 

     //

     // Initalize the bridge control register

     //

-    PciDisableBridgeControlRegister (PciIoDevice, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED);

+    PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED);

 

   }

   //

@@ -684,20 +684,20 @@ PciTestSupportedAttribute (
   //

   // Preserve the original value

   //

-  PciReadCommandRegister (PciIoDevice, OldCommand);

+  PCI_READ_COMMAND_REGISTER (PciIoDevice, OldCommand);

 

   //

   // Raise TPL to high level to disable timer interrupt while the BAR is probed

   //

   OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);

 

-  PciSetCommandRegister (PciIoDevice, *Command);

-  PciReadCommandRegister (PciIoDevice, Command);

+  PCI_SET_COMMAND_REGISTER (PciIoDevice, *Command);

+  PCI_READ_COMMAND_REGISTER (PciIoDevice, Command);

 

   //

   // Write back the original value

   //

-  PciSetCommandRegister (PciIoDevice, *OldCommand);

+  PCI_SET_COMMAND_REGISTER (PciIoDevice, *OldCommand);

 

   //

   // Restore TPL to its original level

@@ -709,20 +709,20 @@ PciTestSupportedAttribute (
     //

     // Preserve the original value

     //

-    PciReadBridgeControlRegister (PciIoDevice, OldBridgeControl);

+    PCI_READ_BRIDGE_CONTROL_REGISTER (PciIoDevice, OldBridgeControl);

 

     //

     // Raise TPL to high level to disable timer interrupt while the BAR is probed

     //

     OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);

 

-    PciSetBridgeControlRegister (PciIoDevice, *BridgeControl);

-    PciReadBridgeControlRegister (PciIoDevice, BridgeControl);

+    PCI_SET_BRIDGE_CONTROL_REGISTER (PciIoDevice, *BridgeControl);

+    PCI_READ_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);

 

     //

     // Write back the original value

     //

-    PciSetBridgeControlRegister (PciIoDevice, *OldBridgeControl);

+    PCI_SET_BRIDGE_CONTROL_REGISTER (PciIoDevice, *OldBridgeControl);

 

     //

     // Restore TPL to its original level

@@ -981,7 +981,7 @@ DetermineDeviceAttribute (
     //

     // Enable other supported attributes but not defined in PCI_IO_PROTOCOL

     //

-    PciEnableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE);

+    PCI_ENABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE);

 

     //

     // Enable IDE native mode

@@ -1057,9 +1057,9 @@ DetermineDeviceAttribute (
 

       if (EFI_ERROR (Status) || (!FastB2BSupport)) {

         FastB2BSupport = FALSE;

-        PciDisableBridgeControlRegister (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK);

+        PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK);

       } else {

-        PciEnableBridgeControlRegister (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK);

+        PCI_ENABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK);

       }

     }

 

@@ -1067,9 +1067,9 @@ DetermineDeviceAttribute (
     while (CurrentLink != NULL && CurrentLink != &PciIoDevice->ChildList) {

       Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);

       if (FastB2BSupport) {

-        PciEnableCommandRegister (Temp, EFI_PCI_COMMAND_FAST_BACK_TO_BACK);

+        PCI_ENABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_FAST_BACK_TO_BACK);

       } else {

-        PciDisableCommandRegister (Temp, EFI_PCI_COMMAND_FAST_BACK_TO_BACK);

+        PCI_DISABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_FAST_BACK_TO_BACK);

       }

 

       CurrentLink = CurrentLink->ForwardLink;

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciIo.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciIo.c
index 7975505328..f2cc373b98 100644
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciIo.c
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciIo.c
@@ -1230,7 +1230,7 @@ SupportPaletteSnoopAttributes (
   //

   if (Temp->Parent == PciIoDevice->Parent) {

 

-    PciReadCommandRegister (Temp, &VGACommand);

+    PCI_READ_COMMAND_REGISTER (Temp, &VGACommand);

 

     //

     // If they are on the same bus, either one can

@@ -1266,7 +1266,7 @@ SupportPaletteSnoopAttributes (
     // GFX should be set to decode

     //

     if (Operation == EfiPciIoAttributeOperationDisable) {

-      PciEnableCommandRegister (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);

+      PCI_ENABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);

       Temp->Attributes |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;

     } else {

       return EFI_UNSUPPORTED;

@@ -1277,7 +1277,7 @@ SupportPaletteSnoopAttributes (
     // GFX should be set to snoop

     //

     if (Operation == EfiPciIoAttributeOperationEnable) {

-      PciDisableCommandRegister (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);

+      PCI_DISABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);

       Temp->Attributes &= (~EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);

     } else {

       return EFI_UNSUPPORTED;

@@ -1536,9 +1536,9 @@ PciIoAttributes (
     //

     // Enable relevant attributes to command register and bridge control register

     //

-    Status = PciEnableCommandRegister (PciIoDevice, Command);

+    Status = PCI_ENABLE_COMMAND_REGISTER (PciIoDevice, Command);

     if (BridgeControl != 0) {

-      Status = PciEnableBridgeControlRegister (PciIoDevice, BridgeControl);

+      Status = PCI_ENABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);

     }

 

     PciIoDevice->Attributes |= Attributes;

@@ -1557,9 +1557,9 @@ PciIoAttributes (
     //

     // Disable relevant attributes to command register and bridge control register

     //

-    Status = PciDisableCommandRegister (PciIoDevice, Command);

+    Status = PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, Command);

     if (BridgeControl != 0) {

-      Status = PciDisableBridgeControlRegister (PciIoDevice, BridgeControl);

+      Status = PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);

     }

 

     PciIoDevice->Attributes &= (~Attributes);

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
index a674cadea0..f81bb92e3f 100644
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
@@ -595,14 +595,14 @@ RomDecode (
     //

     // Setting the memory space bit in the function's command register

     //

-    PciEnableCommandRegister(PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);

+    PCI_ENABLE_COMMAND_REGISTER(PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);

 

   } else {

 

     //

     // disable command register decode to memory

     //

-    PciDisableCommandRegister(PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);

+    PCI_DISABLE_COMMAND_REGISTER(PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);

 

     //

     // Destroy the programmed bar in all the upstream bridge.

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
index e7e40012c3..da0cfa0cae 100644
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
@@ -196,13 +196,15 @@ CalculateApertureIo16 (
   IN PCI_RESOURCE_NODE *Bridge

   )

 {

-

-  UINT64            Aperture;

-  LIST_ENTRY        *CurrentLink;

-  PCI_RESOURCE_NODE *Node;

-  UINT64            Offset;

-  BOOLEAN           IsaEnable;

-  BOOLEAN           VGAEnable;

+  EFI_STATUS              Status;

+  UINT64                  Aperture;

+  LIST_ENTRY              *CurrentLink;

+  PCI_RESOURCE_NODE       *Node;

+  UINT64                  Offset;

+  BOOLEAN                 IsaEnable;

+  BOOLEAN                 VGAEnable;

+  EFI_PCI_PLATFORM_POLICY PciPolicy;

+  

 

   //

   // Always assume there is ISA device and VGA device on the platform

@@ -211,12 +213,22 @@ CalculateApertureIo16 (
   IsaEnable = FALSE;

   VGAEnable = FALSE;

 

-  if (FeaturePcdGet (PcdPciIsaEnable)){

-    IsaEnable = TRUE;

-  }

-

-  if (FeaturePcdGet (PcdPciVgaEnable)){

-    VGAEnable = TRUE;

+  //

+  // Check PciPlatform policy

+  //

+  if (gPciPlatformProtocol != NULL) {

+    Status = gPciPlatformProtocol->GetPlatformPolicy (

+                                     gPciPlatformProtocol,

+                                     &PciPolicy

+                                     );

+    if (!EFI_ERROR (Status)) {

+      if (PciPolicy & EFI_RESERVE_ISA_IO_ALIAS) {

+        IsaEnable = TRUE;

+      }

+      if (PciPolicy & EFI_RESERVE_VGA_IO_ALIAS) {

+        VGAEnable = TRUE;

+      }

+    }

   }

 

   Aperture = 0;

@@ -1386,10 +1398,10 @@ ProgrameUpstreamBridgeForRom (
     //

     if (Enable) {

       ProgramPpbApperture (OptionRomBase, &Node);

-      PciEnableCommandRegister (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);

+      PCI_ENABLE_COMMAND_REGISTER (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);

     } else {

       InitializePpb (Parent);

-      PciDisableCommandRegister (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);

+      PCI_DISABLE_COMMAND_REGISTER (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);

     }

 

     Parent = Parent->Parent;