diff options
| author | yshang1 <yshang1@6f19259b-4bc3-4df7-8a09-765794883524> | 2007-07-02 09:09:00 +0000 |
|---|---|---|
| committer | yshang1 <yshang1@6f19259b-4bc3-4df7-8a09-765794883524> | 2007-07-02 09:09:00 +0000 |
| commit | c3902377a94850795450186d9b4b2bc3007d83be (patch) | |
| tree | adc8ff784a17f85918611259a0242679d1803d30 /IntelFrameworkModulePkg/Include | |
| parent | 92627141817c5f794db66c8937c7453bbff4c302 (diff) | |
| download | edk2-platforms-c3902377a94850795450186d9b4b2bc3007d83be.tar.xz | |
Add DxeBootScriptLibNull in IntelFrameworkPkg.
Add IsaBusDxe in IntelFrameworkModulePkg.
Add Pcat.h in "IntelFrameworkModulePkg/IndustryStandard"
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@2948 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'IntelFrameworkModulePkg/Include')
| -rw-r--r-- | IntelFrameworkModulePkg/Include/IndustryStandard/Pcat.h | 105 | ||||
| -rw-r--r-- | IntelFrameworkModulePkg/Include/Protocol/IsaIo.h | 177 |
2 files changed, 282 insertions, 0 deletions
diff --git a/IntelFrameworkModulePkg/Include/IndustryStandard/Pcat.h b/IntelFrameworkModulePkg/Include/IndustryStandard/Pcat.h new file mode 100644 index 0000000000..480d6c470d --- /dev/null +++ b/IntelFrameworkModulePkg/Include/IndustryStandard/Pcat.h @@ -0,0 +1,105 @@ +/** @file
+ Include file for PC-AT compatability.
+
+Copyright (c) 2006, Intel Corporation. All rights reserved.
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+**/
+
+#ifndef _PC_AT_H_
+#define _PC_AT_H_
+
+//
+// 8254 Timer
+//
+#define TIMER0_COUNT_PORT 0x40
+#define TIMER1_COUNT_PORT 0x41
+#define TIMER2_COUNT_PORT 0x42
+#define TIMER_CONTROL_PORT 0x43
+
+//
+// 8259 PIC interrupt controller
+//
+
+#define PIC_CONTROL_REGISTER_MASTER 0x20
+#define PIC_MASK_REGISTER_MASTER 0x21
+#define PIC_CONTROL_REGISTER_SLAVE 0xA0
+#define PIC_MASK_REGISTER_SLAVE 0xA1
+#define PIC_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4D0
+#define PIC_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1
+
+#define PIC_EOI 0x20
+
+//
+// 8237 DMA registers
+//
+#define R_8237_DMA_BASE_CA_CH0 0x00
+#define R_8237_DMA_BASE_CA_CH1 0x02
+#define R_8237_DMA_BASE_CA_CH2 0x04
+#define R_8237_DMA_BASE_CA_CH3 0xd6
+#define R_8237_DMA_BASE_CA_CH5 0xc4
+#define R_8237_DMA_BASE_CA_CH6 0xc8
+#define R_8237_DMA_BASE_CA_CH7 0xcc
+
+#define R_8237_DMA_BASE_CC_CH0 0x01
+#define R_8237_DMA_BASE_CC_CH1 0x03
+#define R_8237_DMA_BASE_CC_CH2 0x05
+#define R_8237_DMA_BASE_CC_CH3 0xd7
+#define R_8237_DMA_BASE_CC_CH5 0xc6
+#define R_8237_DMA_BASE_CC_CH6 0xca
+#define R_8237_DMA_BASE_CC_CH7 0xce
+
+#define R_8237_DMA_MEM_LP_CH0 0x87
+#define R_8237_DMA_MEM_LP_CH1 0x83
+#define R_8237_DMA_MEM_LP_CH2 0x81
+#define R_8237_DMA_MEM_LP_CH3 0x82
+#define R_8237_DMA_MEM_LP_CH5 0x8B
+#define R_8237_DMA_MEM_LP_CH6 0x89
+#define R_8237_DMA_MEM_LP_CH7 0x8A
+
+
+#define R_8237_DMA_COMMAND_CH0_3 0x08
+#define R_8237_DMA_COMMAND_CH4_7 0xd0
+#define B_8237_DMA_COMMAND_GAP 0x10
+#define B_8237_DMA_COMMAND_CGE 0x04
+
+
+#define R_8237_DMA_STA_CH0_3 0xd8
+#define R_8237_DMA_STA_CH4_7 0xd0
+
+#define R_8237_DMA_WRSMSK_CH0_3 0x0a
+#define R_8237_DMA_WRSMSK_CH4_7 0xd4
+#define B_8237_DMA_WRSMSK_CMS 0x04
+
+
+#define R_8237_DMA_CHMODE_CH0_3 0x0b
+#define R_8237_DMA_CHMODE_CH4_7 0xd6
+#define V_8237_DMA_CHMODE_DEMAND 0x00
+#define V_8237_DMA_CHMODE_SINGLE 0x40
+#define V_8237_DMA_CHMODE_CASCADE 0xc0
+#define B_8237_DMA_CHMODE_DECREMENT 0x20
+#define B_8237_DMA_CHMODE_INCREMENT 0x00
+#define B_8237_DMA_CHMODE_AE 0x10
+#define V_8237_DMA_CHMODE_VERIFY 0
+#define V_8237_DMA_CHMODE_IO2MEM 0x04
+#define V_8237_DMA_CHMODE_MEM2IO 0x08
+
+#define R_8237_DMA_CBPR_CH0_3 0x0c
+#define R_8237_DMA_CBPR_CH4_7 0xd8
+
+#define R_8237_DMA_MCR_CH0_3 0x0d
+#define R_8237_DMA_MCR_CH4_7 0xda
+
+#define R_8237_DMA_CLMSK_CH0_3 0x0e
+#define R_8237_DMA_CLMSK_CH4_7 0xdc
+
+#define R_8237_DMA_WRMSK_CH0_3 0x0f
+#define R_8237_DMA_WRMSK_CH4_7 0xde
+
+#endif
diff --git a/IntelFrameworkModulePkg/Include/Protocol/IsaIo.h b/IntelFrameworkModulePkg/Include/Protocol/IsaIo.h new file mode 100644 index 0000000000..09ac260572 --- /dev/null +++ b/IntelFrameworkModulePkg/Include/Protocol/IsaIo.h @@ -0,0 +1,177 @@ +/*++
+
+Copyright (c) 2006 - 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ IsaIo.h
+
+Abstract:
+
+ EFI ISA I/O Protocol
+
+Revision History
+
+--*/
+
+#ifndef _EFI_ISA_IO_H
+#define _EFI_ISA_IO_H
+
+
+#include <Protocol/IsaAcpi.h>
+
+//
+// Global ID for the ISA I/O Protocol
+//
+
+#define EFI_ISA_IO_PROTOCOL_GUID \
+ { 0x7ee2bd44, 0x3da0, 0x11d4, { 0x9a, 0x38, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } }
+
+typedef struct _EFI_ISA_IO_PROTOCOL EFI_ISA_IO_PROTOCOL;
+
+//
+// Prototypes for the ISA I/O Protocol
+//
+
+typedef enum {
+ EfiIsaIoWidthUint8,
+ EfiIsaIoWidthUint16,
+ EfiIsaIoWidthUint32,
+ EfiIsaIoWidthReserved,
+ EfiIsaIoWidthFifoUint8,
+ EfiIsaIoWidthFifoUint16,
+ EfiIsaIoWidthFifoUint32,
+ EfiIsaIoWidthFifoReserved,
+ EfiIsaIoWidthFillUint8,
+ EfiIsaIoWidthFillUint16,
+ EfiIsaIoWidthFillUint32,
+ EfiIsaIoWidthFillReserved,
+ EfiIsaIoWidthMaximum
+} EFI_ISA_IO_PROTOCOL_WIDTH;
+
+//
+// Attributes for common buffer allocations
+//
+#define EFI_ISA_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x080 // Map a memory range so write are combined
+#define EFI_ISA_IO_ATTRIBUTE_MEMORY_CACHED 0x800 // Map a memory range so all r/w accesses are cached
+#define EFI_ISA_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 // Disable a memory range
+
+//
+// Channel attribute for DMA operations
+//
+#define EFI_ISA_IO_SLAVE_DMA_ATTRIBUTE_SPEED_COMPATIBLE 0x001
+#define EFI_ISA_IO_SLAVE_DMA_ATTRIBUTE_SPEED_A 0x002
+#define EFI_ISA_IO_SLAVE_DMA_ATTRIBUTE_SPEED_B 0x004
+#define EFI_ISA_IO_SLAVE_DMA_ATTRIBUTE_SPEED_C 0x008
+#define EFI_ISA_IO_SLAVE_DMA_ATTRIBUTE_WIDTH_8 0x010
+#define EFI_ISA_IO_SLAVE_DMA_ATTRIBUTE_WIDTH_16 0x020
+#define EFI_ISA_IO_SLAVE_DMA_ATTRIBUTE_SINGLE_MODE 0x040
+#define EFI_ISA_IO_SLAVE_DMA_ATTRIBUTE_DEMAND_MODE 0x080
+#define EFI_ISA_IO_SLAVE_DMA_ATTRIBUTE_AUTO_INITIALIZE 0x100
+
+typedef enum {
+ EfiIsaIoOperationBusMasterRead,
+ EfiIsaIoOperationBusMasterWrite,
+ EfiIsaIoOperationBusMasterCommonBuffer,
+ EfiIsaIoOperationSlaveRead,
+ EfiIsaIoOperationSlaveWrite,
+ EfiIsaIoOperationMaximum
+} EFI_ISA_IO_PROTOCOL_OPERATION;
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ISA_IO_PROTOCOL_IO_MEM) (
+ IN EFI_ISA_IO_PROTOCOL *This,
+ IN EFI_ISA_IO_PROTOCOL_WIDTH Width,
+ IN UINT32 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+typedef struct {
+ EFI_ISA_IO_PROTOCOL_IO_MEM Read;
+ EFI_ISA_IO_PROTOCOL_IO_MEM Write;
+} EFI_ISA_IO_PROTOCOL_ACCESS;
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ISA_IO_PROTOCOL_COPY_MEM) (
+ IN EFI_ISA_IO_PROTOCOL *This,
+ IN EFI_ISA_IO_PROTOCOL_WIDTH Width,
+ IN UINT32 DestOffset,
+ IN UINT32 SrcOffset,
+ IN UINTN Count
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ISA_IO_PROTOCOL_MAP) (
+ IN EFI_ISA_IO_PROTOCOL *This,
+ IN EFI_ISA_IO_PROTOCOL_OPERATION Operation,
+ IN UINT8 ChannelNumber OPTIONAL,
+ IN UINT32 ChannelAttributes,
+ IN VOID *HostAddress,
+ IN OUT UINTN *NumberOfBytes,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ISA_IO_PROTOCOL_UNMAP) (
+ IN EFI_ISA_IO_PROTOCOL *This,
+ IN VOID *Mapping
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ISA_IO_PROTOCOL_ALLOCATE_BUFFER) (
+ IN EFI_ISA_IO_PROTOCOL *This,
+ IN EFI_ALLOCATE_TYPE Type,
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ OUT VOID **HostAddress,
+ IN UINT64 Attributes
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ISA_IO_PROTOCOL_FREE_BUFFER) (
+ IN EFI_ISA_IO_PROTOCOL *This,
+ IN UINTN Pages,
+ IN VOID *HostAddress
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ISA_IO_PROTOCOL_FLUSH) (
+ IN EFI_ISA_IO_PROTOCOL *This
+ );
+
+//
+// Interface structure for the ISA I/O Protocol
+//
+struct _EFI_ISA_IO_PROTOCOL {
+ EFI_ISA_IO_PROTOCOL_ACCESS Mem;
+ EFI_ISA_IO_PROTOCOL_ACCESS Io;
+ EFI_ISA_IO_PROTOCOL_COPY_MEM CopyMem;
+ EFI_ISA_IO_PROTOCOL_MAP Map;
+ EFI_ISA_IO_PROTOCOL_UNMAP Unmap;
+ EFI_ISA_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer;
+ EFI_ISA_IO_PROTOCOL_FREE_BUFFER FreeBuffer;
+ EFI_ISA_IO_PROTOCOL_FLUSH Flush;
+ EFI_ISA_ACPI_RESOURCE_LIST *ResourceList;
+ UINT32 RomSize;
+ VOID *RomImage;
+};
+
+extern EFI_GUID gEfiIsaIoProtocolGuid;
+
+#endif
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