diff options
| author | Ma, Maurice <maurice.ma@intel.com> | 2015-04-29 03:50:20 +0000 |
|---|---|---|
| committer | jyao1 <jyao1@Edk2> | 2015-04-29 03:50:20 +0000 |
| commit | 5c7c41f81d4b89a90dadc01b3c3f4481251852a2 (patch) | |
| tree | 1a21c1d1a25fadd84159f4d6361246af9d389419 /IntelFspWrapperPkg/IntelFspWrapperPkg.dec | |
| parent | 3b17b2458726bf7e2cf640d29ebe14f8af587905 (diff) | |
| download | edk2-platforms-5c7c41f81d4b89a90dadc01b3c3f4481251852a2.tar.xz | |
Add dual FSP binaries support.
There are two FSP images at different locations in a flash (one factory version is read only and other in updatable version)
TempRamInit, FspMemoryInit and TempRamExit are executed from factory version and FspSiliconInit/NotifyPhase will be executed from updatable version.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Ma, Maurice" <maurice.ma@intel.com>
Reviewed-by: "Yao, Jiewen" <Jiewen.Yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17249 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'IntelFspWrapperPkg/IntelFspWrapperPkg.dec')
| -rw-r--r-- | IntelFspWrapperPkg/IntelFspWrapperPkg.dec | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/IntelFspWrapperPkg/IntelFspWrapperPkg.dec b/IntelFspWrapperPkg/IntelFspWrapperPkg.dec index bfed1cc97a..1fc8e2c484 100644 --- a/IntelFspWrapperPkg/IntelFspWrapperPkg.dec +++ b/IntelFspWrapperPkg/IntelFspWrapperPkg.dec @@ -59,10 +59,22 @@ ## Provides the size of the BIOS Flash Device.
gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00200000|UINT32|0x10000002
- ## Indicates the base address of the FSP binary.
+ ## Indicates the base address of the factory FSP binary.
gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFF80000|UINT32|0x10000003
- ## Provides the size of the FSP binary.
+ ## Indicates the base address of the updatable FSP binary to support Dual FSP.
+ # There could be two FSP images at different locations in a flash -
+ # one factory version (default) and updatable version (updatable).
+ # TempRamInit, FspMemoryInit and TempRamExit are always executed from factory version.
+ # FspSiliconInit and NotifyPhase can be executed from updatable version if it is available,
+ # FspSiliconInit and NotifyPhase are executed from factory version if there is no updateable version,
+ # PcdFlashFvFspBase is base address of factory FSP, and PcdFlashFvSecondFspBase
+ # is base address of updatable FSP. If PcdFlashFvSecondFspBase is 0, that means
+ # there is no updatable FSP.
+ gFspWrapperTokenSpaceGuid.PcdFlashFvSecondFspBase|0x00000000|UINT32|0x10000008
+ ## Provides the size of the factory FSP binary.
gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize|0x00048000|UINT32|0x10000004
+ ## Provides the size of the updatable FSP binary to support Dual FSP.
+ gFspWrapperTokenSpaceGuid.PcdFlashFvSecondFspSize|0x00000000|UINT32|0x10000009
## Indicates the base address of the first Microcode Patch in the Microcode Region
gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x10000005
|