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author | jyao1 <jyao1> | 2014-07-24 06:52:43 +0000 |
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committer | jyao1 <jyao1@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-07-24 06:52:43 +0000 |
commit | a33a2f62218e6e49a25d63474b7fe423d8ee4b71 (patch) | |
tree | ca8e4dd491a71f4a7e36fbc17c5e95276d555b43 /IntelFspWrapperPkg/IntelFspWrapperPkg.dec | |
parent | 34717ef034ed275a15683dafd29cb518af50fff0 (diff) | |
download | edk2-platforms-a33a2f62218e6e49a25d63474b7fe423d8ee4b71.tar.xz |
Add IntelFspWrapper to support boot EDKII on FSP bin.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed off by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed by: Ravi Rangarajan <ravi.p.rangarajan@intel.com>
Reviewed by: Maurice Ma <maurice.ma@intel.com>
Reviewed by: Giri Mudusuru <giri.p.mudusuru@intel.com>
Reviewed by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15676 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'IntelFspWrapperPkg/IntelFspWrapperPkg.dec')
-rw-r--r-- | IntelFspWrapperPkg/IntelFspWrapperPkg.dec | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/IntelFspWrapperPkg/IntelFspWrapperPkg.dec b/IntelFspWrapperPkg/IntelFspWrapperPkg.dec new file mode 100644 index 0000000000..0fea5f2269 --- /dev/null +++ b/IntelFspWrapperPkg/IntelFspWrapperPkg.dec @@ -0,0 +1,88 @@ +## @file
+#
+# Provides drivers and definitions to support fsp in EDKII bios.
+#
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License that accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = IntelFspWrapperPkg
+ PACKAGE_GUID = 99101BB6-6DE1-4537-85A3-FD6B594F7468
+ PACKAGE_VERSION = 0.1
+
+[Includes]
+ Include
+
+[LibraryClasses]
+
+[Guids]
+ #
+ # GUID defined in package
+ #
+ gFspWrapperTokenSpaceGuid = {0x2bc1c74a, 0x122f, 0x40b2, { 0xb2, 0x23, 0x8, 0x2b, 0x74, 0x65, 0x22, 0x5d } }
+
+ # Guid define in FSP EAS
+ gFspHeaderFileGuid = { 0x912740BE, 0x2284, 0x4734, { 0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C } }
+ gFspBootLoaderTemporaryMemoryGuid = { 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } }
+ gFspReservedMemoryResourceHobGuid = { 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } }
+ gFspNonVolatileStorageHobGuid = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }
+
+[Ppis]
+ gFspInitDonePpiGuid = { 0xf5ef05e4, 0xd538, 0x4774, 0x8f, 0x1b, 0xe9, 0x77, 0x30, 0x11, 0xe0, 0x38 }
+ gTopOfTemporaryRamPpiGuid = { 0x2f3962b2, 0x57c5, 0x44ec, 0x9e, 0xfc, 0xa6, 0x9f, 0xd3, 0x02, 0x03, 0x2b }
+
+[Protocols]
+
+################################################################################
+#
+# PCD Declarations section - list of all PCDs Declared by this Package
+# Only this package should be providing the
+# declaration, other packages should not.
+#
+################################################################################
+[PcdsFixedAtBuild, PcdsPatchableInModule]
+ ## Provides the memory mapped base address of the BIOS CodeCache Flash Device.
+ gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFFE00000|UINT32|0x10000001
+ ## Provides the size of the BIOS Flash Device.
+ gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00200000|UINT32|0x10000002
+
+ ## Indicates the base address of the FSP binary.
+ gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFF80000|UINT32|0x10000003
+ ## Provides the size of the FSP binary.
+ gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize|0x00048000|UINT32|0x10000004
+
+ ## Indicates the base address of the first Microcode Patch in the Microcode Region
+ gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x10000005
+ gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x10000006
+ ## Indicates the offset of the Cpu Microcode.
+ gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x90|UINT32|0x10000007
+
+ ##
+ # Maximum number of Ppi is provided by SecCore.
+ ##
+ gFspWrapperTokenSpaceGuid.PcdSecCoreMaxPpiSupported|0x6|UINT32|0x20000001
+
+ # This is MAX UPD region size
+ gFspWrapperTokenSpaceGuid.PcdMaxUpdRegionSize|0x200|UINT32|0x30000001
+
+ ## Stack size in the temporary RAM.
+ # 0 means half of TemporaryRamSize.
+ gFspWrapperTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x40000001
+
+ # This is temporary DRAM base and size for StackTop in FspInit
+ gFspWrapperTokenSpaceGuid.PcdTemporaryRamBase|0x00080000|UINT32|0x40000002
+ gFspWrapperTokenSpaceGuid.PcdTemporaryRamSize|0x00010000|UINT32|0x40000003
+
+ ## Indicate the PEI memory size platform want to report
+ gFspWrapperTokenSpaceGuid.PcdPeiMinMemSize|0x1800000|UINT32|0x40000004
+ ## Indicate the PEI memory size platform want to report
+ gFspWrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize|0x3000000|UINT32|0x40000005
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