Improve coding style in MdeModulePkg.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9793 6f19259b-4bc3-4df7-8a09-765794883524

1 files changed, 72 insertions, 70 deletions

diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h
index a995dc40c2..e1b57fafb4 100644
--- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h
+++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h
@@ -2,7 +2,7 @@
 

   This file contains the definination for host controller register operation routines.

 

-Copyright (c) 2007 - 2009, Intel Corporation

+Copyright (c) 2007 - 2010, Intel Corporation

 All rights reserved. This program and the accompanying materials

 are licensed and made available under the terms and conditions of the BSD License

 which accompanies this distribution.  The full text of the license may be found at

@@ -16,75 +16,77 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #ifndef _EFI_EHCI_REG_H_

 #define _EFI_EHCI_REG_H_

 

+//

+// EHCI register offset

+//

+

+

+//

+// Capability register offset

+//

+#define EHC_CAPLENGTH_OFFSET    0    // Capability register length offset

+#define EHC_HCSPARAMS_OFFSET    0x04 // Structural Parameters 04-07h

+#define EHC_HCCPARAMS_OFFSET    0x08 // Capability parameters offset

+

+//

+// Capability register bit definition

+//

+#define HCSP_NPORTS             0x0F // Number of root hub port

+#define HCCP_64BIT              0x01 // 64-bit addressing capability

+

+//

+// Operational register offset

+//

+#define EHC_USBCMD_OFFSET       0x0  // USB command register offset

+#define EHC_USBSTS_OFFSET       0x04 // Statue register offset

+#define EHC_USBINTR_OFFSET      0x08 // USB interrutp offset

+#define EHC_FRINDEX_OFFSET      0x0C // Frame index offset

+#define EHC_CTRLDSSEG_OFFSET    0x10 // Control data structure segment offset

+#define EHC_FRAME_BASE_OFFSET   0x14 // Frame list base address offset

+#define EHC_ASYNC_HEAD_OFFSET   0x18 // Next asynchronous list address offset

+#define EHC_CONFIG_FLAG_OFFSET  0x40 // Configure flag register offset

+#define EHC_PORT_STAT_OFFSET    0x44 // Port status/control offset

+

+#define EHC_FRAME_LEN           1024

 

-typedef enum {

-  //

-  // Capability register offset

-  //

-  EHC_CAPLENGTH_OFFSET    = 0,    // Capability register length offset

-  EHC_HCSPARAMS_OFFSET    = 0x04, // Structural Parameters 04-07h

-  EHC_HCCPARAMS_OFFSET    = 0x08, // Capability parameters offset

-

-  //

-  // Capability register bit definition

-  //

-  HCSP_NPORTS             = 0x0F, // Number of root hub port

-  HCCP_64BIT              = 0x01, // 64-bit addressing capability

-

-  //

-  // Operational register offset

-  //

-  EHC_USBCMD_OFFSET       = 0x0,  // USB command register offset

-  EHC_USBSTS_OFFSET       = 0x04, // Statue register offset

-  EHC_USBINTR_OFFSET      = 0x08, // USB interrutp offset

-  EHC_FRINDEX_OFFSET      = 0x0C, // Frame index offset

-  EHC_CTRLDSSEG_OFFSET    = 0x10, // Control data structure segment offset

-  EHC_FRAME_BASE_OFFSET   = 0x14, // Frame list base address offset

-  EHC_ASYNC_HEAD_OFFSET   = 0x18, // Next asynchronous list address offset

-  EHC_CONFIG_FLAG_OFFSET  = 0x40, // Configure flag register offset

-  EHC_PORT_STAT_OFFSET    = 0x44, // Port status/control offset

-

-  EHC_FRAME_LEN           = 1024,

-

-  //

-  // Register bit definition

-  //

-  CONFIGFLAG_ROUTE_EHC    = 0x01, // Route port to EHC

-

-  USBCMD_RUN              = 0x01,   // Run/stop

-  USBCMD_RESET            = 0x02,   // Start the host controller reset

-  USBCMD_ENABLE_PERIOD    = 0x10,   // Enable periodic schedule

-  USBCMD_ENABLE_ASYNC     = 0x20,   // Enable asynchronous schedule

-  USBCMD_IAAD             = 0x40,   // Interrupt on async advance doorbell

-

-  USBSTS_IAA              = 0x20,   // Interrupt on async advance

-  USBSTS_PERIOD_ENABLED   = 0x4000, // Periodic schedule status

-  USBSTS_ASYNC_ENABLED    = 0x8000, // Asynchronous schedule status

-  USBSTS_HALT             = 0x1000, // Host controller halted

-  USBSTS_SYS_ERROR        = 0x10,   // Host system error

-  USBSTS_INTACK_MASK      = 0x003F, // Mask for the interrupt ACK, the WC

-                                    // (write clean) bits in USBSTS register

-

-  PORTSC_CONN             = 0x01,   // Current Connect Status

-  PORTSC_CONN_CHANGE      = 0x02,   // Connect Status Change

-  PORTSC_ENABLED          = 0x04,   // Port Enable / Disable

-  PORTSC_ENABLE_CHANGE    = 0x08,   // Port Enable / Disable Change

-  PORTSC_OVERCUR          = 0x10,   // Over current Active

-  PORTSC_OVERCUR_CHANGE   = 0x20,   // Over current Change

-  PORSTSC_RESUME          = 0x40,   // Force Port Resume

-  PORTSC_SUSPEND          = 0x80,   // Port Suspend State

-  PORTSC_RESET            = 0x100,  // Port Reset

-  PORTSC_LINESTATE_K      = 0x400,  // Line Status K-state

-  PORTSC_LINESTATE_J      = 0x800,  // Line Status J-state

-  PORTSC_POWER            = 0x1000, // Port Power

-  PORTSC_OWNER            = 0x2000, // Port Owner

-  PORTSC_CHANGE_MASK      = 0x2A,   // Mask of the port change bits,

-                                    // they are WC (write clean)

-  //

-  // PCI Configuration Registers

-  //

-  EHC_BAR_INDEX           = 0 /* how many bytes away from USB_BASE to 0x10 */

-}EHCI_REGISTER_OFFSET;

+//

+// Register bit definition

+//

+#define CONFIGFLAG_ROUTE_EHC    0x01 // Route port to EHC

+

+#define USBCMD_RUN              0x01   // Run/stop

+#define USBCMD_RESET            0x02   // Start the host controller reset

+#define USBCMD_ENABLE_PERIOD    0x10   // Enable periodic schedule

+#define USBCMD_ENABLE_ASYNC     0x20   // Enable asynchronous schedule

+#define USBCMD_IAAD             0x40   // Interrupt on async advance doorbell

+

+#define USBSTS_IAA              0x20   // Interrupt on async advance

+#define USBSTS_PERIOD_ENABLED   0x4000 // Periodic schedule status

+#define USBSTS_ASYNC_ENABLED    0x8000 // Asynchronous schedule status

+#define USBSTS_HALT             0x1000 // Host controller halted

+#define USBSTS_SYS_ERROR        0x10   // Host system error

+#define USBSTS_INTACK_MASK      0x003F // Mask for the interrupt ACK, the WC

+                                       // (write clean) bits in USBSTS register

+

+#define PORTSC_CONN             0x01   // Current Connect Status

+#define PORTSC_CONN_CHANGE      0x02   // Connect Status Change

+#define PORTSC_ENABLED          0x04   // Port Enable / Disable

+#define PORTSC_ENABLE_CHANGE    0x08   // Port Enable / Disable Change

+#define PORTSC_OVERCUR          0x10   // Over current Active

+#define PORTSC_OVERCUR_CHANGE   0x20   // Over current Change

+#define PORSTSC_RESUME          0x40   // Force Port Resume

+#define PORTSC_SUSPEND          0x80   // Port Suspend State

+#define PORTSC_RESET            0x100  // Port Reset

+#define PORTSC_LINESTATE_K      0x400  // Line Status K-state

+#define PORTSC_LINESTATE_J      0x800  // Line Status J-state

+#define PORTSC_POWER            0x1000 // Port Power

+#define PORTSC_OWNER            0x2000 // Port Owner

+#define PORTSC_CHANGE_MASK      0x2A   // Mask of the port change bits,

+                                       // they are WC (write clean)

+//

+// PCI Configuration Registers

+//

+#define EHC_BAR_INDEX           0      // how many bytes away from USB_BASE to 0x10

 

 #define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)

 

@@ -107,7 +109,7 @@ typedef struct {
 //

 #pragma pack(1)

 typedef struct {

-  UINT8                   PI;

+  UINT8                   ProgInterface;

   UINT8                   SubClassCode;

   UINT8                   BaseCode;

 } USB_CLASSC;