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| author | Feng Tian <feng.tian@intel.com> | 2013-09-11 06:57:53 +0000 |
|---|---|---|
| committer | erictian <erictian@6f19259b-4bc3-4df7-8a09-765794883524> | 2013-09-11 06:57:53 +0000 |
| commit | 7b8883c6a97c9e9dcaa456a67f66f92dde45685f (patch) | |
| tree | 04446b2dde40afaf6d717f5507bea1ac6670c7d5 /MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.h | |
| parent | ad3f3656413db1727218c605fd1c367c00be9b58 (diff) | |
| download | edk2-platforms-7b8883c6a97c9e9dcaa456a67f66f92dde45685f.tar.xz | |
MdeModulePkg/NvmExpressDxe: Fix some bugs
1) The Queue size field in create I/O submission/completion queue cmds is 0-based. the current code is 1-based.
2) a typo on allocated memory page size. it's inconsistent that some places is using 4 pages, but a place is using 6 pages.
3) a typo on PRP/SGL mechanism judgment. should directly use Psdt field rather than Opc field.
4) some platforms may not support UINT64 width access on MMIO register. Fix it to use two 32-bit width access.
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Kinney Michael <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14657 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.h')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.h b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.h index d39b62e102..79ab927edb 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.h +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.h @@ -56,11 +56,11 @@ extern EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL gNvmExpressDriverSupportedEfiV #define PCI_CLASS_MASS_STORAGE_NVM 0x08 // mass storage sub-class non-volatile memory.
#define PCI_IF_NVMHCI 0x02 // mass storage programming interface NVMHCI.
-#define NVME_ASQ_SIZE 2 // Number of admin submission queue entries
-#define NVME_ACQ_SIZE 2 // Number of admin completion queue entries
+#define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based
+#define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based
-#define NVME_CSQ_SIZE 2 // Number of I/O submission queue entries
-#define NVME_CCQ_SIZE 2 // Number of I/O completion queue entries
+#define NVME_CSQ_SIZE 1 // Number of I/O submission queue entries, which is 0-based
+#define NVME_CCQ_SIZE 1 // Number of I/O completion queue entries, which is 0-based
#define NVME_MAX_IO_QUEUES 2 // Number of I/O queues supported by the driver
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