Improve coding style in MdeModulePkg.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9793 6f19259b-4bc3-4df7-8a09-765794883524

5 files changed, 133 insertions, 131 deletions

diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c
index 1ed79023a3..c2d560b48c 100644
--- a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c
+++ b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c
@@ -2,7 +2,7 @@
 

   The UHCI driver model and HC protocol routines.

 

-Copyright (c) 2004 - 2009, Intel Corporation

+Copyright (c) 2004 - 2010, Intel Corporation

 All rights reserved. This program and the accompanying materials

 are licensed and made available under the terms and conditions of the BSD License

 which accompanies this distribution.  The full text of the license may be found at

@@ -1411,7 +1411,7 @@ UhciDriverBindingSupported (
   //

   if ((UsbClassCReg.BaseCode != PCI_CLASS_SERIAL) ||

       (UsbClassCReg.SubClassCode != PCI_CLASS_SERIAL_USB) ||

-      (UsbClassCReg.PI != PCI_IF_UHCI)

+      (UsbClassCReg.ProgInterface != PCI_IF_UHCI)

       ) {

 

     Status = EFI_UNSUPPORTED;

diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h
index eb61554e0e..c2377bf3a7 100644
--- a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h
+++ b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h
@@ -2,7 +2,7 @@
 

   The definition for UHCI driver model and HC protocol routines.

 

-Copyright (c) 2004 - 2009, Intel Corporation

+Copyright (c) 2004 - 2010, Intel Corporation

 All rights reserved. This program and the accompanying materials

 are licensed and made available under the terms and conditions of the BSD License

 which accompanies this distribution.  The full text of the license may be found at

@@ -45,38 +45,39 @@ typedef struct _USB_HC_DEV  USB_HC_DEV;
 #include "UhciDebug.h"

 #include "ComponentName.h"

 

-typedef enum {

-  UHC_1_MICROSECOND             = 1,

-  UHC_1_MILLISECOND             = 1000 * UHC_1_MICROSECOND,

-  UHC_1_SECOND                  = 1000 * UHC_1_MILLISECOND,

+//

+// UHC timeout experience values

+//

 

-  //

-  // UHCI register operation timeout, set by experience

-  //

-  UHC_GENERIC_TIMEOUT           = UHC_1_SECOND,

+#define UHC_1_MICROSECOND             1

+#define UHC_1_MILLISECOND             (1000 * UHC_1_MICROSECOND)

+#define UHC_1_SECOND                  (1000 * UHC_1_MILLISECOND)

 

-  //

-  // Wait for force global resume(FGR) complete, refers to

-  // specification[UHCI11-2.1.1]

-  //

-  UHC_FORCE_GLOBAL_RESUME_STALL = 20 * UHC_1_MILLISECOND,

+//

+// UHCI register operation timeout, set by experience

+//

+#define UHC_GENERIC_TIMEOUT           UHC_1_SECOND

 

-  //

-  // Wait for roothub port reset and recovery, reset stall

-  // is set by experience, and recovery stall refers to

-  // specification[UHCI11-2.1.1]

-  //

-  UHC_ROOT_PORT_RESET_STALL     = 50 * UHC_1_MILLISECOND,

-  UHC_ROOT_PORT_RECOVERY_STALL  = 10 * UHC_1_MILLISECOND,

+//

+// Wait for force global resume(FGR) complete, refers to

+// specification[UHCI11-2.1.1]

+//

+#define UHC_FORCE_GLOBAL_RESUME_STALL (20 * UHC_1_MILLISECOND)

 

-  //

-  // Sync and Async transfer polling interval, set by experience,

-  // and the unit of Async is 100us.

-  //

-  UHC_SYNC_POLL_INTERVAL        = 1 * UHC_1_MILLISECOND,

-  UHC_ASYNC_POLL_INTERVAL       = 50 * 10000UL

-}UHC_TIMEOUT_EXPERIENCE_VALUE;

+//

+// Wait for roothub port reset and recovery, reset stall

+// is set by experience, and recovery stall refers to

+// specification[UHCI11-2.1.1]

+//

+#define UHC_ROOT_PORT_RESET_STALL     (50 * UHC_1_MILLISECOND)

+#define UHC_ROOT_PORT_RECOVERY_STALL  (10 * UHC_1_MILLISECOND)

 

+//

+// Sync and Async transfer polling interval, set by experience,

+// and the unit of Async is 100us.

+//

+#define UHC_SYNC_POLL_INTERVAL        (1 * UHC_1_MILLISECOND)

+#define UHC_ASYNC_POLL_INTERVAL       (50 * 10000UL)

 

 //

 // UHC raises TPL to TPL_NOTIFY to serialize all its operations

@@ -88,7 +89,7 @@ typedef enum {
 

 #pragma pack(1)

 typedef struct {

-  UINT8               PI;

+  UINT8               ProgInterface;

   UINT8               SubClassCode;

   UINT8               BaseCode;

 } USB_CLASSC;

diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.h b/MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.h
index 8d7a076889..d9bdc439f5 100644
--- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.h
+++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.h
@@ -2,7 +2,7 @@
 

   The definition for UHCI register operation routines.

 

-Copyright (c) 2007 - 2008, Intel Corporation

+Copyright (c) 2007 - 2010, Intel Corporation

 All rights reserved. This program and the accompanying materials

 are licensed and made available under the terms and conditions of the BSD License

 which accompanies this distribution.  The full text of the license may be found at

@@ -16,81 +16,83 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #ifndef _EFI_UHCI_REG_H_

 #define _EFI_UHCI_REG_H_

 

-typedef enum {

-  UHCI_FRAME_NUM        = 1024,

-

-  //

-  // Register offset and PCI related staff

-  //

-  USB_BAR_INDEX         = 4,

-

-  USBCMD_OFFSET         = 0,

-  USBSTS_OFFSET         = 2,

-  USBINTR_OFFSET        = 4,

-  USBPORTSC_OFFSET      = 0x10,

-  USB_FRAME_NO_OFFSET   = 6,

-  USB_FRAME_BASE_OFFSET = 8,

-  USB_EMULATION_OFFSET  = 0xC0,

-

-  //

-  // Packet IDs

-  //

-  SETUP_PACKET_ID       = 0x2D,

-  INPUT_PACKET_ID       = 0x69,

-  OUTPUT_PACKET_ID      = 0xE1,

-  ERROR_PACKET_ID       = 0x55,

-

-  //

-  // USB port status and control bit definition.

-  //

-  USBPORTSC_CCS         = BIT0,  // Current Connect Status

-  USBPORTSC_CSC         = BIT1,  // Connect Status Change

-  USBPORTSC_PED         = BIT2,  // Port Enable / Disable

-  USBPORTSC_PEDC        = BIT3,  // Port Enable / Disable Change

-  USBPORTSC_LSL         = BIT4,  // Line Status Low BIT

-  USBPORTSC_LSH         = BIT5,  // Line Status High BIT

-  USBPORTSC_RD          = BIT6,  // Resume Detect

-  USBPORTSC_LSDA        = BIT8,  // Low Speed Device Attached

-  USBPORTSC_PR          = BIT9,  // Port Reset

-  USBPORTSC_SUSP        = BIT12, // Suspend

-

-  //

-  // UHCI Spec said it must implement 2 ports each host at least,

-  // and if more, check whether the bit7 of PORTSC is always 1.

-  // So here assume the max of port number each host is 16.

-  //

-  USB_MAX_ROOTHUB_PORT  = 0x0F,

-  

-  //

-  // Command register bit definitions

-  //

-  USBCMD_RS             = BIT0,  // Run/Stop

-  USBCMD_HCRESET        = BIT1,  // Host reset

-  USBCMD_GRESET         = BIT2,  // Global reset

-  USBCMD_EGSM           = BIT3,  // Global Suspend Mode

-  USBCMD_FGR            = BIT4,  // Force Global Resume

-  USBCMD_SWDBG          = BIT5,  // SW Debug mode

-  USBCMD_CF             = BIT6,  // Config Flag (sw only)

-  USBCMD_MAXP           = BIT7,  // Max Packet (0 = 32, 1 = 64)

-

-  //

-  // USB Status register bit definitions

-  //

-  USBSTS_USBINT         = BIT0,  // Interrupt due to IOC

-  USBSTS_ERROR          = BIT1,  // Interrupt due to error

-  USBSTS_RD             = BIT2,  // Resume Detect

-  USBSTS_HSE            = BIT3,  // Host System Error

-  USBSTS_HCPE           = BIT4,  // Host Controller Process Error

-  USBSTS_HCH            = BIT5,  // HC Halted

-

-  USBTD_ACTIVE          = BIT7,  // TD is still active

-  USBTD_STALLED         = BIT6,  // TD is stalled

-  USBTD_BUFFERR         = BIT5,  // Buffer underflow or overflow

-  USBTD_BABBLE          = BIT4,  // Babble condition

-  USBTD_NAK             = BIT3,  // NAK is received

-  USBTD_CRC             = BIT2,  // CRC/Time out error

-  USBTD_BITSTUFF        = BIT1  // Bit stuff error

-}UHCI_REGISTER_OFFSET;

+//

+// UHCI register offset

+//

+

+#define UHCI_FRAME_NUM        1024

+

+//

+// Register offset and PCI related staff

+//

+#define USB_BAR_INDEX         4

+

+#define USBCMD_OFFSET         0

+#define USBSTS_OFFSET         2

+#define USBINTR_OFFSET        4

+#define USBPORTSC_OFFSET      0x10

+#define USB_FRAME_NO_OFFSET   6

+#define USB_FRAME_BASE_OFFSET 8

+#define USB_EMULATION_OFFSET  0xC0

+

+//

+// Packet IDs

+//

+#define SETUP_PACKET_ID       0x2D

+#define INPUT_PACKET_ID       0x69

+#define OUTPUT_PACKET_ID      0xE1

+#define ERROR_PACKET_ID       0x55

+

+//

+// USB port status and control bit definition.

+//

+#define USBPORTSC_CCS         BIT0  // Current Connect Status

+#define USBPORTSC_CSC         BIT1  // Connect Status Change

+#define USBPORTSC_PED         BIT2  // Port Enable / Disable

+#define USBPORTSC_PEDC        BIT3  // Port Enable / Disable Change

+#define USBPORTSC_LSL         BIT4  // Line Status Low BIT

+#define USBPORTSC_LSH         BIT5  // Line Status High BIT

+#define USBPORTSC_RD          BIT6  // Resume Detect

+#define USBPORTSC_LSDA        BIT8  // Low Speed Device Attached

+#define USBPORTSC_PR          BIT9  // Port Reset

+#define USBPORTSC_SUSP        BIT12 // Suspend

+

+//

+// UHCI Spec said it must implement 2 ports each host at least,

+// and if more, check whether the bit7 of PORTSC is always 1.

+// So here assume the max of port number each host is 16.

+//

+#define USB_MAX_ROOTHUB_PORT  0x0F

+

+//

+// Command register bit definitions

+//

+#define USBCMD_RS             BIT0  // Run/Stop

+#define USBCMD_HCRESET        BIT1  // Host reset

+#define USBCMD_GRESET         BIT2  // Global reset

+#define USBCMD_EGSM           BIT3  // Global Suspend Mode

+#define USBCMD_FGR            BIT4  // Force Global Resume

+#define USBCMD_SWDBG          BIT5  // SW Debug mode

+#define USBCMD_CF             BIT6  // Config Flag (sw only)

+#define USBCMD_MAXP           BIT7  // Max Packet (0 = 32, 1 = 64)

+

+//

+// USB Status register bit definitions

+//

+#define USBSTS_USBINT         BIT0  // Interrupt due to IOC

+#define USBSTS_ERROR          BIT1  // Interrupt due to error

+#define USBSTS_RD             BIT2  // Resume Detect

+#define USBSTS_HSE            BIT3  // Host System Error

+#define USBSTS_HCPE           BIT4  // Host Controller Process Error

+#define USBSTS_HCH            BIT5  // HC Halted

+

+#define USBTD_ACTIVE          BIT7  // TD is still active

+#define USBTD_STALLED         BIT6  // TD is stalled

+#define USBTD_BUFFERR         BIT5  // Buffer underflow or overflow

+#define USBTD_BABBLE          BIT4  // Babble condition

+#define USBTD_NAK             BIT3  // NAK is received

+#define USBTD_CRC             BIT2  // CRC/Time out error

+#define USBTD_BITSTUFF        BIT1  // Bit stuff error

 

 

 /**

diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.h b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.h
index b4b7c4c0d6..310dfa0ab2 100644
--- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.h
+++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.h
@@ -2,7 +2,7 @@
 

   The definition for EHCI register operation routines.

 

-Copyright (c) 2007, 2009, Intel Corporation

+Copyright (c) 2007 - 2010, Intel Corporation

 All rights reserved. This program and the accompanying materials

 are licensed and made available under the terms and conditions of the BSD License

 which accompanies this distribution.  The full text of the license may be found at

@@ -17,21 +17,18 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define _EFI_UHCI_SCHED_H_

 

 

-typedef enum {

-  UHCI_ASYNC_INT_SIGNATURE = SIGNATURE_32 ('u', 'h', 'c', 'a'),

-

-  //

-  // The failure mask for USB transfer return status. If any of

-  // these bit is set, the transfer failed. EFI_USB_ERR_NOEXECUTE

-  // and EFI_USB_ERR_NAK are not considered as error condition:

-  // the transfer is still going on.

-  //

-  USB_ERR_FAIL_MASK = EFI_USB_ERR_STALL   | EFI_USB_ERR_BUFFER |

-                      EFI_USB_ERR_BABBLE  | EFI_USB_ERR_CRC    |

-                      EFI_USB_ERR_TIMEOUT | EFI_USB_ERR_BITSTUFF |

-                      EFI_USB_ERR_SYSTEM

+#define UHCI_ASYNC_INT_SIGNATURE  SIGNATURE_32 ('u', 'h', 'c', 'a')

+//

+// The failure mask for USB transfer return status. If any of

+// these bit is set, the transfer failed. EFI_USB_ERR_NOEXECUTE

+// and EFI_USB_ERR_NAK are not considered as error condition:

+// the transfer is still going on.

+//

+#define USB_ERR_FAIL_MASK  (EFI_USB_ERR_STALL   | EFI_USB_ERR_BUFFER | \

+                            EFI_USB_ERR_BABBLE  | EFI_USB_ERR_CRC    | \

+                            EFI_USB_ERR_TIMEOUT | EFI_USB_ERR_BITSTUFF | \

+                            EFI_USB_ERR_SYSTEM)

 

-}UHCI_ERR_FAIL_MASK;

 

 //

 // Structure to return the result of UHCI QH execution.

diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UsbHcMem.h b/MdeModulePkg/Bus/Pci/UhciDxe/UsbHcMem.h
index 6b71442b3c..5ad9f97683 100644
--- a/MdeModulePkg/Bus/Pci/UhciDxe/UsbHcMem.h
+++ b/MdeModulePkg/Bus/Pci/UhciDxe/UsbHcMem.h
@@ -2,7 +2,7 @@
 

   This file contains the definination for host controller memory management routines

 

-Copyright (c) 2007, Intel Corporation

+Copyright (c) 2007 - 2010, Intel Corporation

 All rights reserved. This program and the accompanying materials

 are licensed and made available under the terms and conditions of the BSD License

 which accompanies this distribution.  The full text of the license may be found at

@@ -25,15 +25,16 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
           ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))

 

 

-typedef struct _USBHC_MEM_BLOCK {

+typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;

+struct _USBHC_MEM_BLOCK {

   UINT8                   *Bits;    // Bit array to record which unit is allocated

   UINTN                   BitsLen;

   UINT8                   *Buf;

   UINT8                   *BufHost;

   UINTN                   BufLen;   // Memory size in bytes

   VOID                    *Mapping;

-  struct _USBHC_MEM_BLOCK *Next;

-} USBHC_MEM_BLOCK;

+  USBHC_MEM_BLOCK         *Next;

+};

 

 //

 // USBHC_MEM_POOL is used to manage the memory used by USB

@@ -47,12 +48,13 @@ typedef struct _USBHC_MEM_POOL {
   USBHC_MEM_BLOCK         *Head;

 } USBHC_MEM_POOL;

 

-typedef enum {

-  USBHC_MEM_UNIT           = 64,     // Memory allocation unit, must be 2^n, n>4

+//

+// Memory allocation unit, must be 2^n, n>4

+//

+#define USBHC_MEM_UNIT           64

 

-  USBHC_MEM_UNIT_MASK      = USBHC_MEM_UNIT - 1,

-  USBHC_MEM_DEFAULT_PAGES  = 16

-}UHCI_MEM_UNIT_DATA;

+#define USBHC_MEM_UNIT_MASK      (USBHC_MEM_UNIT - 1)

+#define USBHC_MEM_DEFAULT_PAGES  16

 

 #define USBHC_MEM_ROUND(Len)  (((Len) + USBHC_MEM_UNIT_MASK) & (~USBHC_MEM_UNIT_MASK))