diff options
| author | erictian <erictian@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-11-25 08:08:54 +0000 |
|---|---|---|
| committer | erictian <erictian@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-11-25 08:08:54 +0000 |
| commit | 6b4483cdbdcf5e74ee61b025116f86c4e15a4793 (patch) | |
| tree | 74aee620b7e79a23db4988c9cc0cb9e26418e1ad /MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c | |
| parent | 4d6afad3b90f169dc15f0d21b2067b07ef7b714e (diff) | |
| download | edk2-platforms-6b4483cdbdcf5e74ee61b025116f86c4e15a4793.tar.xz | |
MdeModulePkg: The patch eliminates two assumptions
1) XHCI host controller hw always provides more than 5 interrupters.
Now using interrupter 0 to accommodate all received events.
2) XHCI host controller hw always provides 32bytes context size.
Now it dynamically detect context size and construct it.
also solved several issues:
1) Divides 64byte width register access to two 32bit registers access because some XHCI chipsets cannot support a single 64bit access.
2) Remove halt host controller statement in UsbBusDriverBindingStop(). It has been done by host controller’s DriverBindingStop(). And XhciDriverBindingStop() need XHCI host controller is in running state because it need execute DISABLE_SLOT cmd to release h/w resource.
signed-off-by: erictian
Reviewed-by: li-elvin
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12785 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c | 103 |
1 files changed, 0 insertions, 103 deletions
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c index 874967974c..9d50ef8242 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c @@ -192,39 +192,6 @@ XhcWriteOpReg16 ( }
/**
- Write the data to the 8-bytes width XHCI operational register.
-
- @param Xhc The XHCI Instance.
- @param Offset The offset of the 8-bytes width operational register.
- @param Data The data to write.
-
-**/
-VOID
-XhcWriteOpReg64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT64 Data
- )
-{
- EFI_STATUS Status;
-
- ASSERT (Xhc->CapLength != 0);
-
- Status = Xhc->PciIo->Mem.Write (
- Xhc->PciIo,
- EfiPciIoWidthUint64,
- XHC_BAR_INDEX,
- (UINT64) (Xhc->CapLength + Offset),
- 1,
- &Data
- );
-
- if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "XhcWriteOpReg64: Pci Io Write error: %r at %d\n", Status, Offset));
- }
-}
-
-/**
Read XHCI door bell register.
@param Xhc The XHCI Instance.
@@ -332,43 +299,6 @@ XhcReadRuntimeReg ( }
/**
- Read 8-bytes width XHCI runtime register.
-
- @param Xhc The XHCI Instance.
- @param Offset The offset of the 8-bytes width runtime register.
-
- @return The register content read
-
-**/
-UINT64
-XhcReadRuntimeReg64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
- )
-{
- UINT64 Data;
- EFI_STATUS Status;
-
- ASSERT (Xhc->RTSOff != 0);
-
- Status = Xhc->PciIo->Mem.Read (
- Xhc->PciIo,
- EfiPciIoWidthUint64,
- XHC_BAR_INDEX,
- (UINT64) (Xhc->RTSOff + Offset),
- 1,
- &Data
- );
-
- if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "XhcReadRuntimeReg64: Pci Io Read error - %r at %d\n", Status, Offset));
- Data = 0xFFFFFFFFFFFFFFFFULL;
- }
-
- return Data;
-}
-
-/**
Write the data to the XHCI runtime register.
@param Xhc The XHCI Instance.
@@ -402,39 +332,6 @@ XhcWriteRuntimeReg ( }
/**
- Write the data to the 8-bytes width XHCI runtime register.
-
- @param Xhc The XHCI Instance.
- @param Offset The offset of the 8-bytes width runtime register.
- @param Data The data to write.
-
-**/
-VOID
-XhcWriteRuntimeReg64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT64 Data
- )
-{
- EFI_STATUS Status;
-
- ASSERT (Xhc->RTSOff != 0);
-
- Status = Xhc->PciIo->Mem.Write (
- Xhc->PciIo,
- EfiPciIoWidthUint64,
- XHC_BAR_INDEX,
- (UINT64) (Xhc->RTSOff + Offset),
- 1,
- &Data
- );
-
- if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "XhcWriteRuntimeReg64: Pci Io Write error: %r at %d\n", Status, Offset));
- }
-}
-
-/**
Read XHCI extended capability register.
@param Xhc The XHCI Instance.
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