diff options
| author | Hao Wu <hao.a.wu@intel.com> | 2017-02-24 10:01:34 +0800 |
|---|---|---|
| committer | Hao Wu <hao.a.wu@intel.com> | 2017-03-06 14:33:20 +0800 |
| commit | 16f6922709952c7ad468dcdee6ef94b3e5a3cd90 (patch) | |
| tree | 999456e2e6812457d5c0b32b969ac0eed2b02149 /MdeModulePkg/Bus/Pci | |
| parent | 95ba3d92dca2616715e2af89d2bbeca9577a3e2c (diff) | |
| download | edk2-platforms-16f6922709952c7ad468dcdee6ef94b3e5a3cd90.tar.xz | |
MdeModulePkg: Refine casting expression result to bigger size
There are cases that the operands of an expression are all with rank less
than UINT64/INT64 and the result of the expression is explicitly cast to
UINT64/INT64 to fit the target size.
An example will be:
UINT32 a,b;
// a and b can be any unsigned int type with rank less than UINT64, like
// UINT8, UINT16, etc.
UINT64 c;
c = (UINT64) (a + b);
Some static code checkers may warn that the expression result might
overflow within the rank of "int" (integer promotions) and the result is
then cast to a bigger size.
The commit refines codes by the following rules:
1). When the expression is possible to overflow the range of unsigned int/
int:
c = (UINT64)a + b;
2). When the expression will not overflow within the rank of "int", remove
the explicit type casts:
c = a + b;
3). When the expression will be cast to pointer of possible greater size:
UINT32 a,b;
VOID *c;
c = (VOID *)(UINTN)(a + b); --> c = (VOID *)((UINTN)a + b);
4). When one side of a comparison expression contains only operands with
rank less than UINT32:
UINT8 a;
UINT16 b;
UINTN c;
if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...}
For rule 4), if we remove the 'UINTN' type cast like:
if (a + b > c) {...}
The VS compiler will complain with warning C4018 (signed/unsigned
mismatch, level 3 warning) due to promoting 'a + b' to type 'int'.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Diffstat (limited to 'MdeModulePkg/Bus/Pci')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c | 8 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/IdeBusPei/AtapiPeim.c | 4 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c | 2 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c | 20 |
4 files changed, 17 insertions, 17 deletions
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c index 3a6ed02be7..34836eccf5 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c @@ -2,7 +2,7 @@ The EHCI register operation routines.
-Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -76,7 +76,7 @@ EhcReadDbgRegister ( Ehc->PciIo,
EfiPciIoWidthUint32,
Ehc->DebugPortBarNum,
- (UINT64) (Ehc->DebugPortOffset + Offset),
+ Ehc->DebugPortOffset + Offset,
1,
&Data
);
@@ -115,7 +115,7 @@ EhcReadOpReg ( Ehc->PciIo,
EfiPciIoWidthUint32,
EHC_BAR_INDEX,
- (UINT64) (Ehc->CapLen + Offset),
+ Ehc->CapLen + Offset,
1,
&Data
);
@@ -152,7 +152,7 @@ EhcWriteOpReg ( Ehc->PciIo,
EfiPciIoWidthUint32,
EHC_BAR_INDEX,
- (UINT64) (Ehc->CapLen + Offset),
+ Ehc->CapLen + Offset,
1,
&Data
);
diff --git a/MdeModulePkg/Bus/Pci/IdeBusPei/AtapiPeim.c b/MdeModulePkg/Bus/Pci/IdeBusPei/AtapiPeim.c index be1b829200..b1ab34d597 100644 --- a/MdeModulePkg/Bus/Pci/IdeBusPei/AtapiPeim.c +++ b/MdeModulePkg/Bus/Pci/IdeBusPei/AtapiPeim.c @@ -5,7 +5,7 @@ ATA controllers in the platform. This PPI can be consumed by PEIM which produce gEfiPeiDeviceRecoveryModulePpiGuid
for Atapi CD ROM device.
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions
@@ -593,7 +593,7 @@ AtapiEnumerateDevices ( //
// Pata & Sata, Primary & Secondary channel, Master & Slave device
//
- DevicePosition = (UINTN) (Index1 * 2 + Index2);
+ DevicePosition = Index1 * 2 + Index2;
if (DiscoverAtapiDevice (AtapiBlkIoDev, DevicePosition, &MediaInfo, &MediaInfo2)) {
//
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c index d2ad94eceb..3713c07844 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c @@ -305,7 +305,7 @@ GetOpRomInfo ( return EFI_NOT_FOUND;
}
- PciIoDevice->RomSize = (UINT64) ((~AllOnes) + 1);
+ PciIoDevice->RomSize = (~AllOnes) + 1;
return EFI_SUCCESS;
}
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c index 0e1c86cc16..4d5937de53 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c @@ -2,7 +2,7 @@ The XHCI register operation routines.
-Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -112,7 +112,7 @@ XhcReadOpReg ( Xhc->PciIo,
EfiPciIoWidthUint32,
XHC_BAR_INDEX,
- (UINT64) (Xhc->CapLength + Offset),
+ Xhc->CapLength + Offset,
1,
&Data
);
@@ -148,7 +148,7 @@ XhcWriteOpReg ( Xhc->PciIo,
EfiPciIoWidthUint32,
XHC_BAR_INDEX,
- (UINT64) (Xhc->CapLength + Offset),
+ Xhc->CapLength + Offset,
1,
&Data
);
@@ -181,7 +181,7 @@ XhcWriteOpReg16 ( Xhc->PciIo,
EfiPciIoWidthUint16,
XHC_BAR_INDEX,
- (UINT64) (Xhc->CapLength + Offset),
+ Xhc->CapLength + Offset,
1,
&Data
);
@@ -215,7 +215,7 @@ XhcReadDoorBellReg ( Xhc->PciIo,
EfiPciIoWidthUint32,
XHC_BAR_INDEX,
- (UINT64) (Xhc->DBOff + Offset),
+ Xhc->DBOff + Offset,
1,
&Data
);
@@ -251,7 +251,7 @@ XhcWriteDoorBellReg ( Xhc->PciIo,
EfiPciIoWidthUint32,
XHC_BAR_INDEX,
- (UINT64) (Xhc->DBOff + Offset),
+ Xhc->DBOff + Offset,
1,
&Data
);
@@ -285,7 +285,7 @@ XhcReadRuntimeReg ( Xhc->PciIo,
EfiPciIoWidthUint32,
XHC_BAR_INDEX,
- (UINT64) (Xhc->RTSOff + Offset),
+ Xhc->RTSOff + Offset,
1,
&Data
);
@@ -321,7 +321,7 @@ XhcWriteRuntimeReg ( Xhc->PciIo,
EfiPciIoWidthUint32,
XHC_BAR_INDEX,
- (UINT64) (Xhc->RTSOff + Offset),
+ Xhc->RTSOff + Offset,
1,
&Data
);
@@ -355,7 +355,7 @@ XhcReadExtCapReg ( Xhc->PciIo,
EfiPciIoWidthUint32,
XHC_BAR_INDEX,
- (UINT64) (Xhc->ExtCapRegBase + Offset),
+ Xhc->ExtCapRegBase + Offset,
1,
&Data
);
@@ -391,7 +391,7 @@ XhcWriteExtCapReg ( Xhc->PciIo,
EfiPciIoWidthUint32,
XHC_BAR_INDEX,
- (UINT64) (Xhc->ExtCapRegBase + Offset),
+ Xhc->ExtCapRegBase + Offset,
1,
&Data
);
|