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authorrsun3 <rsun3@6f19259b-4bc3-4df7-8a09-765794883524>2010-11-04 05:27:23 +0000
committerrsun3 <rsun3@6f19259b-4bc3-4df7-8a09-765794883524>2010-11-04 05:27:23 +0000
commit0a6c09052110ebd0242f4ddacf8b4e5007a29774 (patch)
tree7a91b6fb5e3125ae8889ec041841729991c61b03 /MdeModulePkg/Core
parent5469967137a29bf0f8893ae120391df079eccffd (diff)
downloadedk2-platforms-0a6c09052110ebd0242f4ddacf8b4e5007a29774.tar.xz
Complement fix for revision #10998 (Remove PI SMM IPL's dependency on CPU AP).
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11001 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdeModulePkg/Core')
-rw-r--r--MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c20
1 files changed, 12 insertions, 8 deletions
diff --git a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c b/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c
index 5cdb5bdeab..21cd87c315 100644
--- a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c
+++ b/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c
@@ -567,6 +567,7 @@ SmmIplSmmConfigurationEventNotify (
//
// Attempt to reset SMRAM cacheability to UC
+ // Assume CPU AP is available at this time
//
Status = gDS->SetMemorySpaceAttributes(
mSmramCacheBase,
@@ -1069,6 +1070,7 @@ SmmIplEntry (
// Note that it is expected that cacheability of SMRAM has been set to WB if CPU AP
// is not available here.
//
+ CpuArch = NULL;
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&CpuArch);
if (!EFI_ERROR (Status)) {
Status = gDS->SetMemorySpaceAttributes(
@@ -1121,14 +1123,16 @@ SmmIplEntry (
//
// Attempt to reset SMRAM cacheability to UC
//
- Status = gDS->SetMemorySpaceAttributes(
- mSmramCacheBase,
- mSmramCacheSize,
- EFI_MEMORY_UC
- );
- if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_WARN, "SMM IPL failed to reset SMRAM window to EFI_MEMORY_UC\n"));
- }
+ if (CpuArch != NULL) {
+ Status = gDS->SetMemorySpaceAttributes(
+ mSmramCacheBase,
+ mSmramCacheSize,
+ EFI_MEMORY_UC
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "SMM IPL failed to reset SMRAM window to EFI_MEMORY_UC\n"));
+ }
+ }
}
} else {
//