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authorFeng Tian <feng.tian@intel.com>2016-09-14 09:36:11 +0800
committerFeng Tian <feng.tian@intel.com>2016-09-21 12:42:05 +0800
commitdbe10619bc443215477c5c0c4c949410bf68b1ec (patch)
tree16daf03be2f75e5e30622fb81862ed9d9af75b70 /MdeModulePkg/Include/Library/PciHostBridgeLib.h
parent7419aedd93132f2dfc91e7bf3634fba7e0842c7b (diff)
downloadedk2-platforms-dbe10619bc443215477c5c0c4c949410bf68b1ec.tar.xz
MdeModulePkg/XhciDxe:1ms delay before access MMIO reg during reset
Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during HC reset. As this delay is not defined by XHCI spec, we use this workaround to fix the issue. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
Diffstat (limited to 'MdeModulePkg/Include/Library/PciHostBridgeLib.h')
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