diff options
| author | Ruiyu Ni <ruiyu.ni@intel.com> | 2016-04-01 16:14:07 +0800 |
|---|---|---|
| committer | Ruiyu Ni <ruiyu.ni@intel.com> | 2016-05-23 13:49:41 +0800 |
| commit | 05070c1b471b0d2af759f582e3c305859cd36b23 (patch) | |
| tree | 50799f8a35b2437291fcde39d0f758a146df982c /MdeModulePkg | |
| parent | ea669c1ba3313e9192a0dcee2dd7e4e6da75eddf (diff) | |
| download | edk2-platforms-05070c1b471b0d2af759f582e3c305859cd36b23.tar.xz | |
MdeModulePkg/PciBus: do not improperly degrade resource
PciBus driver originally always degrade (64->32) the MMIO resource
for PCI BAR when the PCI device contains option ROM.
But the degrade causes the PCI device can only use resource below 4GB
which makes the resource allocation fails when the PCI device wants
very big MMIO.
The patch follows the PI spec (ECR 1529) to honor the granularity
setting for PCI BAR from IncompatiblePciDeviceSupport so that even
for PCI device which contains option ROM, the degrade doesn't happen
if IncompatiblePciDeviceSupport returns 64 as granularity.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Diffstat (limited to 'MdeModulePkg')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 3 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 33 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c | 8 |
3 files changed, 41 insertions, 3 deletions
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h index 2226b1b052..b12d7ec503 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -1,7 +1,7 @@ /** @file
Header files and data structures needed by PCI Bus module.
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -102,6 +102,7 @@ struct _PCI_BAR { UINT64 Length;
UINT64 Alignment;
PCI_BAR_TYPE BarType;
+ BOOLEAN BarTypeFixed;
UINT16 Offset;
};
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c index 29d80c4a23..80f2885005 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c @@ -1416,6 +1416,38 @@ UpdatePciInfo ( //
if (CheckBarType (PciIoDevice, (UINT8) BarIndex, PciBarTypeMem)) {
SetFlag = TRUE;
+
+ //
+ // Ignored if granularity is 0.
+ // Ignored if PCI BAR is I/O or 32-bit memory.
+ // If PCI BAR is 64-bit memory and granularity is 32, then
+ // the PCI BAR resource is allocated below 4GB.
+ // If PCI BAR is 64-bit memory and granularity is 64, then
+ // the PCI BAR resource is allocated above 4GB.
+ //
+ if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeMem64) {
+ switch (Ptr->AddrSpaceGranularity) {
+ case 32:
+ PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeMem32;
+ case 64:
+ PciIoDevice->PciBar[BarIndex].BarTypeFixed = TRUE;
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypePMem64) {
+ switch (Ptr->AddrSpaceGranularity) {
+ case 32:
+ PciIoDevice->PciBar[BarIndex].BarType = PciBarTypePMem32;
+ case 64:
+ PciIoDevice->PciBar[BarIndex].BarTypeFixed = TRUE;
+ break;
+ default:
+ break;
+ }
+ }
}
break;
@@ -1760,6 +1792,7 @@ PciParseBar ( return Offset + 4;
}
+ PciIoDevice->PciBar[BarIndex].BarTypeFixed = FALSE;
PciIoDevice->PciBar[BarIndex].Offset = (UINT8) Offset;
if ((Value & 0x01) != 0) {
//
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c index 560f8d8a75..b0632d53b8 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c @@ -1072,7 +1072,9 @@ DegradeResource ( ResourceNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink);
NextChildNodeLink = ChildNodeLink->ForwardLink;
- if (ResourceNode->PciDev == PciIoDevice) {
+ if ((ResourceNode->PciDev == PciIoDevice) &&
+ (ResourceNode->Virtual || !PciIoDevice->PciBar[ResourceNode->Bar].BarTypeFixed)
+ ) {
RemoveEntryList (ChildNodeLink);
InsertResourceNode (Mem32Node, ResourceNode);
}
@@ -1086,7 +1088,9 @@ DegradeResource ( ResourceNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink);
NextChildNodeLink = ChildNodeLink->ForwardLink;
- if (ResourceNode->PciDev == PciIoDevice) {
+ if ((ResourceNode->PciDev == PciIoDevice) &&
+ (ResourceNode->Virtual || !PciIoDevice->PciBar[ResourceNode->Bar].BarTypeFixed)
+ ) {
RemoveEntryList (ChildNodeLink);
InsertResourceNode (PMem32Node, ResourceNode);
}
|