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| author | Ruiyu Ni <ruiyu.ni@intel.com> | 2015-12-22 07:13:27 +0000 |
|---|---|---|
| committer | niruiyu <niruiyu@Edk2> | 2015-12-22 07:13:27 +0000 |
| commit | ff3b043f76f1611325984136eef90e8cbf56f394 (patch) | |
| tree | 38f9855d8a7ae4c9fd1fccbb77e4d83f037eb035 /MdeModulePkg | |
| parent | 256aa6d04a59bf8ef5149a1e3c9fe72cf0774111 (diff) | |
| download | edk2-platforms-ff3b043f76f1611325984136eef90e8cbf56f394.tar.xz | |
MdeModulePkg: Add PCD description to MdeModulePkg.uni
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Shumin Qiu <shumin.qiu@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19438 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdeModulePkg')
| -rw-r--r-- | MdeModulePkg/MdeModulePkg.dec | 28 | ||||
| -rw-r--r-- | MdeModulePkg/MdeModulePkg.uni | 35 |
2 files changed, 48 insertions, 15 deletions
diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index e2e0b75cdb..a96229676d 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -983,19 +983,19 @@ # Each array entry is 24-byte in length. The array is terminated
# by an array entry with a PCI Vendor ID of 0xFFFF. If a platform only contains a
# standard 16550 PCI serial device whose class code is 7/0/2, the value is 0xFFFF.
- # The C style structure is defined as below:
- # typedef struct {
- # UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.
- # UINT16 DeviceId; ///< Device ID to match the PCI device
- # UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz
- # UINT64 Offset; ///< The byte offset into to the BAR
- # UINT8 BarIndex; ///< Which BAR to get the UART base address
- # UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.
- # UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
- # UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
- # UINT8 Reserved[2];
- # } PCI_SERIAL_PARAMETER;
- # It contains zero or more instances of the above structure.
+ # The C style structure is defined as below:<BR>
+ # typedef struct {<BR>
+ # UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.<BR>
+ # UINT16 DeviceId; ///< Device ID to match the PCI device.<BR>
+ # UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz.<BR>
+ # UINT64 Offset; ///< The byte offset into to the BAR.<BR>
+ # UINT8 BarIndex; ///< Which BAR to get the UART base address.<BR>
+ # UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.<BR>
+ # UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.<BR>
+ # UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.<BR>
+ # UINT8 Reserved[2];<BR>
+ # } PCI_SERIAL_PARAMETER;<BR>
+ # It contains zero or more instances of the above structure.<BR>
# For example, if a PCI device contains two UARTs, PcdPciSerialParameters needs
# to contain two instances of the above structure, with the VendorId and DeviceId
# equals to the Device ID and Vendor ID of the device; If the PCI device uses the
@@ -1003,7 +1003,7 @@ # BarIndex of second one equals to 1; If the PCI device uses the first BAR to
# support both UARTs, BarIndex of both instance equals to 0, Offset of first
# instance equals to 0 and Offset of second one equals to a value bigger than or
- # equal to 8.
+ # equal to 8.<BR>
# For certain UART whose register needs to be accessed in DWORD aligned address,
# RegisterStride equals to 4.
# @Prompt Pci Serial Parameters
diff --git a/MdeModulePkg/MdeModulePkg.uni b/MdeModulePkg/MdeModulePkg.uni index c026f14534..e473ec3438 100644 --- a/MdeModulePkg/MdeModulePkg.uni +++ b/MdeModulePkg/MdeModulePkg.uni @@ -881,4 +881,37 @@ "FALSE - Not shadow PEIM after memory is ready.<BR>"
#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdShadowPeimOnBoot_PROMPT #language en-US "Shadow Peim on boot"
-
+#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdSerialUseHalfHandshake_PROMPT #language en-US "Enable Serial device Half Hand Shake"
+#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdSerialUseHalfHandshake_HELP #language en-US "Indicates if Serial device uses half hand shake.<BR><BR>\n"
+ "TRUE - Serial device uses half hand shake.<BR>\n"
+ "FALSE - Serial device doesn't use half hand shake.<BR>"
+#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdPciSerialParameters_PROMPT #language en-US "Pci Serial Parameters"
+#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdPciSerialParameters_HELP #language en-US "PCI Serial Parameters. It is an array of VendorID, DeviceID, ClockRate, Offset,\n"
+ "BarIndex, RegisterStride, ReceiveFifoDepth, TransmitFifoDepth information that \n"
+ "describes the parameters of special PCI serial devices.\n"
+ "Each array entry is 24-byte in length. The array is terminated\n"
+ "by an array entry with a PCI Vendor ID of 0xFFFF. If a platform only contains a\n"
+ "standard 16550 PCI serial device whose class code is 7/0/2, the value is 0xFFFF.\n"
+ "The C style structure is defined as below:<BR>\n"
+ "typedef struct {<BR>\n"
+ " UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.<BR>\n"
+ " UINT16 DeviceId; ///< Device ID to match the PCI device<BR>\n"
+ " UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz<BR>\n"
+ " UINT64 Offset; ///< The byte offset into to the BAR<BR>\n"
+ " UINT8 BarIndex; ///< Which BAR to get the UART base address<BR>\n"
+ " UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.<BR>\n"
+ " UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.<BR>\n"
+ " UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.<BR>\n"
+ " UINT8 Reserved[2];<BR>\n"
+ "} PCI_SERIAL_PARAMETER;<BR>\n"
+ "It contains zero or more instances of the above structure.<BR>\n"
+ "For example, if a PCI device contains two UARTs, PcdPciSerialParameters needs\n"
+ "to contain two instances of the above structure, with the VendorId and DeviceId\n"
+ "equals to the Device ID and Vendor ID of the device; If the PCI device uses the\n"
+ "first two BARs to support two UARTs, BarIndex of first instance equals to 0 and\n"
+ "BarIndex of second one equals to 1; If the PCI device uses the first BAR to\n"
+ "support both UARTs, BarIndex of both instance equals to 0, Offset of first\n"
+ "instance equals to 0 and Offset of second one equals to a value bigger than or\n"
+ "equal to 8.<BR>\n"
+ "For certain UART whose register needs to be accessed in DWORD aligned address,\n"
+ "RegisterStride equals to 4.\n"
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