diff options
| author | bbahnsen <bbahnsen@6f19259b-4bc3-4df7-8a09-765794883524> | 2006-04-21 22:54:32 +0000 |
|---|---|---|
| committer | bbahnsen <bbahnsen@6f19259b-4bc3-4df7-8a09-765794883524> | 2006-04-21 22:54:32 +0000 |
| commit | 878ddf1fc3540a715f63594ed22b6929e881afb4 (patch) | |
| tree | c56c44dac138137b510e1fba7c3efe5e4d84bea2 /MdePkg/Include/IndustryStandard | |
| download | edk2-platforms-878ddf1fc3540a715f63594ed22b6929e881afb4.tar.xz | |
Initial import.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@3 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdePkg/Include/IndustryStandard')
| -rw-r--r-- | MdePkg/Include/IndustryStandard/Acpi.h | 91 | ||||
| -rw-r--r-- | MdePkg/Include/IndustryStandard/Usb.h | 282 | ||||
| -rw-r--r-- | MdePkg/Include/IndustryStandard/pci22.h | 481 | ||||
| -rw-r--r-- | MdePkg/Include/IndustryStandard/scsi.h | 282 |
4 files changed, 1136 insertions, 0 deletions
diff --git a/MdePkg/Include/IndustryStandard/Acpi.h b/MdePkg/Include/IndustryStandard/Acpi.h new file mode 100644 index 0000000000..d2fe3459c2 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Acpi.h @@ -0,0 +1,91 @@ +/** @file
+ This file contains some basic ACPI definitions that are consumed by drivers
+ that do not care about ACPI versions.
+
+ Copyright (c) 2006, Intel Corporation
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Module Name: Acpi.h
+
+**/
+
+#ifndef _ACPI_H_
+#define _ACPI_H_
+
+//
+// Common table header, this prefaces all ACPI tables, including FACS, but
+// excluding the RSD PTR structure
+//
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_COMMON_HEADER;
+
+//
+// Common ACPI description table header. This structure prefaces most ACPI tables.
+//
+#pragma pack(1)
+
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT8 Revision;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT64 OemTableId;
+ UINT32 OemRevision;
+ UINT32 CreatorId;
+ UINT32 CreatorRevision;
+} EFI_ACPI_DESCRIPTION_HEADER;
+
+#pragma pack()
+//
+// Define for Pci Host Bridge Resource Allocation
+//
+#define ACPI_ADDRESS_SPACE_DESCRIPTOR 0x8A
+#define ACPI_END_TAG_DESCRIPTOR 0x79
+
+#define ACPI_ADDRESS_SPACE_TYPE_MEM 0x00
+#define ACPI_ADDRESS_SPACE_TYPE_IO 0x01
+#define ACPI_ADDRESS_SPACE_TYPE_BUS 0x02
+
+//
+// Make sure structures match spec
+//
+#pragma pack(1)
+
+typedef struct {
+ UINT8 Desc;
+ UINT16 Len;
+ UINT8 ResType;
+ UINT8 GenFlag;
+ UINT8 SpecificFlag;
+ UINT64 AddrSpaceGranularity;
+ UINT64 AddrRangeMin;
+ UINT64 AddrRangeMax;
+ UINT64 AddrTranslationOffset;
+ UINT64 AddrLen;
+} EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR;
+
+typedef struct {
+ UINT8 Desc;
+ UINT8 Checksum;
+} EFI_ACPI_END_TAG_DESCRIPTOR;
+
+//
+// General use definitions
+//
+#define EFI_ACPI_RESERVED_BYTE 0x00
+#define EFI_ACPI_RESERVED_WORD 0x0000
+#define EFI_ACPI_RESERVED_DWORD 0x00000000
+#define EFI_ACPI_RESERVED_QWORD 0x0000000000000000
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/Usb.h b/MdePkg/Include/IndustryStandard/Usb.h new file mode 100644 index 0000000000..dca7351ff1 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Usb.h @@ -0,0 +1,282 @@ +/** @file
+ Support for USB 1.1 standard.
+
+ Copyright (c) 2006, Intel Corporation
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Module Name: Usb.h
+
+**/
+
+#ifndef __USB_H__
+#define __USB_H__
+
+//
+// USB Descriptor types
+//
+#define USB_DT_DEVICE 0x01
+#define USB_DT_CONFIG 0x02
+#define USB_DT_STRING 0x03
+#define USB_DT_INTERFACE 0x04
+#define USB_DT_ENDPOINT 0x05
+#define USB_DT_HUB 0x29
+#define USB_DT_HID 0x21
+
+//
+// USB request type
+//
+#define USB_TYPE_STANDARD (0x00 << 5)
+#define USB_TYPE_CLASS (0x01 << 5)
+#define USB_TYPE_VENDOR (0x02 << 5)
+#define USB_TYPE_RESERVED (0x03 << 5)
+
+//
+// USB request targer device
+//
+#define USB_RECIP_DEVICE 0x00
+#define USB_RECIP_INTERFACE 0x01
+#define USB_RECIP_ENDPOINT 0x02
+#define USB_RECIP_OTHER 0x03
+
+//
+// Request target types.
+//
+#define USB_RT_DEVICE 0x00
+#define USB_RT_INTERFACE 0x01
+#define USB_RT_ENDPOINT 0x02
+#define USB_RT_HUB (USB_TYPE_CLASS | USB_RECIP_DEVICE)
+#define USB_RT_PORT (USB_TYPE_CLASS | USB_RECIP_OTHER)
+
+//
+// USB Transfer Results
+//
+#define EFI_USB_NOERROR 0x00
+#define EFI_USB_ERR_NOTEXECUTE 0x01
+#define EFI_USB_ERR_STALL 0x02
+#define EFI_USB_ERR_BUFFER 0x04
+#define EFI_USB_ERR_BABBLE 0x08
+#define EFI_USB_ERR_NAK 0x10
+#define EFI_USB_ERR_CRC 0x20
+#define EFI_USB_ERR_TIMEOUT 0x40
+#define EFI_USB_ERR_BITSTUFF 0x80
+#define EFI_USB_ERR_SYSTEM 0x100
+
+//
+//Use 200 ms to increase the error handling response time
+//
+#define EFI_USB_INTERRUPT_DELAY 2000000
+
+//
+// USB transation direction
+//
+typedef enum {
+ EfiUsbDataOut,
+ EfiUsbDataIn,
+ EfiUsbNoData
+} EFI_USB_DATA_DIRECTION;
+
+//
+// Usb Data recipient type
+//
+typedef enum {
+ EfiUsbDevice,
+ EfiUsbInterface,
+ EfiUsbEndpoint
+} EFI_USB_RECIPIENT;
+
+typedef enum {
+ EfiUsbEndpointHalt,
+ EfiUsbDeviceRemoteWakeup
+} EFI_USB_STANDARD_FEATURE_SELECTOR;
+
+#pragma pack(1)
+//
+// Usb device request structure
+//
+typedef struct {
+ UINT8 RequestType;
+ UINT8 Request;
+ UINT16 Value;
+ UINT16 Index;
+ UINT16 Length;
+} EFI_USB_DEVICE_REQUEST;
+
+//
+// Standard USB request
+//
+#define USB_DEV_GET_STATUS 0x00
+
+#define USB_DEV_CLEAR_FEATURE 0x01
+
+#define USB_DEV_SET_FEATURE 0x03
+
+#define USB_DEV_SET_ADDRESS 0x05
+#define USB_DEV_SET_ADDRESS_REQ_TYPE 0x00
+
+#define USB_DEV_GET_DESCRIPTOR 0x06
+#define USB_DEV_GET_DESCRIPTOR_REQ_TYPE 0x80
+
+#define USB_DEV_SET_DESCRIPTOR 0x07
+#define USB_DEV_SET_DESCRIPTOR_REQ_TYPE 0x00
+
+#define USB_DEV_GET_CONFIGURATION 0x08
+#define USB_DEV_GET_CONFIGURATION_REQ_TYPE 0x80
+
+#define USB_DEV_SET_CONFIGURATION 0x09
+#define USB_DEV_SET_CONFIGURATION_REQ_TYPE 0x00
+
+#define USB_DEV_GET_INTERFACE 0x0A
+#define USB_DEV_GET_INTERFACE_REQ_TYPE 0x81
+
+#define USB_DEV_SET_INTERFACE 0x0B
+#define USB_DEV_SET_INTERFACE_REQ_TYPE 0x01
+
+#define USB_DEV_SYNCH_FRAME 0x0C
+#define USB_DEV_SYNCH_FRAME_REQ_TYPE 0x82
+
+//
+// Device descriptor. refer USB1.1
+//
+typedef struct usb_device_descriptor {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT16 BcdUSB;
+ UINT8 DeviceClass;
+ UINT8 DeviceSubClass;
+ UINT8 DeviceProtocol;
+ UINT8 MaxPacketSize0;
+ UINT16 IdVendor;
+ UINT16 IdProduct;
+ UINT16 BcdDevice;
+ UINT8 StrManufacturer;
+ UINT8 StrProduct;
+ UINT8 StrSerialNumber;
+ UINT8 NumConfigurations;
+} EFI_USB_DEVICE_DESCRIPTOR;
+
+//
+// Endpoint descriptor
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT8 EndpointAddress;
+ UINT8 Attributes;
+ UINT16 MaxPacketSize;
+ UINT8 Interval;
+} EFI_USB_ENDPOINT_DESCRIPTOR;
+
+//
+// Interface descriptor
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT8 InterfaceNumber;
+ UINT8 AlternateSetting;
+ UINT8 NumEndpoints;
+ UINT8 InterfaceClass;
+ UINT8 InterfaceSubClass;
+ UINT8 InterfaceProtocol;
+ UINT8 Interface;
+} EFI_USB_INTERFACE_DESCRIPTOR;
+
+//
+// USB alternate setting
+//
+typedef struct {
+ EFI_USB_INTERFACE_DESCRIPTOR *Interface;
+} USB_ALT_SETTING;
+
+//
+// Configuration descriptor
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT16 TotalLength;
+ UINT8 NumInterfaces;
+ UINT8 ConfigurationValue;
+ UINT8 Configuration;
+ UINT8 Attributes;
+ UINT8 MaxPower;
+} EFI_USB_CONFIG_DESCRIPTOR;
+
+//
+// Supported String Languages
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT16 SupportedLanID[1];
+} EFI_USB_SUPPORTED_LANGUAGES;
+
+//
+// String descriptor
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ CHAR16 String[1];
+} EFI_USB_STRING_DESCRIPTOR;
+
+//
+// Hub descriptor
+//
+#define MAXBYTES 8
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT8 NbrPorts;
+ UINT8 HubCharacteristics[2];
+ UINT8 PwrOn2PwrGood;
+ UINT8 HubContrCurrent;
+ UINT8 Filler[MAXBYTES];
+} EFI_USB_HUB_DESCRIPTOR;
+
+typedef struct {
+ UINT16 PortStatus;
+ UINT16 PortChangeStatus;
+} EFI_USB_PORT_STATUS;
+
+//
+// Constant value for Port Status & Port Change Status
+//
+#define USB_PORT_STAT_CONNECTION 0x0001
+#define USB_PORT_STAT_ENABLE 0x0002
+#define USB_PORT_STAT_SUSPEND 0x0004
+#define USB_PORT_STAT_OVERCURRENT 0x0008
+#define USB_PORT_STAT_RESET 0x0010
+#define USB_PORT_STAT_POWER 0x0100
+#define USB_PORT_STAT_LOW_SPEED 0x0200
+
+#define USB_PORT_STAT_C_CONNECTION 0x0001
+#define USB_PORT_STAT_C_ENABLE 0x0002
+#define USB_PORT_STAT_C_SUSPEND 0x0004
+#define USB_PORT_STAT_C_OVERCURRENT 0x0008
+#define USB_PORT_STAT_C_RESET 0x0010
+
+//
+// Used for set/clear port feature request
+//
+typedef enum {
+ EfiUsbPortEnable = 1,
+ EfiUsbPortSuspend = 2,
+ EfiUsbPortReset = 4,
+ EfiUsbPortPower = 8,
+ EfiUsbPortConnectChange = 16,
+ EfiUsbPortEnableChange = 17,
+ EfiUsbPortSuspendChange = 18,
+ EfiUsbPortOverCurrentChange = 19,
+ EfiUsbPortResetChange = 20
+} EFI_USB_PORT_FEATURE;
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/pci22.h b/MdePkg/Include/IndustryStandard/pci22.h new file mode 100644 index 0000000000..7fee279e80 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/pci22.h @@ -0,0 +1,481 @@ +/** @file
+ Support for PCI 2.2 standard.
+
+ Copyright (c) 2006, Intel Corporation
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Module Name: pci22.h
+
+**/
+
+#ifndef _PCI22_H
+#define _PCI22_H
+
+#define PCI_MAX_SEGMENT 0
+
+#define PCI_MAX_BUS 255
+
+#define PCI_MAX_DEVICE 31
+#define PCI_MAX_FUNC 7
+
+//
+// Command
+//
+#define PCI_VGA_PALETTE_SNOOP_DISABLED 0x20
+
+#pragma pack(push, 1)
+typedef struct {
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT16 Command;
+ UINT16 Status;
+ UINT8 RevisionID;
+ UINT8 ClassCode[3];
+ UINT8 CacheLineSize;
+ UINT8 LatencyTimer;
+ UINT8 HeaderType;
+ UINT8 BIST;
+} PCI_DEVICE_INDEPENDENT_REGION;
+
+typedef struct {
+ UINT32 Bar[6];
+ UINT32 CISPtr;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemID;
+ UINT32 ExpansionRomBar;
+ UINT8 CapabilityPtr;
+ UINT8 Reserved1[3];
+ UINT32 Reserved2;
+ UINT8 InterruptLine;
+ UINT8 InterruptPin;
+ UINT8 MinGnt;
+ UINT8 MaxLat;
+} PCI_DEVICE_HEADER_TYPE_REGION;
+
+typedef struct {
+ PCI_DEVICE_INDEPENDENT_REGION Hdr;
+ PCI_DEVICE_HEADER_TYPE_REGION Device;
+} PCI_TYPE00;
+
+typedef struct {
+ UINT32 Bar[2];
+ UINT8 PrimaryBus;
+ UINT8 SecondaryBus;
+ UINT8 SubordinateBus;
+ UINT8 SecondaryLatencyTimer;
+ UINT8 IoBase;
+ UINT8 IoLimit;
+ UINT16 SecondaryStatus;
+ UINT16 MemoryBase;
+ UINT16 MemoryLimit;
+ UINT16 PrefetchableMemoryBase;
+ UINT16 PrefetchableMemoryLimit;
+ UINT32 PrefetchableBaseUpper32;
+ UINT32 PrefetchableLimitUpper32;
+ UINT16 IoBaseUpper16;
+ UINT16 IoLimitUpper16;
+ UINT8 CapabilityPtr;
+ UINT8 Reserved[3];
+ UINT32 ExpansionRomBAR;
+ UINT8 InterruptLine;
+ UINT8 InterruptPin;
+ UINT16 BridgeControl;
+} PCI_BRIDGE_CONTROL_REGISTER;
+
+typedef struct {
+ PCI_DEVICE_INDEPENDENT_REGION Hdr;
+ PCI_BRIDGE_CONTROL_REGISTER Bridge;
+} PCI_TYPE01;
+
+typedef union {
+ PCI_TYPE00 Device;
+ PCI_TYPE01 Bridge;
+} PCI_TYPE_GENERIC;
+
+typedef struct {
+ UINT32 CardBusSocketReg; // Cardus Socket/ExCA Base
+ // Address Register
+ //
+ UINT16 Reserved;
+ UINT16 SecondaryStatus; // Secondary Status
+ UINT8 PciBusNumber; // PCI Bus Number
+ UINT8 CardBusBusNumber; // CardBus Bus Number
+ UINT8 SubordinateBusNumber; // Subordinate Bus Number
+ UINT8 CardBusLatencyTimer; // CardBus Latency Timer
+ UINT32 MemoryBase0; // Memory Base Register 0
+ UINT32 MemoryLimit0; // Memory Limit Register 0
+ UINT32 MemoryBase1;
+ UINT32 MemoryLimit1;
+ UINT32 IoBase0;
+ UINT32 IoLimit0; // I/O Base Register 0
+ UINT32 IoBase1; // I/O Limit Register 0
+ UINT32 IoLimit1;
+ UINT8 InterruptLine; // Interrupt Line
+ UINT8 InterruptPin; // Interrupt Pin
+ UINT16 BridgeControl; // Bridge Control
+} PCI_CARDBUS_CONTROL_REGISTER;
+
+//
+// Definitions of PCI class bytes and manipulation macros.
+//
+#define PCI_CLASS_OLD 0x00
+#define PCI_CLASS_OLD_OTHER 0x00
+#define PCI_CLASS_OLD_VGA 0x01
+
+#define PCI_CLASS_MASS_STORAGE 0x01
+#define PCI_CLASS_MASS_STORAGE_SCSI 0x00
+#define PCI_CLASS_MASS_STORAGE_IDE 0x01 // obsolete
+#define PCI_CLASS_IDE 0x01
+#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
+#define PCI_CLASS_MASS_STORAGE_IPI 0x03
+#define PCI_CLASS_MASS_STORAGE_RAID 0x04
+#define PCI_CLASS_MASS_STORAGE_OTHER 0x80
+
+#define PCI_CLASS_NETWORK 0x02
+#define PCI_CLASS_NETWORK_ETHERNET 0x00
+#define PCI_CLASS_ETHERNET 0x00 // obsolete
+#define PCI_CLASS_NETWORK_TOKENRING 0x01
+#define PCI_CLASS_NETWORK_FDDI 0x02
+#define PCI_CLASS_NETWORK_ATM 0x03
+#define PCI_CLASS_NETWORK_ISDN 0x04
+#define PCI_CLASS_NETWORK_OTHER 0x80
+
+#define PCI_CLASS_DISPLAY 0x03
+#define PCI_CLASS_DISPLAY_CTRL 0x03 // obsolete
+#define PCI_CLASS_DISPLAY_VGA 0x00
+#define PCI_CLASS_VGA 0x00 // obsolete
+#define PCI_CLASS_DISPLAY_XGA 0x01
+#define PCI_CLASS_DISPLAY_3D 0x02
+#define PCI_CLASS_DISPLAY_OTHER 0x80
+#define PCI_CLASS_DISPLAY_GFX 0x80
+#define PCI_CLASS_GFX 0x80 // obsolete
+#define PCI_CLASS_BRIDGE 0x06
+#define PCI_CLASS_BRIDGE_HOST 0x00
+#define PCI_CLASS_BRIDGE_ISA 0x01
+#define PCI_CLASS_ISA 0x01 // obsolete
+#define PCI_CLASS_BRIDGE_EISA 0x02
+#define PCI_CLASS_BRIDGE_MCA 0x03
+#define PCI_CLASS_BRIDGE_P2P 0x04
+#define PCI_CLASS_BRIDGE_PCMCIA 0x05
+#define PCI_CLASS_BRIDGE_NUBUS 0x06
+#define PCI_CLASS_BRIDGE_CARDBUS 0x07
+#define PCI_CLASS_BRIDGE_RACEWAY 0x08
+#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
+#define PCI_CLASS_ISA_POSITIVE_DECODE 0x80 // obsolete
+#define PCI_CLASS_SERIAL 0x0C
+#define PCI_CLASS_SERIAL_FIREWIRE 0x00
+#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
+#define PCI_CLASS_SERIAL_SSA 0x02
+#define PCI_CLASS_SERIAL_USB 0x03
+#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
+#define PCI_CLASS_SERIAL_SMB 0x05
+
+#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
+#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
+#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
+
+#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
+#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)
+#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)
+#define IS_PCI_GFX(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)
+#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
+#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
+#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
+#define IS_PCI_SCSI(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)
+#define IS_PCI_RAID(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)
+#define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)
+#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)
+#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)
+#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
+
+#define HEADER_TYPE_DEVICE 0x00
+#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
+#define HEADER_TYPE_CARDBUS_BRIDGE 0x02
+
+#define HEADER_TYPE_MULTI_FUNCTION 0x80
+#define HEADER_LAYOUT_CODE 0x7f
+
+#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
+#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
+#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
+
+#define PCI_DEVICE_ROMBAR 0x30
+#define PCI_BRIDGE_ROMBAR 0x38
+
+#define PCI_MAX_BAR 6
+#define PCI_MAX_CONFIG_OFFSET 0x100
+//
+// bugbug: this is supported in PCI spec v2.3
+//
+#define PCI_EXP_MAX_CONFIG_OFFSET 0x1000
+
+#define PCI_VENDOR_ID_OFFSET 0x00
+#define PCI_DEVICE_ID_OFFSET 0x02
+#define PCI_COMMAND_OFFSET 0x04
+#define PCI_PRIMARY_STATUS_OFFSET 0x06
+#define PCI_REVISION_ID_OFFSET 0x08
+#define PCI_CLASSCODE_OFFSET 0x09
+#define PCI_CACHELINE_SIZE_OFFSET 0x0C
+#define PCI_LATENCY_TIMER_OFFSET 0x0D
+#define PCI_HEADER_TYPE_OFFSET 0x0E
+#define PCI_BIST_OFFSET 0x0F
+
+#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
+#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
+
+#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
+#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
+#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
+
+typedef struct {
+ UINT8 Register;
+ UINT8 Function;
+ UINT8 Device;
+ UINT8 Bus;
+ UINT8 Reserved[4];
+} DEFIO_PCI_ADDR;
+
+typedef union {
+ struct {
+ UINT32 Reg : 8;
+ UINT32 Func : 3;
+ UINT32 Dev : 5;
+ UINT32 Bus : 8;
+ UINT32 Reserved : 7;
+ UINT32 Enable : 1;
+ } Bits;
+ UINT32 Uint32;
+} PCI_CONFIG_ACCESS_CF8;
+
+#pragma pack()
+
+#define EFI_ROOT_BRIDGE_LIST 'eprb'
+#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
+#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1
+#define PCI_DATA_STRUCTURE_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'I', 'R')
+#define PCI_CODE_TYPE_PCAT_IMAGE 0x00
+#define PCI_CODE_TYPE_EFI_IMAGE 0x03
+#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001
+
+#define EFI_PCI_COMMAND_IO_SPACE 0x0001
+#define EFI_PCI_COMMAND_MEMORY_SPACE 0x0002
+#define EFI_PCI_COMMAND_BUS_MASTER 0x0004
+#define EFI_PCI_COMMAND_SPECIAL_CYCLE 0x0008
+#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE 0x0010
+#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP 0x0020
+#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND 0x0040
+#define EFI_PCI_COMMAND_STEPPING_CONTROL 0x0080
+#define EFI_PCI_COMMAND_SERR 0x0100
+#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK 0x0200
+
+#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE 0x0001
+#define EFI_PCI_BRIDGE_CONTROL_SERR 0x0002
+#define EFI_PCI_BRIDGE_CONTROL_ISA 0x0004
+#define EFI_PCI_BRIDGE_CONTROL_VGA 0x0008
+#define EFI_PCI_BRIDGE_CONTROL_VGA_16 0x0010
+#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT 0x0020
+#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS 0x0040
+#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK 0x0080
+#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER 0x0100
+#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER 0x0200
+#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS 0x0400
+#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR 0x0800
+
+//
+// Following are the PCI-CARDBUS bridge control bit
+//
+#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE 0x0080
+#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE 0x0100
+#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE 0x0200
+#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400
+
+//
+// Following are the PCI status control bit
+//
+#define EFI_PCI_STATUS_CAPABILITY 0x0010
+#define EFI_PCI_STATUS_66MZ_CAPABLE 0x0020
+#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE 0x0080
+#define EFI_PCI_MASTER_DATA_PARITY_ERROR 0x0100
+
+#define EFI_PCI_CAPABILITY_PTR 0x34
+#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
+
+#pragma pack(1)
+typedef struct {
+ UINT16 Signature; // 0xaa55
+ UINT8 Reserved[0x16];
+ UINT16 PcirOffset;
+} PCI_EXPANSION_ROM_HEADER;
+
+typedef struct {
+ UINT16 Signature; // 0xaa55
+ UINT16 InitializationSize;
+ UINT32 EfiSignature; // 0x0EF1
+ UINT16 EfiSubsystem;
+ UINT16 EfiMachineType;
+ UINT16 CompressionType;
+ UINT8 Reserved[8];
+ UINT16 EfiImageHeaderOffset;
+ UINT16 PcirOffset;
+} EFI_PCI_EXPANSION_ROM_HEADER;
+
+typedef struct {
+ UINT16 Signature; // 0xaa55
+ UINT8 Size512;
+ UINT8 Reserved[15];
+ UINT16 PcirOffset;
+} EFI_LEGACY_EXPANSION_ROM_HEADER;
+
+typedef union {
+ UINT8 *Raw;
+ PCI_EXPANSION_ROM_HEADER *Generic;
+ EFI_PCI_EXPANSION_ROM_HEADER *Efi;
+ EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;
+} EFI_PCI_ROM_HEADER;
+
+typedef struct {
+ UINT32 Signature; // "PCIR"
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT16 Reserved0;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT8 ClassCode[3];
+ UINT16 ImageLength;
+ UINT16 CodeRevision;
+ UINT8 CodeType;
+ UINT8 Indicator;
+ UINT16 Reserved1;
+} PCI_DATA_STRUCTURE;
+
+//
+// PCI Capability List IDs and records
+//
+#define EFI_PCI_CAPABILITY_ID_PMI 0x01
+#define EFI_PCI_CAPABILITY_ID_AGP 0x02
+#define EFI_PCI_CAPABILITY_ID_VPD 0x03
+#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
+#define EFI_PCI_CAPABILITY_ID_MSI 0x05
+#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
+#define EFI_PCI_CAPABILITY_ID_PCIX 0x07
+//
+// bugbug: this ID is defined in PCI spec v2.3
+//
+#define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10
+
+typedef struct {
+ UINT8 CapabilityID;
+ UINT8 NextItemPtr;
+} EFI_PCI_CAPABILITY_HDR;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_PMI
+//
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 PMC;
+ UINT16 PMCSR;
+ UINT8 BridgeExtention;
+ UINT8 Data;
+} EFI_PCI_CAPABILITY_PMI;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_AGP
+//
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT8 Rev;
+ UINT8 Reserved;
+ UINT32 Status;
+ UINT32 Command;
+} EFI_PCI_CAPABILITY_AGP;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_VPD
+//
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 AddrReg;
+ UINT32 DataReg;
+} EFI_PCI_CAPABILITY_VPD;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_SLOTID
+//
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT8 ExpnsSlotReg;
+ UINT8 ChassisNo;
+} EFI_PCI_CAPABILITY_SLOTID;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_MSI
+//
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 MsgCtrlReg;
+ UINT32 MsgAddrReg;
+ UINT16 MsgDataReg;
+} EFI_PCI_CAPABILITY_MSI32;
+
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 MsgCtrlReg;
+ UINT32 MsgAddrRegLsdw;
+ UINT32 MsgAddrRegMsdw;
+ UINT16 MsgDataReg;
+} EFI_PCI_CAPABILITY_MSI64;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG
+//
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ //
+ // not finished - fields need to go here
+ //
+} EFI_PCI_CAPABILITY_HOTPLUG;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_PCIX
+//
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 CommandReg;
+ UINT32 StatusReg;
+} EFI_PCI_CAPABILITY_PCIX;
+
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 SecStatusReg;
+ UINT32 StatusReg;
+ UINT32 SplitTransCtrlRegUp;
+ UINT32 SplitTransCtrlRegDn;
+} EFI_PCI_CAPABILITY_PCIX_BRDG;
+
+#define DEVICE_ID_NOCARE 0xFFFF
+
+#define PCI_ACPI_UNUSED 0
+#define PCI_BAR_NOCHANGE 0
+#define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL
+#define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
+#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
+#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
+
+#define PCI_BAR_IDX0 0x00
+#define PCI_BAR_IDX1 0x01
+#define PCI_BAR_IDX2 0x02
+#define PCI_BAR_IDX3 0x03
+#define PCI_BAR_IDX4 0x04
+#define PCI_BAR_IDX5 0x05
+#define PCI_BAR_ALL 0xFF
+
+#pragma pack(pop)
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/scsi.h b/MdePkg/Include/IndustryStandard/scsi.h new file mode 100644 index 0000000000..41023094f5 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/scsi.h @@ -0,0 +1,282 @@ +/** @file
+ support for SCSI standard
+
+ Copyright (c) 2006, Intel Corporation
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Module Name: scsi.h
+
+**/
+
+#ifndef _SCSI_H
+#define _SCSI_H
+
+//
+// SCSI command OP Code
+//
+//
+// Commands for all device types
+//
+#define EFI_SCSI_OP_CHANGE_DEFINITION 0x40
+#define EFI_SCSI_OP_COMPARE 0x39
+#define EFI_SCSI_OP_COPY 0x18
+#define EFI_SCSI_OP_COPY_VERIFY 0x3a
+#define EFI_SCSI_OP_INQUIRY 0x12
+#define EFI_SCSI_OP_LOG_SELECT 0x4c
+#define EFI_SCSI_OP_LOG_SENSE 0x4d
+#define EFI_SCSI_OP_MODE_SEL6 0x15
+#define EFI_SCSI_OP_MODE_SEL10 0x55
+#define EFI_SCSI_OP_MODE_SEN6 0x1a
+#define EFI_SCSI_OP_MODE_SEN10 0x5a
+#define EFI_SCSI_OP_READ_BUFFER 0x3c
+#define EFI_SCSI_OP_REQUEST_SENSE 0x03
+#define EFI_SCSI_OP_SEND_DIAG 0x1d
+#define EFI_SCSI_OP_TEST_UNIT_READY 0x00
+#define EFI_SCSI_OP_WRITE_BUFF 0x3b
+
+//
+// Commands unique to Direct Access Devices
+//
+#define EFI_SCSI_OP_COMPARE 0x39
+#define EFI_SCSI_OP_FORMAT 0x04
+#define EFI_SCSI_OP_LOCK_UN_CACHE 0x36
+#define EFI_SCSI_OP_PREFETCH 0x34
+#define EFI_SCSI_OP_MEDIA_REMOVAL 0x1e
+#define EFI_SCSI_OP_READ6 0x08
+#define EFI_SCSI_OP_READ10 0x28
+#define EFI_SCSI_OP_READ_CAPACITY 0x25
+#define EFI_SCSI_OP_READ_DEFECT 0x37
+#define EFI_SCSI_OP_READ_LONG 0x3e
+#define EFI_SCSI_OP_REASSIGN_BLK 0x07
+#define EFI_SCSI_OP_RECEIVE_DIAG 0x1c
+#define EFI_SCSI_OP_RELEASE 0x17
+#define EFI_SCSI_OP_REZERO 0x01
+#define EFI_SCSI_OP_SEARCH_DATA_E 0x31
+#define EFI_SCSI_OP_SEARCH_DATA_H 0x30
+#define EFI_SCSI_OP_SEARCH_DATA_L 0x32
+#define EFI_SCSI_OP_SEEK6 0x0b
+#define EFI_SCSI_OP_SEEK10 0x2b
+#define EFI_SCSI_OP_SEND_DIAG 0x1d
+#define EFI_SCSI_OP_SET_LIMIT 0x33
+#define EFI_SCSI_OP_START_STOP_UNIT 0x1b
+#define EFI_SCSI_OP_SYNC_CACHE 0x35
+#define EFI_SCSI_OP_VERIFY 0x2f
+#define EFI_SCSI_OP_WRITE6 0x0a
+#define EFI_SCSI_OP_WRITE10 0x2a
+#define EFI_SCSI_OP_WRITE_VERIFY 0x2e
+#define EFI_SCSI_OP_WRITE_LONG 0x3f
+#define EFI_SCSI_OP_WRITE_SAME 0x41
+
+//
+// Commands unique to Sequential Access Devices
+//
+#define EFI_SCSI_OP_ERASE 0x19
+#define EFI_SCSI_OP_LOAD_UNLOAD 0x1b
+#define EFI_SCSI_OP_LOCATE 0x2b
+#define EFI_SCSI_OP_READ_BLOCK_LIMIT 0x05
+#define EFI_SCSI_OP_READ_POS 0x34
+#define EFI_SCSI_OP_READ_REVERSE 0x0f
+#define EFI_SCSI_OP_RECOVER_BUF_DATA 0x14
+#define EFI_SCSI_OP_RESERVE_UNIT 0x16
+#define EFI_SCSI_OP_REWIND 0x01
+#define EFI_SCSI_OP_SPACE 0x11
+#define EFI_SCSI_OP_VERIFY_TAPE 0x13
+#define EFI_SCSI_OP_WRITE_FILEMARK 0x10
+
+//
+// Commands unique to Printer Devices
+//
+#define EFI_SCSI_OP_PRINT 0x0a
+#define EFI_SCSI_OP_SLEW_PRINT 0x0b
+#define EFI_SCSI_OP_STOP_PRINT 0x1b
+#define EFI_SCSI_OP_SYNC_BUFF 0x10
+
+//
+// Commands unique to Processor Devices
+//
+#define EFI_SCSI_OP_RECEIVE 0x08
+#define EFI_SCSI_OP_SEND 0x0a
+
+//
+// Commands unique to Write-Once Devices
+//
+#define EFI_SCSI_OP_MEDIUM_SCAN 0x38
+#define EFI_SCSI_OP_SEARCH_DAT_E10 0x31
+#define EFI_SCSI_OP_SEARCH_DAT_E12 0xb1
+#define EFI_SCSI_OP_SEARCH_DAT_H10 0x30
+#define EFI_SCSI_OP_SEARCH_DAT_H12 0xb0
+#define EFI_SCSI_OP_SEARCH_DAT_L10 0x32
+#define EFI_SCSI_OP_SEARCH_DAT_L12 0xb2
+#define EFI_SCSI_OP_SET_LIMIT10 0x33
+#define EFI_SCSI_OP_SET_LIMIT12 0xb3
+#define EFI_SCSI_OP_VERIFY10 0x2f
+#define EFI_SCSI_OP_VERIFY12 0xaf
+#define EFI_SCSI_OP_WRITE12 0xaa
+#define EFI_SCSI_OP_WRITE_VERIFY10 0x2e
+#define EFI_SCSI_OP_WRITE_VERIFY12 0xae
+
+//
+// Commands unique to CD-ROM Devices
+//
+#define EFI_SCSI_OP_PLAY_AUD_10 0x45
+#define EFI_SCSI_OP_PLAY_AUD_12 0xa5
+#define EFI_SCSI_OP_PLAY_AUD_MSF 0x47
+#define EFI_SCSI_OP_PLAY_AUD_TKIN 0x48
+#define EFI_SCSI_OP_PLAY_TK_REL10 0x49
+#define EFI_SCSI_OP_PLAY_TK_REL12 0xa9
+#define EFI_SCSI_OP_READ_CD_CAPACITY 0x25
+#define EFI_SCSI_OP_READ_HEADER 0x44
+#define EFI_SCSI_OP_READ_SUB_CHANNEL 0x42
+#define EFI_SCSI_OP_READ_TOC 0x43
+
+//
+// Commands unique to Scanner Devices
+//
+#define EFI_SCSI_OP_GET_DATABUFF_STAT 0x34
+#define EFI_SCSI_OP_GET_WINDOW 0x25
+#define EFI_SCSI_OP_OBJECT_POS 0x31
+#define EFI_SCSI_OP_SCAN 0x1b
+#define EFI_SCSI_OP_SET_WINDOW 0x24
+
+//
+// Commands unique to Optical Memory Devices
+//
+#define EFI_SCSI_OP_UPDATE_BLOCK 0x3d
+
+//
+// Commands unique to Medium Changer Devices
+//
+#define EFI_SCSI_OP_EXCHANGE_MEDIUM 0xa6
+#define EFI_SCSI_OP_INIT_ELEMENT_STAT 0x07
+#define EFI_SCSI_OP_POS_TO_ELEMENT 0x2b
+#define EFI_SCSI_OP_REQUEST_VE_ADDR 0xb5
+#define EFI_SCSI_OP_SEND_VOL_TAG 0xb6
+
+//
+// Commands unique to Communition Devices
+//
+#define EFI_SCSI_OP_GET_MESSAGE6 0x08
+#define EFI_SCSI_OP_GET_MESSAGE10 0x28
+#define EFI_SCSI_OP_GET_MESSAGE12 0xa8
+#define EFI_SCSI_OP_SEND_MESSAGE6 0x0a
+#define EFI_SCSI_OP_SEND_MESSAGE10 0x2a
+#define EFI_SCSI_OP_SEND_MESSAGE12 0xaa
+
+//
+// SCSI Data Transfer Direction
+//
+#define EFI_SCSI_DATA_IN 0
+#define EFI_SCSI_DATA_OUT 1
+
+//
+// Peripheral Device Type Definitions
+//
+#define EFI_SCSI_TYPE_DISK 0x00 // Disk device
+#define EFI_SCSI_TYPE_TAPE 0x01 // Tape device
+#define EFI_SCSI_TYPE_PRINTER 0x02 // Printer
+#define EFI_SCSI_TYPE_PROCESSOR 0x03 // Processor
+#define EFI_SCSI_TYPE_WORM 0x04 // Write-once read-multiple
+#define EFI_SCSI_TYPE_CDROM 0x05 // CD-ROM device
+#define EFI_SCSI_TYPE_SCANNER 0x06 // Scanner device
+#define EFI_SCSI_TYPE_OPTICAL 0x07 // Optical memory device
+#define EFI_SCSI_TYPE_MEDIUMCHANGER 0x08 // Medium Changer device
+#define EFI_SCSI_TYPE_COMMUNICATION 0x09 // Communications device
+#define EFI_SCSI_TYPE_RESERVED_LOW 0x0A // Reserved (low)
+#define EFI_SCSI_TYPE_RESERVED_HIGH 0x1E // Reserved (high)
+#define EFI_SCSI_TYPE_UNKNOWN 0x1F // Unknown or no device type
+#pragma pack(1)
+//
+// Data structures for scsi command use
+//
+typedef struct {
+ UINT8 Peripheral_Type : 5;
+ UINT8 Peripheral_Qualifier : 3;
+ UINT8 DeviceType_Modifier : 7;
+ UINT8 RMB : 1;
+ UINT8 Version;
+ UINT8 Response_Data_Format;
+ UINT8 Addnl_Length;
+ UINT8 Reserved_5_95[95 - 5 + 1];
+} EFI_SCSI_INQUIRY_DATA;
+
+typedef struct {
+ UINT8 Error_Code : 7;
+ UINT8 Valid : 1;
+ UINT8 Segment_Number;
+ UINT8 Sense_Key : 4;
+ UINT8 Reserved_21 : 1;
+ UINT8 ILI : 1;
+ UINT8 Reserved_22 : 2;
+ UINT8 Information_3_6[4];
+ UINT8 Addnl_Sense_Length; // n - 7
+ UINT8 Vendor_Specific_8_11[4];
+ UINT8 Addnl_Sense_Code; // mandatory
+ UINT8 Addnl_Sense_Code_Qualifier; // mandatory
+ UINT8 Field_Replaceable_Unit_Code; // optional
+ UINT8 Reserved_15_17[3];
+} EFI_SCSI_SENSE_DATA;
+
+typedef struct {
+ UINT8 LastLba3;
+ UINT8 LastLba2;
+ UINT8 LastLba1;
+ UINT8 LastLba0;
+ UINT8 BlockSize3;
+ UINT8 BlockSize2;
+ UINT8 BlockSize1;
+ UINT8 BlockSize0;
+} EFI_SCSI_DISK_CAPACITY_DATA;
+
+#pragma pack()
+//
+// Sense Key
+//
+#define EFI_SCSI_REQUEST_SENSE_ERROR (0x70)
+#define EFI_SCSI_SK_NO_SENSE (0x0)
+#define EFI_SCSI_SK_RECOVERY_ERROR (0x1)
+#define EFI_SCSI_SK_NOT_READY (0x2)
+#define EFI_SCSI_SK_MEDIUM_ERROR (0x3)
+#define EFI_SCSI_SK_HARDWARE_ERROR (0x4)
+#define EFI_SCSI_SK_ILLEGAL_REQUEST (0x5)
+#define EFI_SCSI_SK_UNIT_ATTENTION (0x6)
+#define EFI_SCSI_SK_DATA_PROTECT (0x7)
+#define EFI_SCSI_SK_BLANK_CHECK (0x8)
+#define EFI_SCSI_SK_VENDOR_SPECIFIC (0x9)
+#define EFI_SCSI_SK_RESERVED_A (0xA)
+#define EFI_SCSI_SK_ABORT (0xB)
+#define EFI_SCSI_SK_RESERVED_C (0xC)
+#define EFI_SCSI_SK_OVERFLOW (0xD)
+#define EFI_SCSI_SK_MISCOMPARE (0xE)
+#define EFI_SCSI_SK_RESERVED_F (0xF)
+
+//
+// Additional Sense Codes
+//
+#define EFI_SCSI_ASC_NOT_READY (0x04)
+#define EFI_SCSI_ASC_MEDIA_ERR1 (0x10)
+#define EFI_SCSI_ASC_MEDIA_ERR2 (0x11)
+#define EFI_SCSI_ASC_MEDIA_ERR3 (0x14)
+#define EFI_SCSI_ASC_MEDIA_ERR4 (0x30)
+#define EFI_SCSI_ASC_MEDIA_UPSIDE_DOWN (0x06)
+#define EFI_SCSI_ASC_INVALID_CMD (0x20)
+#define EFI_SCSI_ASC_LBA_OUT_OF_RANGE (0x21)
+#define EFI_SCSI_ASC_INVALID_FIELD (0x24)
+#define EFI_SCSI_ASC_WRITE_PROTECTED (0x27)
+#define EFI_SCSI_ASC_MEDIA_CHANGE (0x28)
+#define EFI_SCSI_ASC_RESET (0x29) /* Power On Reset or Bus Reset occurred */
+#define EFI_SCSI_ASC_ILLEGAL_FIELD (0x26)
+#define EFI_SCSI_ASC_NO_MEDIA (0x3A)
+#define EFI_SCSI_ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
+
+//
+// Additional Sense Code Qualifier
+//
+#define EFI_SCSI_ASCQ_IN_PROGRESS (0x01)
+
+#endif
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