diff options
| author | ajfish <ajfish@6f19259b-4bc3-4df7-8a09-765794883524> | 2006-10-22 07:32:16 +0000 |
|---|---|---|
| committer | ajfish <ajfish@6f19259b-4bc3-4df7-8a09-765794883524> | 2006-10-22 07:32:16 +0000 |
| commit | 92ea7f231b3948395e6348ab6e38e3467eff7a3d (patch) | |
| tree | 865757b5713ed657dbdbb85b591d6d44b35bd805 /MdePkg/Include/Library/BaseLib.h | |
| parent | b077fb74924774d9d4c1189000eb9e8aed7a67ac (diff) | |
| download | edk2-platforms-92ea7f231b3948395e6348ab6e38e3467eff7a3d.tar.xz | |
Updated the Runtime Driver to use the MDE libs for cache flush and removed local copy of Cache flush code. Updated FPD files that include Runtime driver as a new lib was added to Runtime Driver for the cache flush. Removed Cache Flush routine from EDK DXE SAL Lib.
Cleaned up BaseLib IPF cache routines to only Flush ranges when needed and not to flush the entire cache.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@1811 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdePkg/Include/Library/BaseLib.h')
| -rw-r--r-- | MdePkg/Include/Library/BaseLib.h | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index e414e27399..329385d9c1 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -5072,24 +5072,24 @@ IpfReadItc ( /**
- Invalidates a range of instruction cache lines in the cache coherency domain
- of the calling CPU.
-
- Invalidates the instruction cache lines specified by Address and Length. If
- Address is not aligned on a cache line boundary, then entire instruction
- cache line containing Address is invalidated. If Address + Length is not
- aligned on a cache line boundary, then the entire instruction cache line
- containing Address + Length -1 is invalidated. This function may choose to
- invalidate the entire instruction cache if that is more efficient than
- invalidating the specified range. If Length is 0, the no instruction cache
- lines are invalidated. Address is returned.
+ Flush a range of cache lines in the cache coherency domain of the calling
+ CPU.
+
+ Invalidates the cache lines specified by Address and Length. If Address is
+ not aligned on a cache line boundary, then entire cache line containing
+ Address is invalidated. If Address + Length is not aligned on a cache line
+ boundary, then the entire instruction cache line containing Address + Length
+ -1 is invalidated. This function may choose to invalidate the entire
+ instruction cache if that is more efficient than invalidating the specified
+ range. If Length is 0, the no instruction cache lines are invalidated.
+ Address is returned.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
- @param Address The base address of the instruction cache lines to
- invalidate. If the CPU is in a physical addressing mode, then
- Address is a physical address. If the CPU is in a virtual
- addressing mode, then Address is a virtual address.
+ @param Address The base address of the instruction lines to invalidate. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing mode,
+ then Address is a virtual address.
@param Length The number of bytes to invalidate from the instruction cache.
@@ -5098,7 +5098,7 @@ IpfReadItc ( **/
VOID *
EFIAPI
-IpfInvalidateInstructionCacheRange (
+IpfFlushCacheRange (
IN VOID *Address,
IN UINTN Length
);
|