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| author | klu2 <klu2@6f19259b-4bc3-4df7-8a09-765794883524> | 2009-08-20 04:45:08 +0000 |
|---|---|---|
| committer | klu2 <klu2@6f19259b-4bc3-4df7-8a09-765794883524> | 2009-08-20 04:45:08 +0000 |
| commit | b2057cc9111e9de63e67273eda300240c55e6c2d (patch) | |
| tree | d5dfe7829665fc41da23cc87ba5fa1ba86c723b8 /MdePkg/Include/Pi | |
| parent | 90f6a2c69c7a2bfd56ec67b11e347692deaf7587 (diff) | |
| download | edk2-platforms-b2057cc9111e9de63e67273eda300240c55e6c2d.tar.xz | |
Add computing Unit Chipset Subclass Progress Code definitions from PI 1.2 specification.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9146 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdePkg/Include/Pi')
| -rw-r--r-- | MdePkg/Include/Pi/PiStatusCode.h | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/MdePkg/Include/Pi/PiStatusCode.h b/MdePkg/Include/Pi/PiStatusCode.h index ed808daf09..23c6a3836a 100644 --- a/MdePkg/Include/Pi/PiStatusCode.h +++ b/MdePkg/Include/Pi/PiStatusCode.h @@ -209,6 +209,61 @@ typedef struct { //
///
+/// South Bridge initialization prior to memory detection
+///
+#define EFI_CHIPSET_PC_PEI_CAR_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000000)
+
+///
+/// North Bridge initialization prior to memory detection
+///
+#define EFI_CHIPSET_PC_PEI_CAR_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000001)
+
+///
+/// South Bridge initialization after memory detection
+///
+#define EFI_CHIPSET_PC_PEI_MEM_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000002)
+
+///
+/// North Bridge initialization after memory detection
+///
+#define EFI_CHIPSET_PC_PEI_MEM_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000003)
+
+///
+/// PCI Host Bridge DXE initialization
+///
+#define EFI_CHIPSET_PC_DXE_HB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000004)
+
+///
+/// North Bridge DXE initialization
+///
+#define EFI_CHIPSET_PC_DXE_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000005)
+
+///
+/// North Bridge specific SMM initialization in DXE
+///
+#define EFI_CHIPSET_PC_DXE_NB_SMM_INIT (EFI_SUBCLASS_SPECIFIC|0x00000006)
+
+///
+/// Initialization of the South Bridge specific UEFI Runtime Services
+///
+#define EFI_CHIPSET_PC_DXE_SB_RT_INIT (EFI_SUBCLASS_SPECIFIC|0x00000007)
+
+///
+/// South Bridge DXE initialization
+///
+#define EFI_CHIPSET_PC_DXE_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000008)
+
+///
+/// South Bridge specific SMM initialization in DXE
+///
+#define EFI_CHIPSET_PC_DXE_SB_SMM_INIT (EFI_SUBCLASS_SPECIFIC|0x00000009)
+
+///
+/// Initialization of the South Bridge devices
+///
+#define EFI_CHIPSET_PC_DXE_SB_DEVICES_INIT (EFI_SUBCLASS_SPECIFIC|0x0000000a)
+
+///
/// Computing Unit Class Error Code definitions.
/// These are shared by all subclasses.
///
|