Fixed a bug in WriteBackInvalidDataCache() that always flush cache lines even when the argument Length is zero.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@1504 6f19259b-4bc3-4df7-8a09-765794883524

1 files changed, 17 insertions, 9 deletions

diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c b/MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c
index 3879cdfa2d..6e812c99c3 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c
@@ -14,6 +14,12 @@
 

 **/

 

+//

+// This size must be at or below the smallest cache size possible among all

+// supported processors

+//

+#define CACHE_LINE_SIZE             0x20

+

 /**

   Invalidates the entire instruction cache in cache coherency domain of the

   calling CPU.

@@ -118,19 +124,21 @@ WriteBackInvalidateDataCacheRange (
   IN      UINTN                     Length

   )

 {

-  UINT8                             (*Uint8Ptr)[32];

+  UINTN                             Start, End;

 

   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);

 

-  Uint8Ptr = Address;

-  while (Length > sizeof (*Uint8Ptr)) {

-    AsmFlushCacheLine (Uint8Ptr++);

-    Length -= sizeof (*Uint8Ptr);

-  }

-  if (Length > 0) {

-    AsmFlushCacheLine (Uint8Ptr);

-    AsmFlushCacheLine (&(*Uint8Ptr)[Length - 1]);

+  if (Length == 0) {

+    return Address;

   }

+

+  Start = (UINTN)Address;

+  End = (Start + Length + (CACHE_LINE_SIZE - 1)) & ~(CACHE_LINE_SIZE - 1);

+  Start &= ~(CACHE_LINE_SIZE - 1);

+

+  do {

+    Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CACHE_LINE_SIZE;

+  } while (Start != End);

   return Address;

 }