diff options
| author | mdkinney <mdkinney@6f19259b-4bc3-4df7-8a09-765794883524> | 2009-08-18 21:24:08 +0000 |
|---|---|---|
| committer | mdkinney <mdkinney@6f19259b-4bc3-4df7-8a09-765794883524> | 2009-08-18 21:24:08 +0000 |
| commit | 990e25aa3597f1f48ec5920b03a276b94c5db8ec (patch) | |
| tree | 38af25be40a50bfbfed9a78dd35d292c70589c37 /MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm | |
| parent | 64698eb8415e6829b956a12c3883655acc02f5a7 (diff) | |
| download | edk2-platforms-990e25aa3597f1f48ec5920b03a276b94c5db8ec.tar.xz | |
Add Add ARM support
Add C inline assembly files for IA32 and X64 GCC builds.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9114 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm')
| -rw-r--r-- | MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm b/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm new file mode 100644 index 0000000000..e0aaf21663 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm @@ -0,0 +1,39 @@ +;------------------------------------------------------------------------------
+;
+; CpuSleep() for ARM
+;
+; Copyright (c) 2006 - 2009, Intel Corporation<BR>
+; Portions copyright (c) 2008-2009 Apple Inc.<BR>
+; All rights reserved. This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+ EXPORT CpuSleep
+ AREA cpu_sleep, CODE, READONLY
+
+;/**
+; Places the CPU in a sleep state until an interrupt is received.
+;
+; Places the CPU in a sleep state until an interrupt is received. If interrupts
+; are disabled prior to calling this function, then the CPU will be placed in a
+; sleep state indefinitely.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuSleep (
+; VOID
+; );
+;
+CpuSleep
+ MOV r0,#0
+ MCR p15,0,r0,c7,c0,4 ;Wait for Interrupt instruction
+ BX LR
+
+ END
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