Add Add ARM support

Add C inline assembly files for IA32 and X64 GCC builds.


git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9114 6f19259b-4bc3-4df7-8a09-765794883524

7 files changed, 230 insertions, 4 deletions

diff --git a/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.S b/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.S
new file mode 100644
index 0000000000..6581425491
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.S
@@ -0,0 +1,36 @@
+#------------------------------------------------------------------------------ 

+#

+# CpuFlushTlb() for ARM

+#

+# Copyright (c) 2006 - 2009, Intel Corporation<BR>

+# Portions copyright (c) 2008-2009 Apple Inc.<BR>

+# All rights reserved. This program and the accompanying materials

+# are licensed and made available under the terms and conditions of the BSD License

+# which accompanies this distribution.  The full text of the license may be found at

+# http://opensource.org/licenses/bsd-license.php

+#

+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+#

+#------------------------------------------------------------------------------

+

+.text

+.p2align 2

+.globl ASM_PFX(CpuFlushTlb)

+

+#/**

+#  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.

+#

+#  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.

+#

+#**/

+#VOID

+#EFIAPI

+#CpuFlushTlb (

+#  VOID

+#  )#

+#

+ASM_PFX(CpuFlushTlb):

+    mov r0,#0

+    mcr p15,0,r0,c8,c5,0        # Invalidate all the unlocked entried in TLB

+    bx  LR

diff --git a/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.asm b/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.asm
new file mode 100644
index 0000000000..e0ccdfdfde
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.asm
@@ -0,0 +1,37 @@
+;------------------------------------------------------------------------------ 

+;

+; CpuFlushTlb() for ARM

+;

+; Copyright (c) 2006 - 2009, Intel Corporation<BR>

+; Portions copyright (c) 2008-2009 Apple Inc.<BR>

+; All rights reserved. This program and the accompanying materials

+; are licensed and made available under the terms and conditions of the BSD License

+; which accompanies this distribution.  The full text of the license may be found at

+; http://opensource.org/licenses/bsd-license.php

+;

+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+;

+;------------------------------------------------------------------------------

+

+  EXPORT CpuFlushTlb

+  AREA cpu_flush_tlb, CODE, READONLY

+

+;/**

+;  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.

+;

+;  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.

+;

+;**/

+;VOID

+;EFIAPI

+;CpuFlushTlb (

+;  VOID

+;  );

+;

+CpuFlushTlb 

+    MOV r0,#0

+    MCR p15,0,r0,c8,c5,0        ;Invalidate all the unlocked entried in TLB

+    BX LR

+

+  END

diff --git a/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.S b/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.S
new file mode 100644
index 0000000000..8d06372262
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.S
@@ -0,0 +1,38 @@
+#------------------------------------------------------------------------------ 

+#

+# CpuSleep() for ARM

+#

+# Copyright (c) 2006 - 2009, Intel Corporation<BR>

+# Portions copyright (c) 2008-2009 Apple Inc.<BR>

+# All rights reserved. This program and the accompanying materials

+# are licensed and made available under the terms and conditions of the BSD License

+# which accompanies this distribution.  The full text of the license may be found at

+# http://opensource.org/licenses/bsd-license.php

+#

+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+#

+#------------------------------------------------------------------------------

+

+.text

+.p2align 2

+.globl ASM_PFX(CpuSleep)

+

+#/**

+#  Places the CPU in a sleep state until an interrupt is received.

+#

+#  Places the CPU in a sleep state until an interrupt is received. If interrupts

+#  are disabled prior to calling this function, then the CPU will be placed in a

+#  sleep state indefinitely.

+#

+#**/

+#VOID

+#EFIAPI

+#CpuSleep (

+#  VOID

+#  );

+#

+ASM_PFX(CpuSleep):

+    mov r0,#0

+    mcr p15,0,r0,c7,c0,4   ;Wait for Interrupt instruction

+    bx  lr

diff --git a/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm b/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm
new file mode 100644
index 0000000000..e0aaf21663
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm
@@ -0,0 +1,39 @@
+;------------------------------------------------------------------------------ 

+;

+; CpuSleep() for ARM

+;

+; Copyright (c) 2006 - 2009, Intel Corporation<BR>

+; Portions copyright (c) 2008-2009 Apple Inc.<BR>

+; All rights reserved. This program and the accompanying materials

+; are licensed and made available under the terms and conditions of the BSD License

+; which accompanies this distribution.  The full text of the license may be found at

+; http://opensource.org/licenses/bsd-license.php

+;

+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+;

+;------------------------------------------------------------------------------

+

+  EXPORT CpuSleep

+  AREA cpu_sleep, CODE, READONLY

+

+;/**

+;  Places the CPU in a sleep state until an interrupt is received.

+;

+;  Places the CPU in a sleep state until an interrupt is received. If interrupts

+;  are disabled prior to calling this function, then the CPU will be placed in a

+;  sleep state indefinitely.

+;

+;**/

+;VOID

+;EFIAPI

+;CpuSleep (

+;  VOID

+;  );

+;

+CpuSleep

+    MOV r0,#0

+    MCR p15,0,r0,c7,c0,4   ;Wait for Interrupt instruction

+    BX LR

+

+  END

diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
index 2747224083..567202a779 100644
--- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
@@ -4,7 +4,8 @@
 #  CPU Library implemented using ASM functions for IA-32 and X64,

 #  PAL CALLs for IPF, and empty functions for EBC.

 #

-#  Copyright (c) 2007 - 2008, Intel Corporation.

+#  Copyright (c) 2007 - 2008, Intel Corporation.<BR>

+#  Portions Copyright (c) 2008-2009 Apple Inc.<BR>
 #

 #  All rights reserved. This program and the accompanying materials

 #  are licensed and made available under the terms and conditions of the BSD License

@@ -26,12 +27,12 @@
 

 

 #

-#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC

+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC ARM

 #

 

 [Sources.common]

 

-[Sources.Ia32]

+[Sources.IA32]

   Ia32/CpuSleep.c | MSFT 

   Ia32/CpuFlushTlb.c | MSFT 

 

@@ -55,10 +56,16 @@
 [Sources.EBC]

   Ebc/CpuSleepFlushTlb.c

 

+[Sources.ARM]
+  Arm/CpuFlushTlb.asm | RVCT
+  Arm/CpuSleep.asm    | RVCT  
+  Arm/CpuFlushTlb.S   | GCC
+  Arm/CpuSleep.S      | GCC  
+
 [Packages]

   MdePkg/MdePkg.dec

 

 

-[LibraryClasses.Ipf]

+[LibraryClasses.IPF]

   PalLib

   BaseLib
\ No newline at end of file
diff --git a/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlbGcc.c b/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlbGcc.c
new file mode 100644
index 0000000000..1b27f79e45
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlbGcc.c
@@ -0,0 +1,36 @@
+/** @file
+  CpuFlushTlb function for Ia32/X64 GCC.
+
+  Copyright (c) 2006 - 2008, Intel Corporation<BR>
+  Portions copyright (c) 2008-2009 Apple Inc.<BR>
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+
+/**
+  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+**/
+VOID
+EFIAPI
+CpuFlushTlb (
+  VOID
+  )
+{
+  __asm__ __volatile__ (
+    "movl %%cr3, %0\n\t"
+    "movl %0, %%cr3    "
+    : "r"  // %0
+    );
+}
+
diff --git a/MdePkg/Library/BaseCpuLib/Ia32/CpuSleepGcc.c b/MdePkg/Library/BaseCpuLib/Ia32/CpuSleepGcc.c
new file mode 100644
index 0000000000..a684059b59
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Ia32/CpuSleepGcc.c
@@ -0,0 +1,33 @@
+/** @file
+  CpuSleep function for Ia32/X64 GCC.
+
+  Copyright (c) 2006 - 2008, Intel Corporation<BR>
+  Portions copyright (c) 2008-2009 Apple Inc.<BR>
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+/**
+  Places the CPU in a sleep state until an interrupt is received.
+
+  Places the CPU in a sleep state until an interrupt is received. If interrupts
+  are disabled prior to calling this function, then the CPU will be placed in a
+  sleep state indefinitely.
+
+**/
+VOID
+EFIAPI
+CpuSleep (
+  VOID
+  )
+{
+  __asm__ __volatile__ ("hlt"::: "memory");
+}
+