diff options
| author | vanjeff <vanjeff@6f19259b-4bc3-4df7-8a09-765794883524> | 2007-07-02 09:34:25 +0000 |
|---|---|---|
| committer | vanjeff <vanjeff@6f19259b-4bc3-4df7-8a09-765794883524> | 2007-07-02 09:34:25 +0000 |
| commit | f1baef624fb7119c54c3389a2cd99b108ee08f0e (patch) | |
| tree | d713f9ecb9bcb40f62ace27aa135db8c4b0e86e0 /MdePkg/Library/BaseLib/Ipf | |
| parent | 29b052646a5f5fa0b28cbe9ca6224541e688f251 (diff) | |
| download | edk2-platforms-f1baef624fb7119c54c3389a2cd99b108ee08f0e.tar.xz | |
1. Port X64, IPF and EBC arch for BaseLib
2. Port X64 arch codes for BaseMemoryLibRepStr and BaseMemoryLibSee2
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@2955 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdePkg/Library/BaseLib/Ipf')
26 files changed, 3218 insertions, 0 deletions
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessDbr.s b/MdePkg/Library/BaseLib/Ipf/AccessDbr.s new file mode 100644 index 0000000000..49d1fecbbf --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/AccessDbr.s @@ -0,0 +1,118 @@ +/// @file
+/// IPF specific Debug Breakpoint Registers accessing functions
+///
+/// Copyright (c) 2006, Intel Corporation
+/// All rights reserved. This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: AccessDbr.s
+///
+///
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadDbr
+//
+// This routine is used to Reads the current value of Data Breakpoint Register (DBR).
+//
+// Arguments :
+//
+// On Entry : The 8-bit DBR index to read.
+//
+// Return Value: The current value of DBR by Index.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadDbr, @function
+.proc AsmReadDbr
+.regstk 1, 0, 0, 0
+
+AsmReadDbr::
+ mov r8 = dbr[in0];;
+ br.ret.dpnt b0;;
+.endp AsmReadDbr
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteDbr
+//
+// This routine is used to write the current value to Data Breakpoint Register (DBR).
+//
+// Arguments :
+//
+// On Entry : The 8-bit DBR index to read.
+// The value should be written to DBR
+//
+// Return Value: The value written to DBR.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWriteDbr, @function
+.proc AsmWriteDbr
+.regstk 2, 0, 0, 0
+
+AsmWriteDbr::
+ mov dbr[in0] = in1
+ mov r8 = in1;;
+ srlz.d;;
+ br.ret.dpnt b0;;
+.endp AsmWriteDbr
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadIbr
+//
+// This routine is used to Reads the current value of Instruction Breakpoint Register (IBR).
+//
+// Arguments :
+//
+// On Entry : The 8-bit IBR index.
+//
+// Return Value: The current value of IBR by Index.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadIbr, @function
+.proc AsmReadIbr
+.regstk 1, 0, 0, 0
+
+AsmReadIbr::
+ mov r8 = ibr[in0];;
+ br.ret.dpnt b0;;
+.endp AsmReadIbr
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteIbr
+//
+// This routine is used to write the current value to Instruction Breakpoint Register (IBR).
+//
+// Arguments :
+//
+// On Entry : The 8-bit IBR index.
+// The value should be written to IBR
+//
+// Return Value: The value written to IBR.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWriteIbr, @function
+.proc AsmWriteIbr
+.regstk 2, 0, 0, 0
+
+AsmWriteIbr::
+ mov ibr[in0] = in1
+ mov r8 = in1;;
+ srlz.i;;
+ br.ret.dpnt b0;;
+.endp AsmWriteIbr
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessEicr.s b/MdePkg/Library/BaseLib/Ipf/AccessEicr.s new file mode 100644 index 0000000000..03d7e034f8 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/AccessEicr.s @@ -0,0 +1,512 @@ +/// @file
+/// IPF specific External Interrupt Control Registers accessing functions
+///
+/// Copyright (c) 2006, Intel Corporation
+/// All rights reserved. This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: AccessEicr.s
+///
+///
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadLid
+//
+// This routine is used to read the value of Local Interrupt ID Register (LID).
+//
+// Arguments :
+//
+// On Entry :
+//
+// Return Value: The current value of LID.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadLid, @function
+.proc AsmReadLid
+
+AsmReadLid::
+ mov r8 = cr.lid;;
+ srlz.d;;
+ br.ret.dpnt b0;;
+.endp AsmReadLid
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteLid
+//
+// This routine is used to write the value to Local Interrupt ID Register (LID).
+//
+// Arguments :
+//
+// On Entry : The value need to be written to LID.
+//
+// Return Value: The value written to LID.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWriteLid, @function
+.proc AsmWriteLid
+.regstk 1, 0, 0, 0
+
+AsmWriteLid::
+ mov cr.lid = in0
+ mov r8 = in0;;
+ srlz.d;;
+ br.ret.dpnt b0;;
+.endp AsmWriteLid
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadIvr
+//
+// This routine is used to read the value of External Interrupt Vector Register (IVR).
+//
+// Arguments :
+//
+// On Entry :
+//
+// Return Value: The current value of IVR.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadIvr, @function
+.proc AsmReadIvr
+
+AsmReadIvr::
+ mov r8 = cr.ivr;;
+ srlz.d;;
+ br.ret.dpnt b0;;
+.endp AsmReadIvr
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadTpr
+//
+// This routine is used to read the value of Task Priority Register (TPR).
+//
+// Arguments :
+//
+// On Entry :
+//
+// Return Value: The current value of TPR.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadTpr, @function
+.proc AsmReadTpr
+
+AsmReadTpr::
+ mov r8 = cr.tpr;;
+ br.ret.dpnt b0;;
+.endp AsmReadTpr
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteTpr
+//
+// This routine is used to write the value to Task Priority Register (TPR).
+//
+// Arguments :
+//
+// On Entry : The value need to be written to TPR.
+//
+// Return Value: The value written to TPR.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWriteTpr, @function
+.proc AsmWriteTpr
+.regstk 1, 0, 0, 0
+
+AsmWriteTpr::
+ mov cr.tpr = in0
+ mov r8 = in0;;
+ srlz.d;;
+ br.ret.dpnt b0;;
+.endp AsmWriteTpr
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteEoi
+//
+// This routine is used to write the value to End of External Interrupt Register (EOI).
+//
+// Arguments :
+//
+// On Entry : The value need to be written to EOI.
+//
+// Return Value: The value written to EOI.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWriteEoi, @function
+.proc AsmWriteEoi
+
+AsmWriteEoi::
+ mov cr.eoi = r0;;
+ srlz.d;;
+ br.ret.dpnt b0;;
+.endp AsmWriteEoi
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadIrr0
+//
+// This routine is used to Read the value of External Interrupt Request Register 0 (IRR0).
+//
+// Arguments :
+//
+// On Entry :
+//
+// Return Value: The current value of IRR0.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadIrr0, @function
+.proc AsmReadIrr0
+
+AsmReadIrr0::
+ mov r8 = cr.irr0;;
+ br.ret.dpnt b0;;
+.endp AsmReadIrr0
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadIrr1
+//
+// This routine is used to Read the value of External Interrupt Request Register 1 (IRR1).
+//
+// Arguments :
+//
+// On Entry :
+//
+// Return Value: The current value of IRR1.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadIrr1, @function
+.proc AsmReadIrr1
+
+AsmReadIrr1::
+ mov r8 = cr.irr1;;
+ br.ret.dpnt b0;;
+.endp AsmReadIrr1
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadIrr2
+//
+// This routine is used to Read the value of External Interrupt Request Register 2 (IRR2).
+//
+// Arguments :
+//
+// On Entry :
+//
+// Return Value: The current value of IRR2.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadIrr2, @function
+.proc AsmReadIrr2
+
+AsmReadIrr2::
+ mov r8 = cr.irr2;;
+ br.ret.dpnt b0;;
+.endp AsmReadIrr2
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadIrr3
+//
+// This routine is used to Read the value of External Interrupt Request Register 3 (IRR3).
+//
+// Arguments :
+//
+// On Entry :
+//
+// Return Value: The current value of IRR3.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadIrr3, @function
+.proc AsmReadIrr3
+
+AsmReadIrr3::
+ mov r8 = cr.irr3;;
+ br.ret.dpnt b0;;
+.endp AsmReadIrr3
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadItv
+//
+// This routine is used to Read the value of Interval Timer Vector Register (ITV).
+//
+// Arguments :
+//
+// On Entry :
+//
+// Return Value: The current value of ITV.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadItv, @function
+.proc AsmReadItv
+
+AsmReadItv::
+ mov r8 = cr.itv;;
+ br.ret.dpnt b0;;
+.endp AsmReadItv
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteItv
+//
+// This routine is used to write the value to Interval Timer Vector Register (ITV).
+//
+// Arguments :
+//
+// On Entry : The value need to be written to ITV
+//
+// Return Value: The value written to ITV.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWriteItv, @function
+.proc AsmWriteItv
+.regstk 1, 0, 0, 0
+
+AsmWriteItv::
+ mov cr.itv = in0
+ mov r8 = in0;;
+ srlz.d;;
+ br.ret.dpnt b0;;
+.endp AsmWriteItv
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadPmv
+//
+// This routine is used to Read the value of Performance Monitoring Vector Register (PMV).
+//
+// Arguments :
+//
+// On Entry :
+//
+// Return Value: The current value of PMV.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadPmv, @function
+.proc AsmReadPmv
+
+AsmReadPmv::
+ mov r8 = cr.pmv;;
+ br.ret.dpnt b0;;
+.endp AsmReadPmv
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWritePmv
+//
+// This routine is used to write the value to Performance Monitoring Vector Register (PMV).
+//
+// Arguments :
+//
+// On Entry : The value need to be written to PMV
+//
+// Return Value: The value written to PMV.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWritePmv, @function
+.proc AsmWritePmv
+.regstk 1, 0, 0, 0
+
+AsmWritePmv::
+ mov cr.pmv = in0
+ mov r8 = in0;;
+ srlz.d;;
+ br.ret.dpnt b0;;
+.endp AsmWritePmv
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadCmcv
+//
+// This routine is used to Read the value of Corrected Machine Check Vector Register (CMCV).
+//
+// Arguments :
+//
+// On Entry :
+//
+// Return Value: The current value of CMCV.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadCmcv, @function
+.proc AsmReadCmcv
+
+AsmReadCmcv::
+ mov r8 = cr.cmcv;;
+ br.ret.dpnt b0;;
+.endp AsmReadCmcv
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteCmcv
+//
+// This routine is used to write the value to Corrected Machine Check Vector Register (CMCV).
+//
+// Arguments :
+//
+// On Entry : The value need to be written to CMCV
+//
+// Return Value: The value written to CMCV.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWriteCmcv, @function
+.proc AsmWriteCmcv
+.regstk 1, 0, 0, 0
+
+AsmWriteCmcv::
+ mov cr.cmcv = in0
+ mov r8 = in0;;
+ srlz.d;;
+ br.ret.dpnt b0;;
+.endp AsmWriteCmcv
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadLrr0
+//
+// This routine is used to read the value of Local Redirection Register 0 (LRR0).
+//
+// Arguments :
+//
+// On Entry :
+//
+// Return Value: The current value of LRR0.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadLrr0, @function
+.proc AsmReadLrr0
+
+AsmReadLrr0::
+ mov r8 = cr.lrr0;;
+ br.ret.dpnt b0;;
+.endp AsmReadLrr0
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteLrr0
+//
+// This routine is used to write the value to Local Redirection Register 0 (LRR0).
+//
+// Arguments :
+//
+// On Entry : The value need to be written to LRR0.
+//
+// Return Value: The value written to LRR0.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWriteLrr0, @function
+.proc AsmWriteLrr0
+.regstk 1, 0, 0, 0
+
+AsmWriteLrr0::
+ mov cr.lrr0 = in0
+ mov r8 = in0;;
+ srlz.d;;
+ br.ret.dpnt b0;;
+.endp AsmWriteLrr0
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadLrr1
+//
+// This routine is used to read the value of Local Redirection Register 1 (LRR1).
+//
+// Arguments :
+//
+// On Entry :
+//
+// Return Value: The current value of LRR1.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadLrr1, @function
+.proc AsmReadLrr1
+
+AsmReadLrr1::
+ mov r8 = cr.lrr1;;
+ br.ret.dpnt b0;;
+.endp AsmReadLrr1
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteLrr1
+//
+// This routine is used to write the value to Local Redirection Register 1 (LRR1).
+//
+// Arguments :
+//
+// On Entry : The value need to be written to LRR1.
+//
+// Return Value: The value written to LRR1.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWriteLrr1, @function
+.proc AsmWriteLrr1
+.regstk 1, 0, 0, 0
+
+AsmWriteLrr1::
+ mov cr.lrr1 = in0
+ mov r8 = in0;;
+ srlz.d;;
+ br.ret.dpnt b0;;
+.endp AsmWriteLrr1
+
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessGcr.s b/MdePkg/Library/BaseLib/Ipf/AccessGcr.s new file mode 100644 index 0000000000..54b3a30a6d --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/AccessGcr.s @@ -0,0 +1,264 @@ +/// @file
+/// IPF specific Global Control Registers accessing functions
+///
+/// Copyright (c) 2006, Intel Corporation
+/// All rights reserved. This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: AccessGcr.s
+///
+///
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadDcr
+//
+// This routine is used to Read the value of Default Control Register (DCR).
+//
+// Arguments :
+//
+// On Entry :
+//
+// Return Value: The current value of DCR.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadDcr, @function
+.proc AsmReadDcr
+
+AsmReadDcr::
+ mov r8 = cr.dcr;;
+ br.ret.dpnt b0;;
+.endp AsmReadDcr
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteDcr
+//
+// This routine is used to write the value to Default Control Register (DCR).
+//
+// Arguments :
+//
+// On Entry : The value need to be written to DCR
+//
+// Return Value: The value written to DCR.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWriteDcr, @function
+.proc AsmWriteDcr
+.regstk 1, 0, 0, 0
+
+AsmWriteDcr::
+ mov cr.dcr = in0
+ mov r8 = in0;;
+ srlz.i;;
+ srlz.d;;
+ br.ret.dpnt b0;;
+.endp AsmWriteDcr
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadItc
+//
+// This routine is used to Read the value of Interval Timer Counter Register (ITC).
+//
+// Arguments :
+//
+// On Entry :
+//
+// Return Value: The current value of ITC.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadItc, @function
+.proc AsmReadItc
+
+AsmReadItc::
+ mov r8 = ar.itc;;
+ br.ret.dpnt b0;;
+.endp AsmReadItc
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteItc
+//
+// This routine is used to write the value to Interval Timer Counter Register (ITC).
+//
+// Arguments :
+//
+// On Entry : The value need to be written to the ITC
+//
+// Return Value: The value written to the ITC.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWriteItc, @function
+.proc AsmWriteItc
+.regstk 1, 0, 0, 0
+
+AsmWriteItc::
+ mov ar.itc = in0
+ mov r8 = in0;;
+ br.ret.dpnt b0;;
+.endp AsmWriteItc
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadItm
+//
+// This routine is used to Read the value of Interval Timer Match Register (ITM).
+//
+// Arguments :
+//
+// On Entry :
+//
+// Return Value: The current value of ITM.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadItm, @function
+.proc AsmReadItm
+
+AsmReadItm::
+ mov r8 = cr.itm;;
+ br.ret.dpnt b0;;
+.endp AsmReadItm
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteItm
+//
+// This routine is used to write the value to Interval Timer Match Register (ITM).
+//
+// Arguments :
+//
+// On Entry : The value need to be written to ITM
+//
+// Return Value: The value written to ITM.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWriteItm, @function
+.proc AsmWriteItm
+.regstk 1, 0, 0, 0
+
+AsmWriteItm::
+ mov cr.itm = in0
+ mov r8 = in0;;
+ srlz.d;
+ br.ret.dpnt b0;;
+.endp AsmWriteItm
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadIva
+//
+// This routine is used to read the value of Interruption Vector Address Register (IVA).
+//
+// Arguments :
+//
+// On Entry :
+//
+// Return Value: The current value of IVA.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadIva, @function
+.proc AsmReadIva
+
+AsmReadIva::
+ mov r8 = cr.iva;;
+ br.ret.dpnt b0;;
+.endp AsmReadIva
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteIva
+//
+// This routine is used to write the value to Interruption Vector Address Register (IVA).
+//
+// Arguments :
+//
+// On Entry : The value need to be written to IVA
+//
+// Return Value: The value written to IVA.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWriteIva, @function
+.proc AsmWriteIva
+.regstk 1, 0, 0, 0
+
+AsmWriteIva::
+ mov cr.iva = in0
+ mov r8 = in0;;
+ br.ret.dpnt b0;;
+.endp AsmWriteIva
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadPta
+//
+// This routine is used to read the value of Page Table Address Register (PTA).
+//
+// Arguments :
+//
+// On Entry :
+//
+// Return Value: The current value of PTA.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadPta, @function
+.proc AsmReadPta
+
+AsmReadPta::
+ mov r8 = cr.pta;;
+ br.ret.dpnt b0;;
+.endp AsmReadPta
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWritePta
+//
+// This routine is used to write the value to Page Table Address Register (PTA)).
+//
+// Arguments :
+//
+// On Entry : The value need to be written to PTA
+//
+// Return Value: The value written to PTA.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWritePta, @function
+.proc AsmWritePta
+.regstk 1, 0, 0, 0
+
+AsmWritePta::
+ mov cr.pta = in0
+ mov r8 = in0;;
+ srlz.i;;
+ srlz.d;;
+ br.ret.dpnt b0;;
+.endp AsmWritePta
\ No newline at end of file diff --git a/MdePkg/Library/BaseLib/Ipf/AccessGp.s b/MdePkg/Library/BaseLib/Ipf/AccessGp.s new file mode 100644 index 0000000000..5c5f20f584 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/AccessGp.s @@ -0,0 +1,86 @@ +/// @file
+/// IPF specific Global Pointer and Stack Pointer accessing functions
+///
+/// Copyright (c) 2006, Intel Corporation
+/// All rights reserved. This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: AccessGp.s
+///
+///
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadGp
+//
+// This routine is used to read the current value of 64-bit Global Pointer (GP).
+//
+// Arguments :
+//
+// On Entry :
+//
+// Return Value: The current GP value.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadGp, @function
+.proc AsmReadGp
+
+AsmReadGp::
+ mov r8 = gp;;
+ br.ret.dpnt b0;;
+.endp AsmReadGp
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteGp
+//
+// This routine is used to write the current value of 64-bit Global Pointer (GP).
+//
+// Arguments :
+//
+// On Entry : The value need to be written.
+//
+// Return Value: The value have been written.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWriteGp, @function
+.proc AsmWriteGp
+.regstk 1, 0, 0, 0
+
+AsmWriteGp::
+ mov gp = in0
+ mov r8 = in0;;
+ br.ret.dpnt b0;;
+.endp AsmWriteGp
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadSp
+//
+// This routine is used to read the current value of 64-bit Stack Pointer (SP).
+//
+// Arguments :
+//
+// On Entry :
+//
+// Return Value: The current SP value.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadSp, @function
+.proc AsmReadSp
+
+AsmReadSp::
+ mov r8 = sp;;
+ br.ret.dpnt b0;;
+.endp AsmReadSp
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessKr.s b/MdePkg/Library/BaseLib/Ipf/AccessKr.s new file mode 100644 index 0000000000..5a38954292 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/AccessKr.s @@ -0,0 +1,400 @@ +/// @file
+/// IPF specific AsmReadKrX() and AsmWriteKrX functions, 'X' is from '0' to '7'
+///
+/// Copyright (c) 2006, Intel Corporation
+/// All rights reserved. This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: AccessKr.s
+///
+///
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadKr0
+//
+// This routine is used to get KR0.
+//
+// Arguments :
+//
+// On Entry : None.
+//
+// Return Value: The value store in KR0.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadKr0, @function
+.proc AsmReadKr0
+
+AsmReadKr0::
+ mov r8 = ar.k0;;
+ br.ret.dpnt b0;;
+.endp AsmReadKr0
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteKr0
+//
+// This routine is used to Write KR0.
+//
+// Arguments :
+//
+// On Entry : None.
+//
+// Return Value: The value written to the KR0.
+//
+//--
+//----------------------------------------------------------------------------------
+
+.text
+.type AsmWriteKr0, @function
+.proc AsmWriteKr0
+.regstk 1, 0, 0, 0
+
+AsmWriteKr0::
+ mov ar.k0 = in0
+ mov r8 = in0;;
+ br.ret.dpnt b0;;
+.endp AsmWriteKr0
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadKr1
+//
+// This routine is used to get KR1.
+//
+// Arguments :
+//
+// On Entry : None.
+//
+// Return Value: The value store in KR1.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadKr1, @function
+.proc AsmReadKr1
+
+AsmReadKr1::
+ mov r8 = ar.k1;;
+ br.ret.dpnt b0;;
+.endp AsmReadKr1
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteKr1
+//
+// This routine is used to Write KR1.
+//
+// Arguments :
+//
+// On Entry : None.
+//
+// Return Value: The value written to the KR1.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWriteKr1, @function
+.proc AsmWriteKr1
+
+AsmWriteKr1::
+ mov ar.k1 = in0
+ mov r8 = in0;;
+ br.ret.dpnt b0;;
+.endp AsmWriteKr1
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadKr2
+//
+// This routine is used to get KR2.
+//
+// Arguments :
+//
+// On Entry : None.
+//
+// Return Value: The value store in KR2.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadKr2, @function
+.proc AsmReadKr2
+
+AsmReadKr2::
+ mov r8 = ar.k2;;
+ br.ret.dpnt b0;;
+.endp AsmReadKr2
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteKr2
+//
+// This routine is used to Write KR2.
+//
+// Arguments :
+//
+// On Entry : None.
+//
+// Return Value: The value written to the KR2.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWriteKr2, @function
+.proc AsmWriteKr2
+
+AsmWriteKr2::
+ mov ar.k2 = in0
+ mov r8 = in0;;
+ br.ret.dpnt b0;;
+.endp AsmWriteKr2
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadKr3
+//
+// This routine is used to get KR3.
+//
+// Arguments :
+//
+// On Entry : None.
+//
+// Return Value: The value store in KR3.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadKr3, @function
+.proc AsmReadKr3
+
+AsmReadKr3::
+ mov r8 = ar.k3;;
+ br.ret.dpnt b0;;
+.endp AsmReadKr3
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteKr3
+//
+// This routine is used to Write KR3.
+//
+// Arguments :
+//
+// On Entry : None.
+//
+// Return Value: The value written to the KR3.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWriteKr3, @function
+.proc AsmWriteKr3
+
+AsmWriteKr3::
+ mov ar.k3 = in0
+ mov r8 = in0;;
+ br.ret.dpnt b0;;
+.endp AsmWriteKr3
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadKr4
+//
+// This routine is used to get KR4.
+//
+// Arguments :
+//
+// On Entry : None.
+//
+// Return Value: The value store in KR4.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadKr4, @function
+.proc AsmReadKr4
+
+AsmReadKr4::
+ mov r8 = ar.k4;;
+ br.ret.dpnt b0;;
+.endp AsmReadKr4
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteKr4
+//
+// This routine is used to Write KR4.
+//
+// Arguments :
+//
+// On Entry : None.
+//
+// Return Value: The value written to the KR4.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWriteKr4, @function
+.proc AsmWriteKr4
+
+AsmWriteKr4::
+ mov ar.k4 = in0
+ mov r8 = in0;;
+ br.ret.dpnt b0;;
+.endp AsmWriteKr4
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadKr5
+//
+// This routine is used to get KR5.
+//
+// Arguments :
+//
+// On Entry : None.
+//
+// Return Value: The value store in KR5.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadKr5, @function
+.proc AsmReadKr5
+
+AsmReadKr5::
+ mov r8 = ar.k5;;
+ br.ret.dpnt b0;;
+.endp AsmReadKr5
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteKr5
+//
+// This routine is used to Write KR5.
+//
+// Arguments :
+//
+// On Entry : None.
+//
+// Return Value: The value written to the KR5.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWriteKr5, @function
+.proc AsmWriteKr5
+
+AsmWriteKr5::
+ mov ar.k5 = in0
+ mov r8 = in0;;
+ br.ret.dpnt b0;;
+.endp AsmWriteKr5
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadKr6
+//
+// This routine is used to get KR6.
+//
+// Arguments :
+//
+// On Entry : None.
+//
+// Return Value: The value store in KR6.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadKr6, @function
+.proc AsmReadKr6
+
+AsmReadKr6::
+ mov r8 = ar.k6;;
+ br.ret.dpnt b0;;
+.endp AsmReadKr6
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteKr6
+//
+// This routine is used to write KR6.
+//
+// Arguments :
+//
+// On Entry : None.
+//
+// Return Value: The value written to the KR6.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWriteKr6, @function
+.proc AsmWriteKr6
+
+AsmWriteKr6::
+ mov ar.k6 = in0
+ mov r8 = in0;;
+ br.ret.dpnt b0;;
+.endp AsmWriteKr6
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadKr7
+//
+// This routine is used to get KR7.
+//
+// Arguments :
+//
+// On Entry : None.
+//
+// Return Value: The value store in KR7.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadKr7, @function
+.proc AsmReadKr7
+
+AsmReadKr7::
+ mov r8 = ar.k7;;
+ br.ret.dpnt b0;;
+.endp AsmReadKr7
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWriteKr7
+//
+// This routine is used to write KR7.
+//
+// Arguments :
+//
+// On Entry : None.
+//
+// Return Value: The value written to the KR7.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWriteKr7, @function
+.proc AsmWriteKr7
+
+AsmWriteKr7::
+ mov ar.k7 = in0
+ mov r8 = in0;;
+ br.ret.dpnt b0;;
+.endp AsmWriteKr7
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessPmr.s b/MdePkg/Library/BaseLib/Ipf/AccessPmr.s new file mode 100644 index 0000000000..cea376c638 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/AccessPmr.s @@ -0,0 +1,124 @@ +/// @file
+/// IPF specific Performance Monitor Configuration/Data Registers accessing functions
+///
+/// Copyright (c) 2006, Intel Corporation
+/// All rights reserved. This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: AccessPmr.s
+///
+///
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadPmc
+//
+// This routine is used to Reads the current value of Performance Monitor Configuration Register (PMC).
+//
+// Arguments :
+//
+// On Entry : The 8-bit PMC index.
+//
+// Return Value: The current value of PMC by Index.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadPmc, @function
+.proc AsmReadPmc
+.regstk 1, 0, 0, 0
+
+AsmReadPmc::
+ srlz.i;;
+ srlz.d;;
+ mov r8 = pmc[in0];;
+ br.ret.dpnt b0;;
+.endp AsmReadPmc
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWritePmc
+//
+// This routine is used to write the current value to a Performance Monitor Configuration Register (PMC).
+//
+// Arguments :
+//
+// On Entry : The 8-bit PMC index.
+// The value should be written to PMC
+//
+// Return Value: The value written to PMC.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWritePmc, @function
+.proc AsmWritePmc
+.regstk 2, 0, 0, 0
+
+AsmWritePmc::
+ mov pmc[in0] = in1
+ mov r8 = in1;;
+ srlz.i;;
+ srlz.d;;
+ br.ret.dpnt b0;;
+.endp AsmWritePmc
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadPmd
+//
+// This routine is used to Reads the current value of Performance Monitor Data Register (PMD).
+//
+// Arguments :
+//
+// On Entry : The 8-bit PMD index.
+//
+// Return Value: The current value of PMD by Index.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadPmd, @function
+.proc AsmReadPmd
+.regstk 1, 0, 0, 0
+
+AsmReadPmd::
+ srlz.i;;
+ srlz.d;;
+ mov r8 = pmd[in0];;
+ br.ret.dpnt b0;;
+.endp AsmReadPmd
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWritePmd
+//
+// This routine is used to write the current value to Performance Monitor Data Register (PMD).
+//
+// Arguments :
+//
+// On Entry : The 8-bit PMD index.
+// The value should be written to PMD
+//
+// Return Value: The value written to PMD.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWritePmd, @function
+.proc AsmWritePmd
+.regstk 2, 0, 0, 0
+
+AsmWritePmd::
+ mov pmd[in0] = in1
+ mov r8 = in1;;
+ srlz.i;;
+ srlz.d;;
+ br.ret.dpnt b0;;
+.endp AsmWritePmd
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessPsr.s b/MdePkg/Library/BaseLib/Ipf/AccessPsr.s new file mode 100644 index 0000000000..9b4fe49ff1 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/AccessPsr.s @@ -0,0 +1,110 @@ +/// @file
+/// IPF specific Processor Status Register accessing functions
+///
+/// Copyright (c) 2006, Intel Corporation
+/// All rights reserved. This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: AccessPsr.s
+///
+///
+
+#define CpuModeMask 0x0000001008020000
+
+#define CpuInVirtualMode 0x1
+#define CpuInPhysicalMode 0x0
+#define CpuInMixMode (0x0 - 0x1)
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadPsr
+//
+// This routine is used to read the current value of Processor Status Register (PSR).
+//
+// Arguments :
+//
+// On Entry :
+//
+// Return Value: The current PSR value.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadPsr, @function
+.proc AsmReadPsr
+
+AsmReadPsr::
+ mov r8 = psr;;
+ br.ret.dpnt b0;;
+.endp AsmReadPsr
+
+//---------------------------------------------------------------------------------
+//++
+// AsmWritePsr
+//
+// This routine is used to write the value of Processor Status Register (PSR).
+//
+// Arguments :
+//
+// On Entry : The value need to be written.
+//
+// Return Value: The value have been written.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmWritePsr, @function
+.proc AsmWritePsr
+.regstk 1, 0, 0, 0
+
+AsmWritePsr::
+ mov psr.l = in0
+ mov r8 = in0;;
+ srlz.d;;
+ srlz.i;;
+ br.ret.dpnt b0;;
+.endp AsmWritePsr
+
+//---------------------------------------------------------------------------------
+//++
+// AsmCpuVirtual
+//
+// This routine is used to determines if the CPU is currently executing
+// in virtual, physical, or mixed mode.
+//
+// If the CPU is in virtual mode(PSR.RT=1, PSR.DT=1, PSR.IT=1), then 1 is returned.
+// If the CPU is in physical mode(PSR.RT=0, PSR.DT=0, PSR.IT=0), then 0 is returned.
+// If the CPU is not in physical mode or virtual mode, then it is in mixed mode,
+// and -1 is returned.
+//
+// Arguments:
+//
+// On Entry: None
+//
+// Return Value: The CPU mode flag
+// return 1 The CPU is in virtual mode.
+// return 0 The CPU is in physical mode.
+// return -1 The CPU is in mixed mode.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmCpuVirtual, @function
+.proc AsmCpuVirtual
+
+AsmCpuVirtual::
+ mov r29 = psr
+ movl r30 = CpuModeMask;;
+ and r28 = r30, r29;;
+ cmp.eq p6, p7 = r30, r28;;
+(p6) mov r8 = CpuInVirtualMode;;
+(p7) cmp.eq p6, p7 = 0x0, r28;;
+(p6) mov r8 = CpuInPhysicalMode;;
+(p7) mov r8 = CpuInMixMode;;
+ br.ret.dpnt b0;;
+.endp AsmCpuVirtual
\ No newline at end of file diff --git a/MdePkg/Library/BaseLib/Ipf/AsmPalCall.s b/MdePkg/Library/BaseLib/Ipf/AsmPalCall.s new file mode 100644 index 0000000000..9e70a78729 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/AsmPalCall.s @@ -0,0 +1,158 @@ +/// @file
+/// Contains an implementation of CallPalProcStacked on Itanium-based
+/// architecture.
+///
+/// Copyright (c) 2006, Intel Corporation
+/// All rights reserved. This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: AsmPalCall.s
+///
+///
+
+
+//-----------------------------------------------------------------------------
+//++
+// AsmPalCall
+//
+// Makes a PAL procedure call.
+// This is function to make a PAL procedure call. Based on the Index
+// value this API will make static or stacked PAL call. The following table
+// describes the usage of PAL Procedure Index Assignment. Architected procedures
+// may be designated as required or optional. If a PAL procedure is specified
+// as optional, a unique return code of 0xFFFFFFFFFFFFFFFF is returned in the
+// Status field of the PAL_CALL_RETURN structure.
+// This indicates that the procedure is not present in this PAL implementation.
+// It is the caller¡¯s responsibility to check for this return code after calling
+// any optional PAL procedure.
+// No parameter checking is performed on the 5 input parameters, but there are
+// some common rules that the caller should follow when making a PAL call. Any
+// address passed to PAL as buffers for return parameters must be 8-byte aligned.
+// Unaligned addresses may cause undefined results. For those parameters defined
+// as reserved or some fields defined as reserved must be zero filled or the invalid
+// argument return value may be returned or undefined result may occur during the
+// execution of the procedure. If the PalEntryPoint does not point to a valid
+// PAL entry point then the system behavior is undefined. This function is only
+// available on IPF.
+//
+// On Entry :
+// in0: PAL_PROC entrypoint
+// in1-in4 : PAL_PROC arguments
+//
+// Return Value:
+//
+// As per stacked calling conventions.
+//
+//--
+//---------------------------------------------------------------------------
+
+//
+// PAL function calls
+//
+#define PAL_MC_CLEAR_LOG 0x0015
+#define PAL_MC_DYNAMIC_STATE 0x0018
+#define PAL_MC_ERROR_INFO 0x0019
+#define PAL_MC_RESUME 0x001a
+
+
+.text
+.proc AsmPalCall
+.type AsmPalCall, @function
+
+AsmPalCall::
+ alloc loc1 = ar.pfs,5,8,4,0
+ mov loc0 = b0
+ mov loc3 = b5
+ mov loc4 = r2
+ mov loc7 = r1
+ mov r2 = psr;;
+ mov r28 = in1
+ mov loc5 = r2;;
+
+ movl loc6 = 0x100;;
+ cmp.ge p6,p7 = r28,loc6;;
+
+(p6) movl loc6 = 0x1FF;;
+(p7) br.dpnt.few PalCallStatic;; // 0 ~ 255 make a static Pal Call
+(p6) cmp.le p6,p7 = r28,loc6;;
+(p6) br.dpnt.few PalCallStacked;; // 256 ~ 511 make a stacked Pal Call
+(p7) movl loc6 = 0x300;;
+(p7) cmp.ge p6,p7 = r28,loc6;;
+(p7) br.dpnt.few PalCallStatic;; // 512 ~ 767 make a static Pal Call
+(p6) movl loc6 = 0x3FF;;
+(p6) cmp.le p6,p7 = r28,loc6;;
+(p6) br.dpnt.few PalCallStacked;; // 768 ~ 1023 make a stacked Pal Call
+
+(p7) mov r8 = 0xFFFFFFFFFFFFFFFF;; // > 1024 return invalid
+(p7) br.dpnt.few ComeBackFromPALCall;;
+
+PalCallStatic:
+ movl loc6 = PAL_MC_CLEAR_LOG;;
+ cmp.eq p6,p7 = r28,loc6;;
+
+(p7) movl loc6 = PAL_MC_DYNAMIC_STATE;;
+(p7) cmp.eq p6,p7 = r28,loc6;;
+
+(p7) movl loc6 = PAL_MC_ERROR_INFO;;
+(p7) cmp.eq p6,p7 = r28,loc6;;
+
+(p7) movl loc6 = PAL_MC_RESUME;;
+(p7) cmp.eq p6,p7 = r28,loc6 ;;
+
+ mov loc6 = 0x1;;
+(p7) dep r2 = loc6,r2,13,1;; // psr.ic = 1
+
+// p6 will be true, if it is one of the MCHK calls. There has been lots of debate
+// on psr.ic for these values. For now, do not do any thing to psr.ic
+
+ dep r2 = r0,r2,14,1;; // psr.i = 0
+
+ mov psr.l = r2
+ srlz.d // Needs data serailization.
+ srlz.i // Needs instruction serailization.
+
+StaticGetPALLocalIP:
+ mov loc2 = ip;;
+ add loc2 = ComeBackFromPALCall - StaticGetPALLocalIP,loc2;;
+ mov b0 = loc2 // return address after Pal call
+
+ mov r29 = in2
+ mov r30 = in3
+ mov r31 = in4
+ mov b5 = in0;; // get the PalProcEntrypt from input
+ br.sptk b5;; // Take the plunge.
+
+PalCallStacked:
+ dep r2 = r0,r2,14,1;; // psr.i = 0
+ mov psr.l = r2;;
+ srlz.d // Needs data serailization.
+ srlz.i // Needs instruction serailization.
+
+StackedGetPALLocalIP:
+ mov out0 = in1
+ mov out1 = in2
+ mov out2 = in3
+ mov out3 = in4
+ mov b5 = in0 ;; // get the PalProcEntrypt from input
+ br.call.dpnt b0 = b5 ;; // Take the plunge.
+
+ComeBackFromPALCall:
+ mov psr.l = loc5 ;;
+ srlz.d // Needs data serailization.
+ srlz.i // Needs instruction serailization.
+
+ mov b5 = loc3
+ mov r2 = loc4
+ mov r1 = loc7
+
+ mov b0 = loc0
+ mov ar.pfs = loc1;;
+ br.ret.dpnt b0;;
+
+.endp AsmPalCall
+
diff --git a/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c b/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c new file mode 100644 index 0000000000..3dcbecf29d --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c @@ -0,0 +1,123 @@ +/** @file
+ Base Library CPU functions for Itanium
+
+ Copyright (c) 2006, Intel Corporation<BR>
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// Include common header file for this module.
+//
+#include <BaseLibInternals.h>
+
+//void __mfa (void);
+
+#pragma intrinsic (_enable)
+#pragma intrinsic (_disable)
+#pragma intrinsic (__break)
+#pragma intrinsic (__mfa)
+
+
+/**
+ Generates a breakpoint on the CPU.
+
+ Generates a breakpoint on the CPU. The breakpoint must be implemented such
+ that code can resume normal execution after the breakpoint.
+
+**/
+VOID
+EFIAPI
+CpuBreakpoint (
+ VOID
+ )
+{
+ __break (0);
+}
+
+/**
+ Used to serialize load and store operations.
+
+ All loads and stores that proceed calls to this function are guaranteed to be
+ globally visible when this function returns.
+
+**/
+VOID
+EFIAPI
+MemoryFence (
+ VOID
+ )
+{
+ __mfa ();
+}
+
+/**
+ Disables CPU interrupts.
+
+ Disables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+DisableInterrupts (
+ VOID
+ )
+{
+ _disable ();
+}
+
+/**
+ Enables CPU interrupts.
+
+ Enables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+EnableInterrupts (
+ VOID
+ )
+{
+ _enable ();
+}
+
+/**
+ Enables CPU interrupts for the smallest window required to capture any
+ pending interrupts.
+
+ Enables CPU interrupts for the smallest window required to capture any
+ pending interrupts.
+
+**/
+VOID
+EFIAPI
+EnableDisableInterrupts (
+ VOID
+ )
+{
+ EnableInterrupts ();
+ DisableInterrupts ();
+}
+
+/**
+ Places the CPU in a sleep state until an interrupt is received.
+
+ Places the CPU in a sleep state until an interrupt is received. If interrupts
+ are disabled prior to calling this function, then the CPU will be placed in a
+ sleep state indefinitely.
+
+**/
+VOID
+EFIAPI
+CpuSleep (
+ VOID
+ )
+{
+ PalCallStatic (NULL, 29, 0, 0, 0);
+}
diff --git a/MdePkg/Library/BaseLib/Ipf/CpuFlushTlb.s b/MdePkg/Library/BaseLib/Ipf/CpuFlushTlb.s new file mode 100644 index 0000000000..520c51f6ba --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/CpuFlushTlb.s @@ -0,0 +1,58 @@ +/// @file
+/// CpuFlushTlb() function for Itanium-based architecture.
+///
+/// Copyright (c) 2006, Intel Corporation
+/// All rights reserved. This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: CpuFlushTlb.s
+///
+///
+
+.auto
+.text
+
+.globl PalCallStatic
+.type PalCallStatic, @function
+
+.proc CpuFlushTlb
+.type CpuFlushTlb, @function
+CpuFlushTlb::
+ alloc loc0 = ar.pfs, 0, 3, 5, 0
+ mov out0 = 0
+ mov out1 = 6
+ mov out2 = 0
+ mov out3 = 0
+ mov loc1 = b0
+ mov out4 = 0
+ brl.call.sptk b0 = PalCallStatic
+ mov loc2 = psr // save PSR
+ mov ar.pfs = loc0
+ extr.u r14 = r10, 32, 32 // r14 <- count1
+ rsm 1 << 14 // Disable interrupts
+ extr.u r15 = r11, 32, 32 // r15 <- stride1
+ extr.u r10 = r10, 0, 32 // r10 <- count2
+ add r10 = -1, r10
+ extr.u r11 = r11, 0, 32 // r11 <- stride2
+ br.cond.sptk LoopPredicate
+LoopOuter:
+ mov ar.lc = r10 // LC <- count2
+ mov ar.ec = r0 // EC <- 0
+Loop:
+ ptc.e r9
+ add r9 = r11, r9 // r9 += stride2
+ br.ctop.sptk Loop
+ add r9 = r15, r9 // r9 += stride1
+LoopPredicate:
+ cmp.ne p6 = r0, r14 // count1 == 0?
+ add r14 = -1, r14
+(p6) br.cond.sptk LoopOuter
+ mov psr.l = loc2
+ mov b0 = loc1
+ br.ret.sptk.many b0
+.endp
diff --git a/MdePkg/Library/BaseLib/Ipf/CpuPause.s b/MdePkg/Library/BaseLib/Ipf/CpuPause.s new file mode 100644 index 0000000000..f52692f438 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/CpuPause.s @@ -0,0 +1,25 @@ +/// @file
+/// CpuPause() function for Itanium-based architecture.
+///
+/// Copyright (c) 2006, Intel Corporation
+/// All rights reserved. This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: CpuPause.s
+///
+///
+
+.auto
+.text
+
+.proc CpuPause
+.type CpuPause, @function
+CpuPause::
+ hint @pause
+ br.ret.sptk.many b0
+.endp
diff --git a/MdePkg/Library/BaseLib/Ipf/ExecFc.s b/MdePkg/Library/BaseLib/Ipf/ExecFc.s new file mode 100644 index 0000000000..a5a9e9bc8a --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/ExecFc.s @@ -0,0 +1,66 @@ +/// @file
+/// IPF specific AsmFc() and AsmFci () functions
+///
+/// Copyright (c) 2006, Intel Corporation
+/// All rights reserved. This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: ExecFc.s
+///
+///
+
+//---------------------------------------------------------------------------------
+//++
+// AsmFc
+//
+// This routine is used to execute a FC instruction on the specific address.
+//
+// Arguments :
+//
+// On Entry : The specific address need to execute FC instruction.
+//
+// Return Value: The specific address have been execute FC instruction.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmFc, @function
+.proc AsmFc
+.regstk 1, 0, 0, 0
+
+AsmFc::
+ fc in0
+ mov r8 = in0;;
+ br.ret.dpnt b0;;
+.endp AsmFc
+
+
+//---------------------------------------------------------------------------------
+//++
+// AsmFci
+//
+// This routine is used to execute a FC.i instruction on the specific address.
+//
+// Arguments :
+//
+// On Entry : The specific address need to execute FC.i instruction.
+//
+// Return Value: The specific address have been execute FC.i instruction.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmFci, @function
+.proc AsmFci
+.regstk 1, 0, 0, 0
+
+AsmFci::
+ fc.i in0
+ mov r8 = in0;;
+ br.ret.dpnt b0;;
+.endp AsmFci
\ No newline at end of file diff --git a/MdePkg/Library/BaseLib/Ipf/FlushCacheRange.s b/MdePkg/Library/BaseLib/Ipf/FlushCacheRange.s new file mode 100644 index 0000000000..6e467f0d13 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/FlushCacheRange.s @@ -0,0 +1,96 @@ +//++
+// Copyright (c) 2006, Intel Corporation
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Module Name:
+// FlushCacheRange.s
+//
+// Abstract:
+// Assemble routine to flush cache lines
+//
+// Revision History:
+//
+//--
+.file "IpfCpuCache.s"
+
+#include "IpfMacro.i"
+//#include "IpfDefines.h"
+
+//
+// Invalidates a range of instruction cache lines in the cache coherency domain
+// of the calling CPU.
+//
+// Invalidates the instruction cache lines specified by Address and Length. If
+// Address is not aligned on a cache line boundary, then entire instruction
+// cache line containing Address is invalidated. If Address + Length is not
+// aligned on a cache line boundary, then the entire instruction cache line
+// containing Address + Length -1 is invalidated. This function may choose to
+// invalidate the entire instruction cache if that is more efficient than
+// invalidating the specified range. If Length is 0, the no instruction cache
+// lines are invalidated. Address is returned.
+//
+// If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+//
+// @param Address The base address of the instruction cache lines to
+// invalidate. If the CPU is in a physical addressing mode, then
+// Address is a physical address. If the CPU is in a virtual
+// addressing mode, then Address is a virtual address.
+//
+// @param Length The number of bytes to invalidate from the instruction cache.
+//
+// @return Address
+//
+// VOID *
+// EFIAPI
+// IpfFlushCacheRange (
+// IN VOID *Address,
+// IN UINTN Length
+// );
+//
+PROCEDURE_ENTRY (IpfFlushCacheRange)
+
+ NESTED_SETUP (5,8,0,0)
+
+ mov loc2 = ar.lc
+
+ mov loc3 = in0 // Start address.
+ mov loc4 = in1;; // Length in bytes.
+
+ cmp.eq p6,p7 = loc4, r0;; // If Length is zero then don't flush any cache
+ (p6) br.spnt.many DoneFlushingC;;
+
+ add loc4 = loc4,loc3
+ mov loc5 = 1;;
+ sub loc4 = loc4, loc5 ;; // the End address to flush
+
+ dep loc3 = r0,loc3,0,5
+ dep loc4 = r0,loc4,0,5;;
+ shr loc3 = loc3,5
+ shr loc4 = loc4,5;; // 32 byte cache line
+
+ sub loc4 = loc4,loc3;; // total flush count, It should be add 1 but
+ // the br.cloop will first execute one time
+ mov loc3 = in0
+ mov loc5 = 32
+ mov ar.lc = loc4;;
+
+StillFlushingC:
+ fc loc3;;
+ sync.i;;
+ srlz.i;;
+ add loc3 = loc5,loc3;;
+ br.cloop.sptk.few StillFlushingC;;
+
+DoneFlushingC:
+ mov ar.lc = loc2
+ mov r8 = in0 // return *Address
+ NESTED_RETURN
+
+PROCEDURE_EXIT (IpfFlushCacheRange)
+
diff --git a/MdePkg/Library/BaseLib/Ipf/GetInterruptState.s b/MdePkg/Library/BaseLib/Ipf/GetInterruptState.s new file mode 100644 index 0000000000..d5b5fc852f --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/GetInterruptState.s @@ -0,0 +1,27 @@ +/// @file
+/// Retrieve of the interrupt state of the running processor for the Itanium
+/// architecture.
+///
+/// Copyright (c) 2006, Intel Corporation
+/// All rights reserved. This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: GetInterruptState.s
+///
+///
+
+.auto
+.text
+
+.proc GetInterruptState
+.type GetInterruptState, @function
+GetInterruptState::
+ mov r8 = psr
+ extr.u r8 = r8, 14, 1
+ br.ret.sptk.many b0
+.endp GetInterruptState
diff --git a/MdePkg/Library/BaseLib/Ipf/InterlockedCompareExchange32.s b/MdePkg/Library/BaseLib/Ipf/InterlockedCompareExchange32.s new file mode 100644 index 0000000000..3a278d7268 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/InterlockedCompareExchange32.s @@ -0,0 +1,29 @@ +/// @file
+/// Contains an implementation of InterlockedCompareExchange32 on Itanium-
+/// based architecture.
+///
+/// Copyright (c) 2006, Intel Corporation
+/// All rights reserved. This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: InterlockedCompareExchange32.s
+///
+///
+
+.auto
+.text
+
+.proc InternalSyncCompareExchange32
+.type InternalSyncCompareExchange32, @function
+InternalSyncCompareExchange32::
+ zxt4 r33 = r33
+ mov ar.ccv = r33
+ cmpxchg4.rel r8 = [r32], r34
+ mf
+ br.ret.sptk.many b0
+.endp InternalSyncCompareExchange32
\ No newline at end of file diff --git a/MdePkg/Library/BaseLib/Ipf/InterlockedCompareExchange64.s b/MdePkg/Library/BaseLib/Ipf/InterlockedCompareExchange64.s new file mode 100644 index 0000000000..88b9d2b490 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/InterlockedCompareExchange64.s @@ -0,0 +1,28 @@ +/// @file
+/// Contains an implementation of InterlockedCompareExchange64 on Itanium-
+/// based architecture.
+///
+/// Copyright (c) 2006, Intel Corporation
+/// All rights reserved. This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: InterlockedCompareExchange64.s
+///
+///
+
+.auto
+.text
+
+.proc InternalSyncCompareExchange64
+.type InternalSyncCompareExchange64, @function
+InternalSyncCompareExchange64::
+ mov ar.ccv = r33
+ cmpxchg8.rel r8 = [r32], r34
+ mf
+ br.ret.sptk.many b0
+.endp InternalSyncCompareExchange64
\ No newline at end of file diff --git a/MdePkg/Library/BaseLib/Ipf/InternalSwitchStack.c b/MdePkg/Library/BaseLib/Ipf/InternalSwitchStack.c new file mode 100644 index 0000000000..60d0a37562 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/InternalSwitchStack.c @@ -0,0 +1,68 @@ +/** @file
+ SwitchStack() function for IPF.
+
+ Copyright (c) 2007, Intel Corporation<BR>
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Module Name: InternalSwitchStack.c
+
+**/
+
+#include <BaseLibInternals.h>
+
+/** + Transfers control to a function starting with a new stack. + + Transfers control to the function specified by EntryPoint using the + new stack specified by NewStack and passing in the parameters specified + by Context1 and Context2. Context1 and Context2 are optional and may + be NULL. The function EntryPoint must never return. + Marker will be ignored on IA-32, x64, and EBC. + IPF CPUs expect one additional parameter of type VOID * that specifies + the new backing store pointer.
+ + If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+ + @param EntryPoint A pointer to function to call with the new stack. + @param Context1 A pointer to the context to pass into the EntryPoint + function. + @param Context2 A pointer to the context to pass into the EntryPoint + function. + @param NewStack A pointer to the new stack to use for the EntryPoint + function.
+ @param Marker VA_LIST marker for the variable argument list. + +**/
+VOID +EFIAPI +InternalSwitchStack ( + IN SWITCH_STACK_ENTRY_POINT EntryPoint, + IN VOID *Context1, OPTIONAL + IN VOID *Context2, OPTIONAL + IN VOID *NewStack, + IN VA_LIST Marker + )
+
+{
+ VOID *NewBsp;
+
+ //
+ // Get new backing store pointer from variable list
+ //
+ NewBsp = VA_ARG (Marker, VOID *);
+
+ //
+ // Stack should be aligned with CPU_STACK_ALIGNMENT
+ //
+ ASSERT (((UINTN)NewStack & (CPU_STACK_ALIGNMENT - 1)) == 0);
+ ASSERT (((UINTN)NewBsp & (CPU_STACK_ALIGNMENT - 1)) == 0);
+
+ AsmSwitchStackAndBackingStore (EntryPoint, Context1, Context2, NewStack, NewBsp);
+}
diff --git a/MdePkg/Library/BaseLib/Ipf/PalCallStatic.s b/MdePkg/Library/BaseLib/Ipf/PalCallStatic.s new file mode 100644 index 0000000000..c21d7427f9 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/PalCallStatic.s @@ -0,0 +1,48 @@ +/// @file
+/// Contains an implementation of CallPalProcStatic on Itanium-based
+/// architecture.
+///
+/// Copyright (c) 2006, Intel Corporation
+/// All rights reserved. This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: PalCallStatic.s
+///
+///
+
+.auto
+.text
+
+.proc PalCallStatic
+.type PalCallStatic, @function
+.regstk 5, 0, 0, 0
+PalCallStatic::
+ cmp.eq p15 = in0, r0
+ mov r31 = in4
+ mov r8 = ip
+
+(p15) mov in0 = ar.k5
+ add r8 = (_PalProcReturn - PalCallStatic), r8
+ mov r30 = in3
+
+ mov in4 = psr
+ mov in3 = b0
+ mov b7 = in0
+
+ rsm 1 << 14 // Disable interrupts
+ mov r29 = in2
+ mov r28 = in1
+
+ mov b0 = r8
+ br.cond.sptk.many b7
+
+_PalProcReturn:
+ mov psr.l = in4
+ mov b0 = in3
+ br.ret.sptk.many b0
+.endp PalCallStatic
diff --git a/MdePkg/Library/BaseLib/Ipf/ReadCpuid.s b/MdePkg/Library/BaseLib/Ipf/ReadCpuid.s new file mode 100644 index 0000000000..2176dad116 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/ReadCpuid.s @@ -0,0 +1,40 @@ +/// @file
+/// IPF specific AsmReadCpuid()function
+///
+/// Copyright (c) 2006, Intel Corporation
+/// All rights reserved. This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: ReadCpuid.s
+///
+///
+
+//---------------------------------------------------------------------------------
+//++
+// AsmReadCpuid
+//
+// This routine is used to Reads the current value of Processor Identifier Register (CPUID).
+//
+// Arguments :
+//
+// On Entry : The 8-bit Processor Identifier Register index to read.
+//
+// Return Value: The current value of Processor Identifier Register specified by Index.
+//
+//--
+//----------------------------------------------------------------------------------
+.text
+.type AsmReadCpuid, @function
+.proc AsmReadCpuid
+.regstk 1, 0, 0, 0
+
+AsmReadCpuid::
+ mov r8 = cpuid[in0];;
+ br.ret.dpnt b0;;
+.endp AsmReadCpuid
+
diff --git a/MdePkg/Library/BaseLib/Ipf/SwitchStack.s b/MdePkg/Library/BaseLib/Ipf/SwitchStack.s new file mode 100644 index 0000000000..a3c524f119 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/SwitchStack.s @@ -0,0 +1,50 @@ +/// @file
+/// IPF specific SwitchStack() function
+///
+/// Copyright (c) 2006, Intel Corporation
+/// All rights reserved. This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: SwitchStack.s
+///
+///
+
+.auto
+.text
+
+.proc AsmSwitchStackAndBackingStore
+.type AsmSwitchStackAndBackingStore, @function
+.regstk 5, 0, 0, 0
+AsmSwitchStackAndBackingStore::
+ mov r14 = ar.rsc
+ movl r2 = ~((((1 << 14) - 1) << 16) | 3)
+
+ mov r17 = in1
+ mov r18 = in2
+ and r2 = r14, r2
+
+ mov ar.rsc = r2
+ mov sp = in3
+ mov r19 = in4
+
+ ld8.nt1 r16 = [in0], 8
+ ld8.nta gp = [in0]
+ mov r3 = -1
+
+ loadrs
+ mov ar.bspstore = r19
+ mov b7 = r16
+
+ alloc r2 = ar.pfs, 0, 0, 2, 0
+ mov out0 = r17
+ mov out1 = r18
+
+ mov ar.rnat = r3
+ mov ar.rsc = r14
+ br.call.sptk.many b0 = b7
+.endp AsmSwitchStackAndBackingStore
diff --git a/MdePkg/Library/BaseLib/Ipf/Synchronization.c b/MdePkg/Library/BaseLib/Ipf/Synchronization.c new file mode 100644 index 0000000000..c29a8763d3 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/Synchronization.c @@ -0,0 +1,79 @@ +/** @file
+ Implementation of synchronization functions on Itanium.
+
+ Copyright (c) 2006, Intel Corporation<BR>
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Module Name: Synchronization.c
+
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Performs an atomic increment of an 32-bit unsigned integer.
+
+ Performs an atomic increment of the 32-bit unsigned integer specified by
+ Value and returns the incremented value. The increment operation must be
+ performed using MP safe mechanisms. The state of the return value is not
+ guaranteed to be MP safe.
+
+ @param Value A pointer to the 32-bit value to increment.
+
+ @return The incremented value.
+
+**/
+UINT32
+EFIAPI
+InternalSyncIncrement (
+ IN volatile UINT32 *Value
+ )
+{
+ UINT32 OriginalValue;
+
+ do {
+ OriginalValue = *Value;
+ } while (OriginalValue != InternalSyncCompareExchange32 (
+ Value,
+ OriginalValue,
+ OriginalValue + 1
+ ));
+ return OriginalValue + 1;
+}
+
+/**
+ Performs an atomic decrement of an 32-bit unsigned integer.
+
+ Performs an atomic decrement of the 32-bit unsigned integer specified by
+ Value and returns the decrement value. The decrement operation must be
+ performed using MP safe mechanisms. The state of the return value is not
+ guaranteed to be MP safe.
+
+ @param Value A pointer to the 32-bit value to decrement.
+
+ @return The decrement value.
+
+**/
+UINT32
+EFIAPI
+InternalSyncDecrement (
+ IN volatile UINT32 *Value
+ )
+{
+ UINT32 OriginalValue;
+
+ do {
+ OriginalValue = *Value;
+ } while (OriginalValue != InternalSyncCompareExchange32 (
+ Value,
+ OriginalValue,
+ OriginalValue - 1
+ ));
+ return OriginalValue - 1;
+}
diff --git a/MdePkg/Library/BaseLib/Ipf/Unaligned.c b/MdePkg/Library/BaseLib/Ipf/Unaligned.c new file mode 100644 index 0000000000..1c4a937ab9 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/Unaligned.c @@ -0,0 +1,248 @@ +/** @file
+ Unaligned access functions of BaseLib for IPF.
+
+ Copyright (c) 2006, Intel Corporation<BR>
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Module Name: Unaligned.c
+
+**/
+
+//
+// Include common header file for this module.
+//
+#include <BaseLibInternals.h>
+
+/**
+ Reads a 16-bit value from memory that may be unaligned.
+
+ This function returns the 16-bit value pointed to by Buffer. The function
+ guarantees that the read operation does not produce an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer Pointer to a 16-bit value that may be unaligned.
+
+ @return *Uint16
+
+**/
+UINT16
+EFIAPI
+ReadUnaligned16 (
+ IN CONST UINT16 *Buffer
+ )
+{
+ ASSERT (Buffer != NULL);
+
+ return (UINT16)(((UINT8*)Buffer)[0] | (((UINT8*)Buffer)[1] << 8));
+}
+
+/**
+ Writes a 16-bit value to memory that may be unaligned.
+
+ This function writes the 16-bit value specified by Value to Buffer. Value is
+ returned. The function guarantees that the write operation does not produce
+ an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer Pointer to a 16-bit value that may be unaligned.
+ @param Value 16-bit value to write to Buffer.
+
+ @return Value
+
+**/
+UINT16
+EFIAPI
+WriteUnaligned16 (
+ OUT UINT16 *Buffer,
+ IN UINT16 Value
+ )
+{
+ ASSERT (Buffer != NULL);
+
+ ((UINT8*)Buffer)[0] = (UINT8)Value;
+ ((UINT8*)Buffer)[1] = (UINT8)(Value >> 8);
+
+ return Value;
+}
+
+/**
+ Reads a 24-bit value from memory that may be unaligned.
+
+ This function returns the 24-bit value pointed to by Buffer. The function
+ guarantees that the read operation does not produce an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer Pointer to a 24-bit value that may be unaligned.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+ReadUnaligned24 (
+ IN CONST UINT32 *Buffer
+ )
+{
+ ASSERT (Buffer != NULL);
+
+ return (UINT32)(
+ ReadUnaligned16 ((UINT16*)Buffer) |
+ (((UINT8*)Buffer)[2] << 16)
+ );
+}
+
+/**
+ Writes a 24-bit value to memory that may be unaligned.
+
+ This function writes the 24-bit value specified by Value to Buffer. Value is
+ returned. The function guarantees that the write operation does not produce
+ an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer Pointer to a 24-bit value that may be unaligned.
+ @param Value 24-bit value to write to Buffer.
+
+ @return The value written.
+
+**/
+UINT32
+EFIAPI
+WriteUnaligned24 (
+ OUT UINT32 *Buffer,
+ IN UINT32 Value
+ )
+{
+ ASSERT (Buffer != NULL);
+
+ WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
+ *(UINT8*)((UINT16*)Buffer + 1) = (UINT8)(Value >> 16);
+ return Value;
+}
+
+/**
+ Reads a 32-bit value from memory that may be unaligned.
+
+ This function returns the 32-bit value pointed to by Buffer. The function
+ guarantees that the read operation does not produce an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer Pointer to a 32-bit value that may be unaligned.
+
+ @return *Uint32
+
+**/
+UINT32
+EFIAPI
+ReadUnaligned32 (
+ IN CONST UINT32 *Buffer
+ )
+{
+ UINT16 LowerBytes;
+ UINT16 HigherBytes;
+
+ ASSERT (Buffer != NULL);
+
+ LowerBytes = ReadUnaligned16 ((UINT16*) Buffer);
+ HigherBytes = ReadUnaligned16 ((UINT16*) Buffer + 1);
+
+ return (UINT32) (LowerBytes | (HigherBytes << 16));
+}
+
+/**
+ Writes a 32-bit value to memory that may be unaligned.
+
+ This function writes the 32-bit value specified by Value to Buffer. Value is
+ returned. The function guarantees that the write operation does not produce
+ an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer Pointer to a 32-bit value that may be unaligned.
+ @param Value 32-bit value to write to Buffer.
+
+ @return Value
+
+**/
+UINT32
+EFIAPI
+WriteUnaligned32 (
+ OUT UINT32 *Buffer,
+ IN UINT32 Value
+ )
+{
+ ASSERT (Buffer != NULL);
+
+ WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
+ WriteUnaligned16 ((UINT16*)Buffer + 1, (UINT16)(Value >> 16));
+ return Value;
+}
+
+/**
+ Reads a 64-bit value from memory that may be unaligned.
+
+ This function returns the 64-bit value pointed to by Buffer. The function
+ guarantees that the read operation does not produce an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer Pointer to a 64-bit value that may be unaligned.
+
+ @return *Uint64
+
+**/
+UINT64
+EFIAPI
+ReadUnaligned64 (
+ IN CONST UINT64 *Buffer
+ )
+{
+ UINT32 LowerBytes;
+ UINT32 HigherBytes;
+
+ ASSERT (Buffer != NULL);
+
+ LowerBytes = ReadUnaligned32 ((UINT32*) Buffer);
+ HigherBytes = ReadUnaligned32 ((UINT32*) Buffer + 1);
+
+ return (UINT64) (LowerBytes | LShiftU64 (HigherBytes, 32));
+}
+
+/**
+ Writes a 64-bit value to memory that may be unaligned.
+
+ This function writes the 64-bit value specified by Value to Buffer. Value is
+ returned. The function guarantees that the write operation does not produce
+ an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer Pointer to a 64-bit value that may be unaligned.
+ @param Value 64-bit value to write to Buffer.
+
+ @return Value
+
+**/
+UINT64
+EFIAPI
+WriteUnaligned64 (
+ OUT UINT64 *Buffer,
+ IN UINT64 Value
+ )
+{
+ ASSERT (Buffer != NULL);
+
+ WriteUnaligned32 ((UINT32*)Buffer, (UINT32)Value);
+ WriteUnaligned32 ((UINT32*)Buffer + 1, (UINT32)RShiftU64 (Value, 32));
+ return Value;
+}
diff --git a/MdePkg/Library/BaseLib/Ipf/asm.h b/MdePkg/Library/BaseLib/Ipf/asm.h new file mode 100644 index 0000000000..8ef0b30626 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/asm.h @@ -0,0 +1,27 @@ +/// @file
+/// This module contains generic macros for an assembly writer.
+///
+/// Copyright (c) 2006, Intel Corporation<BR>
+/// All rights reserved. This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: asm.h
+///
+#ifndef _ASM_H
+#define _ASM_H
+
+#define TRUE 1
+#define FALSE 0
+#define PROCEDURE_ENTRY(name) .##text; \
+ .##type name, @function; \
+ .##proc name; \
+ name::
+
+#define PROCEDURE_EXIT(name) .##endp name
+
+#endif // _ASM_H
diff --git a/MdePkg/Library/BaseLib/Ipf/ia_64gen.h b/MdePkg/Library/BaseLib/Ipf/ia_64gen.h new file mode 100644 index 0000000000..081cc4a8f6 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/ia_64gen.h @@ -0,0 +1,205 @@ +/// @file
+///
+///
+/// Copyright (c) 2006, Intel Corporation<BR>
+/// All rights reserved. This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: ia_64gen.h
+///
+#ifndef _IA64GEN_H
+#define _IA64GEN_H
+
+#define TT_UNAT 0
+#define C_PSR 0
+#define J_UNAT 0
+#define T_TYPE 0
+#define T_IPSR 0x8
+#define T_ISR 0x10
+#define T_IIP 0x18
+#define T_IFA 0x20
+#define T_IIPA 0x28
+#define T_IFS 0x30
+#define T_IIM 0x38
+#define T_RSC 0x40
+#define T_BSP 0x48
+#define T_BSPSTORE 0x50
+#define T_RNAT 0x58
+#define T_PFS 0x60
+#define T_KBSPSTORE 0x68
+#define T_UNAT 0x70
+#define T_CCV 0x78
+#define T_DCR 0x80
+#define T_PREDS 0x88
+#define T_NATS 0x90
+#define T_R1 0x98
+#define T_GP 0x98
+#define T_R2 0xa0
+#define T_R3 0xa8
+#define T_R4 0xb0
+#define T_R5 0xb8
+#define T_R6 0xc0
+#define T_R7 0xc8
+#define T_R8 0xd0
+#define T_R9 0xd8
+#define T_R10 0xe0
+#define T_R11 0xe8
+#define T_R12 0xf0
+#define T_SP 0xf0
+#define T_R13 0xf8
+#define T_R14 0x100
+#define T_R15 0x108
+#define T_R16 0x110
+#define T_R17 0x118
+#define T_R18 0x120
+#define T_R19 0x128
+#define T_R20 0x130
+#define T_R21 0x138
+#define T_R22 0x140
+#define T_R23 0x148
+#define T_R24 0x150
+#define T_R25 0x158
+#define T_R26 0x160
+#define T_R27 0x168
+#define T_R28 0x170
+#define T_R29 0x178
+#define T_R30 0x180
+#define T_R31 0x188
+#define T_F2 0x1f0
+#define T_F3 0x200
+#define T_F4 0x210
+#define T_F5 0x220
+#define T_F6 0x230
+#define T_F7 0x240
+#define T_F8 0x250
+#define T_F9 0x260
+#define T_F10 0x270
+#define T_F11 0x280
+#define T_F12 0x290
+#define T_F13 0x2a0
+#define T_F14 0x2b0
+#define T_F15 0x2c0
+#define T_F16 0x2d0
+#define T_F17 0x2e0
+#define T_F18 0x2f0
+#define T_F19 0x300
+#define T_F20 0x310
+#define T_F21 0x320
+#define T_F22 0x330
+#define T_F23 0x340
+#define T_F24 0x350
+#define T_F25 0x360
+#define T_F26 0x370
+#define T_F27 0x380
+#define T_F28 0x390
+#define T_F29 0x3a0
+#define T_F30 0x3b0
+#define T_F31 0x3c0
+#define T_FPSR 0x1e0
+#define T_B0 0x190
+#define T_B1 0x198
+#define T_B2 0x1a0
+#define T_B3 0x1a8
+#define T_B4 0x1b0
+#define T_B5 0x1b8
+#define T_B6 0x1c0
+#define T_B7 0x1c8
+#define T_EC 0x1d0
+#define T_LC 0x1d8
+#define J_NATS 0x8
+#define J_PFS 0x10
+#define J_BSP 0x18
+#define J_RNAT 0x20
+#define J_PREDS 0x28
+#define J_LC 0x30
+#define J_R4 0x38
+#define J_R5 0x40
+#define J_R6 0x48
+#define J_R7 0x50
+#define J_SP 0x58
+#define J_F2 0x60
+#define J_F3 0x70
+#define J_F4 0x80
+#define J_F5 0x90
+#define J_F16 0xa0
+#define J_F17 0xb0
+#define J_F18 0xc0
+#define J_F19 0xd0
+#define J_F20 0xe0
+#define J_F21 0xf0
+#define J_F22 0x100
+#define J_F23 0x110
+#define J_F24 0x120
+#define J_F25 0x130
+#define J_F26 0x140
+#define J_F27 0x150
+#define J_F28 0x160
+#define J_F29 0x170
+#define J_F30 0x180
+#define J_F31 0x190
+#define J_FPSR 0x1a0
+#define J_B0 0x1a8
+#define J_B1 0x1b0
+#define J_B2 0x1b8
+#define J_B3 0x1c0
+#define J_B4 0x1c8
+#define J_B5 0x1d0
+#define TRAP_FRAME_LENGTH 0x3d0
+#define C_UNAT 0x28
+#define C_NATS 0x30
+#define C_PFS 0x8
+#define C_BSPSTORE 0x10
+#define C_RNAT 0x18
+#define C_RSC 0x20
+#define C_PREDS 0x38
+#define C_LC 0x40
+#define C_DCR 0x48
+#define C_R1 0x50
+#define C_GP 0x50
+#define C_R4 0x58
+#define C_R5 0x60
+#define C_R6 0x68
+#define C_R7 0x70
+#define C_SP 0x78
+#define C_R13 0x80
+#define C_F2 0x90
+#define C_F3 0xa0
+#define C_F4 0xb0
+#define C_F5 0xc0
+#define C_F16 0xd0
+#define C_F17 0xe0
+#define C_F18 0xf0
+#define C_F19 0x100
+#define C_F20 0x110
+#define C_F21 0x120
+#define C_F22 0x130
+#define C_F23 0x140
+#define C_F24 0x150
+#define C_F25 0x160
+#define C_F26 0x170
+#define C_F27 0x180
+#define C_F28 0x190
+#define C_F29 0x1a0
+#define C_F30 0x1b0
+#define C_F31 0x1c0
+#define C_FPSR 0x1d0
+#define C_B0 0x1d8
+#define C_B1 0x1e0
+#define C_B2 0x1e8
+#define C_B3 0x1f0
+#define C_B4 0x1f8
+#define C_B5 0x200
+#define TT_R2 0x8
+#define TT_R3 0x10
+#define TT_R8 0x18
+#define TT_R9 0x20
+#define TT_R10 0x28
+#define TT_R11 0x30
+#define TT_R14 0x38
+
+#endif _IA64GEN_H
diff --git a/MdePkg/Library/BaseLib/Ipf/longjmp.s b/MdePkg/Library/BaseLib/Ipf/longjmp.s new file mode 100644 index 0000000000..20a0df10f7 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/longjmp.s @@ -0,0 +1,121 @@ +/// @file
+/// Contains an implementation of longjmp for the Itanium-based architecture.
+///
+/// Copyright (c) 2006, Intel Corporation
+/// All rights reserved. This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: longjmp.s
+///
+///
+
+.auto
+.text
+
+.proc InternalLongJump
+.type InternalLongJump, @function
+.regstk 2, 0, 0, 0
+InternalLongJump::
+ add r10 = 0x10*20 + 8*14, in0
+ movl r2 = ~((((1 << 14) - 1) << 16) | 3)
+
+ ld8.nt1 r14 = [r10], -8*2 // BSP, skip PFS
+ mov r15 = ar.bspstore // BSPSTORE
+
+ ld8.nt1 r17 = [r10], -8 // UNAT after spill
+ mov r16 = ar.rsc // RSC
+ cmp.leu p6 = r14, r15
+
+ ld8.nt1 r18 = [r10], -8 // UNAT
+ ld8.nt1 r25 = [r10], -8 // b5
+ and r2 = r16, r2
+
+ ldf.fill.nt1 f2 = [in0], 0x10
+ ld8.nt1 r24 = [r10], -8 // b4
+ mov b5 = r25
+
+ mov ar.rsc = r2
+ ld8.nt1 r23 = [r10], -8 // b3
+ mov b4 = r24
+
+ ldf.fill.nt1 f3 = [in0], 0x10
+ mov ar.unat = r17
+(p6) br.spnt.many _skip_flushrs
+
+ flushrs
+ mov r15 = ar.bsp // New BSPSTORE
+
+_skip_flushrs:
+ mov r31 = ar.rnat // RNAT
+ loadrs
+
+ ldf.fill.nt1 f4 = [in0], 0x10
+ ld8.nt1 r22 = [r10], -8
+ dep r2 = -1, r14, 3, 6
+
+ ldf.fill.nt1 f5 = [in0], 0x10
+ ld8.nt1 r21 = [r10], -8
+ cmp.ltu p6 = r2, r15
+
+ ld8.nt1 r20 = [r10], -0x10 // skip sp
+(p6) ld8.nta r31 = [r2]
+ mov b3 = r23
+
+ ldf.fill.nt1 f16 = [in0], 0x10
+ ld8.fill.nt1 r7 = [r10], -8
+ mov b2 = r22
+
+ ldf.fill.nt1 f17 = [in0], 0x10
+ ld8.fill.nt1 r6 = [r10], -8
+ mov b1 = r21
+
+ ldf.fill.nt1 f18 = [in0], 0x10
+ ld8.fill.nt1 r5 = [r10], -8
+ mov b0 = r20
+
+ ldf.fill.nt1 f19 = [in0], 0x10
+ ld8.fill.nt1 r4 = [r10], 8*13
+
+ ldf.fill.nt1 f20 = [in0], 0x10
+ ld8.nt1 r19 = [r10], 0x10 // PFS
+
+ ldf.fill.nt1 f21 = [in0], 0x10
+ ld8.nt1 r26 = [r10], 8 // Predicate
+ mov ar.pfs = r19
+
+ ldf.fill.nt1 f22 = [in0], 0x10
+ ld8.nt1 r27 = [r10], 8 // LC
+ mov pr = r26, -1
+
+ ldf.fill.nt1 f23 = [in0], 0x10
+ ld8.nt1 r28 = [r10], -17*8 - 0x10
+ mov ar.lc = r27
+
+ ldf.fill.nt1 f24 = [in0], 0x10
+ ldf.fill.nt1 f25 = [in0], 0x10
+ mov r8 = in1
+
+ ldf.fill.nt1 f26 = [in0], 0x10
+ ldf.fill.nt1 f31 = [r10], -0x10
+
+ ldf.fill.nt1 f27 = [in0], 0x10
+ ldf.fill.nt1 f30 = [r10], -0x10
+
+ ldf.fill.nt1 f28 = [in0]
+ ldf.fill.nt1 f29 = [r10], 0x10*3 + 8*4
+
+ ld8.fill.nt1 sp = [r10]
+ mov ar.unat = r18
+
+ mov ar.bspstore = r14
+ mov ar.rnat = r31
+
+ invala
+ mov ar.rsc = r16
+ br.ret.sptk b0
+.endp
diff --git a/MdePkg/Library/BaseLib/Ipf/setjmp.s b/MdePkg/Library/BaseLib/Ipf/setjmp.s new file mode 100644 index 0000000000..e2b346ee72 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/setjmp.s @@ -0,0 +1,108 @@ +/// @file
+/// Contains an implementation of longjmp for the Itanium-based architecture.
+///
+/// Copyright (c) 2006, Intel Corporation
+/// All rights reserved. This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: longjmp.s
+///
+///
+
+.auto
+.text
+
+.globl InternalAssertJumpBuffer
+.type InternalAssertJumpBuffer, @function
+
+.proc SetJump
+.type SetJump, @function
+SetJump::
+ alloc loc0 = ar.pfs, 1, 2, 1, 0
+ mov loc1 = b0
+ mov out0 = in0
+
+ brl.call.sptk.many b0 = InternalAssertJumpBuffer
+
+ mov r14 = ar.unat
+ mov r15 = ar.bsp
+ add r10 = 0x10*20, in0
+
+ stf.spill.nta [in0] = f2, 0x10
+ st8.spill.nta [r10] = r4, 8
+ mov r21 = b1
+
+ stf.spill.nta [in0] = f3, 0x10
+ st8.spill.nta [r10] = r5, 8
+ mov r22 = b2
+
+ stf.spill.nta [in0] = f4, 0x10
+ st8.spill.nta [r10] = r6, 8
+ mov r23 = b3
+
+ stf.spill.nta [in0] = f5, 0x10
+ st8.spill.nta [r10] = r7, 8
+ mov r24 = b4
+
+ stf.spill.nta [in0] = f16, 0x10
+ st8.spill.nta [r10] = sp, 8
+ mov r25 = b5
+
+ stf.spill.nta [in0] = f17, 0x10
+ st8.nta [r10] = loc1, 8
+ mov r16 = pr
+
+ stf.spill.nta [in0] = f18, 0x10
+ st8.nta [r10] = r21, 8
+ mov r17 = ar.lc
+
+ stf.spill.nta [in0] = f19, 0x10
+ st8.nta [r10] = r22, 8
+
+ stf.spill.nta [in0] = f20, 0x10
+ st8.nta [r10] = r23, 8
+
+ stf.spill.nta [in0] = f21, 0x10
+ st8.nta [r10] = r24, 8
+
+ stf.spill.nta [in0] = f22, 0x10
+ st8.nta [r10] = r25, 8
+
+ stf.spill.nta [in0] = f23, 0x10
+ mov r18 = ar.unat
+
+ stf.spill.nta [in0] = f24, 0x10
+ st8.nta [r10] = r14, 8 // UNAT
+
+ stf.spill.nta [in0] = f25, 0x10
+ st8.nta [r10] = r18, 8 // UNAT after spill
+
+ stf.spill.nta [in0] = f26, 0x10
+ st8.nta [r10] = loc0, 8 // PFS
+
+ stf.spill.nta [in0] = f27, 0x10
+ st8.nta [r10] = r15, 8 // BSP
+ mov r8 = 0
+
+ stf.spill.nta [in0] = f28, 0x10
+ mov r19 = ar.fpsr
+
+ stf.spill.nta [in0] = f29, 0x10
+ st8.nta [r10] = r16, 8 // PR
+ mov ar.pfs = loc0
+
+ stf.spill.nta [in0] = f30, 0x10
+ st8.nta [r10] = r17, 8 // LC
+ mov b0 = loc1
+
+ stf.spill.nta [in0] = f31, 0x10
+ st8.nta [r10] = r19 // FPSR
+
+ mov ar.unat = r14
+ br.ret.sptk b0
+.endp SetJump
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