diff options
| author | Jordan Justen <jordan.l.justen@intel.com> | 2016-05-30 18:51:53 -0700 |
|---|---|---|
| committer | Liming Gao <liming.gao@intel.com> | 2016-06-28 09:48:26 +0800 |
| commit | 2c71f739de08b988e146fca2fdc95442bfb71cf0 (patch) | |
| tree | 86100a13ede971a11cb4fb0c66ee4aad4e17698e /MdePkg/Library/BaseLib | |
| parent | 6074ca7022d034f4d5134996d3aef4a55b38fe5d (diff) | |
| download | edk2-platforms-2c71f739de08b988e146fca2fdc95442bfb71cf0.tar.xz | |
MdePkg BaseLib: Convert Ia32/EnablePaging64.asm to NASM
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/EnablePaging64.asm to Ia32/EnablePaging64.nasm
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Diffstat (limited to 'MdePkg/Library/BaseLib')
| -rw-r--r-- | MdePkg/Library/BaseLib/BaseLib.inf | 3 | ||||
| -rw-r--r-- | MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm | 65 |
2 files changed, 68 insertions, 0 deletions
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index 7f511ee520..a429fb1f37 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -158,6 +158,7 @@ Ia32/ARShiftU64.c | MSFT
Ia32/Thunk16.nasm | MSFT
Ia32/Thunk16.asm | MSFT
+ Ia32/EnablePaging64.nasm| MSFT
Ia32/EnablePaging64.asm | MSFT
Ia32/EnableCache.c | MSFT
Ia32/DisableCache.c | MSFT
@@ -254,6 +255,7 @@ Ia32/ARShiftU64.asm | INTEL
Ia32/Thunk16.nasm | INTEL
Ia32/Thunk16.asm | INTEL
+ Ia32/EnablePaging64.nasm| INTEL
Ia32/EnablePaging64.asm | INTEL
Ia32/EnableCache.asm | INTEL
Ia32/DisableCache.asm | INTEL
@@ -263,6 +265,7 @@ Ia32/Thunk16.nasm | GCC
Ia32/Thunk16.S | XCODE
Ia32/EnableDisableInterrupts.S | GCC
+ Ia32/EnablePaging64.nasm| GCC
Ia32/EnablePaging64.S | GCC
Ia32/DisablePaging32.S | GCC
Ia32/EnablePaging32.S | GCC
diff --git a/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm b/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm new file mode 100644 index 0000000000..41f0ed1ce5 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm @@ -0,0 +1,65 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; EnablePaging64.Asm
+;
+; Abstract:
+;
+; AsmEnablePaging64 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86EnablePaging64 (
+; IN UINT16 Cs,
+; IN UINT64 EntryPoint,
+; IN UINT64 Context1, OPTIONAL
+; IN UINT64 Context2, OPTIONAL
+; IN UINT64 NewStack
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86EnablePaging64)
+ASM_PFX(InternalX86EnablePaging64):
+ cli
+ mov DWORD [esp], .0 ; offset for far retf, seg is the 1st arg
+ mov eax, cr4
+ or al, (1 << 5)
+ mov cr4, eax ; enable PAE
+ mov ecx, 0xc0000080
+ rdmsr
+ or ah, 1 ; set LME
+ wrmsr
+ mov eax, cr0
+ bts eax, 31 ; set PG
+ mov cr0, eax ; enable paging
+ retf ; topmost 2 dwords hold the address
+.0:
+ DB 0x67, 0x48 ; 32-bit address size, 64-bit operand size
+ mov ebx, [esp] ; mov rbx, [esp]
+ DB 0x67, 0x48
+ mov ecx, [esp + 8] ; mov rcx, [esp + 8]
+ DB 0x67, 0x48
+ mov edx, [esp + 0x10] ; mov rdx, [esp + 10h]
+ DB 0x67, 0x48
+ mov esp, [esp + 0x18] ; mov rsp, [esp + 18h]
+ DB 0x48
+ add esp, -0x20 ; add rsp, -20h
+ call ebx ; call rbx
+ hlt ; no one should get here
+
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