diff options
| author | xli24 <xli24@6f19259b-4bc3-4df7-8a09-765794883524> | 2007-01-25 06:05:36 +0000 |
|---|---|---|
| committer | xli24 <xli24@6f19259b-4bc3-4df7-8a09-765794883524> | 2007-01-25 06:05:36 +0000 |
| commit | 582510249f2fb1334e507b99421b9485f6b89159 (patch) | |
| tree | cd9d7414885d26e79565cd12ec241af93dc600f2 /MdePkg/Library/DxeIoLibCpuIo | |
| parent | ba3a1cb5bb97ffdea980f188fbd14b08200aeac6 (diff) | |
| download | edk2-platforms-582510249f2fb1334e507b99421b9485f6b89159.tar.xz | |
Make MDE package pass intel IPF compiler with /W4 /WX switched on.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@2312 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdePkg/Library/DxeIoLibCpuIo')
| -rw-r--r-- | MdePkg/Library/DxeIoLibCpuIo/DxeCpuIoLibInternal.h | 107 | ||||
| -rw-r--r-- | MdePkg/Library/DxeIoLibCpuIo/DxeIoLibCpuIo.msa | 1 | ||||
| -rw-r--r-- | MdePkg/Library/DxeIoLibCpuIo/IoHighLevel.c | 24 | ||||
| -rw-r--r-- | MdePkg/Library/DxeIoLibCpuIo/IoLib.c | 2 |
4 files changed, 122 insertions, 12 deletions
diff --git a/MdePkg/Library/DxeIoLibCpuIo/DxeCpuIoLibInternal.h b/MdePkg/Library/DxeIoLibCpuIo/DxeCpuIoLibInternal.h new file mode 100644 index 0000000000..11a5f6eeb8 --- /dev/null +++ b/MdePkg/Library/DxeIoLibCpuIo/DxeCpuIoLibInternal.h @@ -0,0 +1,107 @@ +/** @file
+ Internal include file of DXE CPU IO Library.
+
+ Copyright (c) 2006, Intel Corporation
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Module Name: DxeCpuIoLibInternal.h
+
+**/
+
+#ifndef __DXE_CPUIO_LIB_INTERNAL_H__
+#define __DXE_CPUIO_LIB_INTERNAL_H__
+
+/**
+ Reads registers in the EFI CPU I/O space.
+
+ Reads the I/O port specified by Port with registers width specified by Width.
+ The read value is returned. If such operations are not supported, then ASSERT().
+ This function must guarantee that all I/O read and write operations are serialized.
+
+ @param Port The base address of the I/O operation.
+ The caller is responsible for aligning the Address if required.
+ @param Width The width of the I/O operation.
+
+ @return Data read from registers in the EFI CPU I/O space.
+
+**/
+UINT64
+EFIAPI
+IoReadWorker (
+ IN UINTN Port,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width
+ );
+
+/**
+ Writes registers in the EFI CPU I/O space.
+
+ Writes the I/O port specified by Port with registers width and value specified by Width
+ and Data respectively. Data is returned. If such operations are not supported, then ASSERT().
+ This function must guarantee that all I/O read and write operations are serialized.
+
+ @param Port The base address of the I/O operation.
+ The caller is responsible for aligning the Address if required.
+ @param Width The width of the I/O operation.
+ @param Data The value to write to the I/O port.
+
+ @return The paramter of Data.
+
+**/
+UINT64
+EFIAPI
+IoWriteWorker (
+ IN UINTN Port,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Data
+ );
+
+/**
+ Reads memory-mapped registers in the EFI system memory space.
+
+ Reads the MMIO registers specified by Address with registers width specified by Width.
+ The read value is returned. If such operations are not supported, then ASSERT().
+ This function must guarantee that all MMIO read and write operations are serialized.
+
+ @param Address The MMIO register to read.
+ The caller is responsible for aligning the Address if required.
+ @param Width The width of the I/O operation.
+
+ @return Data read from registers in the EFI system memory space.
+
+**/
+UINT64
+EFIAPI
+MmioReadWorker (
+ IN UINTN Address,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width
+ );
+
+/**
+ Writes memory-mapped registers in the EFI system memory space.
+
+ Writes the MMIO registers specified by Address with registers width and value specified by Width
+ and Data respectively. Data is returned. If such operations are not supported, then ASSERT().
+ This function must guarantee that all MMIO read and write operations are serialized.
+
+ @param Address The MMIO register to read.
+ The caller is responsible for aligning the Address if required.
+ @param Width The width of the I/O operation.
+
+ @return Data read from registers in the EFI system memory space.
+
+**/
+UINT64
+EFIAPI
+MmioWriteWorker (
+ IN UINTN Address,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Data
+ );
+
+#endif
diff --git a/MdePkg/Library/DxeIoLibCpuIo/DxeIoLibCpuIo.msa b/MdePkg/Library/DxeIoLibCpuIo/DxeIoLibCpuIo.msa index c570679b15..8309d58192 100644 --- a/MdePkg/Library/DxeIoLibCpuIo/DxeIoLibCpuIo.msa +++ b/MdePkg/Library/DxeIoLibCpuIo/DxeIoLibCpuIo.msa @@ -39,6 +39,7 @@ <SourceFiles>
<Filename>IoLib.c</Filename>
<Filename>IoHighLevel.c</Filename>
+ <Filename>DxeCpuIoLibInternal.h</Filename>
</SourceFiles>
<PackageDependencies>
<Package PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
diff --git a/MdePkg/Library/DxeIoLibCpuIo/IoHighLevel.c b/MdePkg/Library/DxeIoLibCpuIo/IoHighLevel.c index 0d8d0de8f4..ed09b4e5aa 100644 --- a/MdePkg/Library/DxeIoLibCpuIo/IoHighLevel.c +++ b/MdePkg/Library/DxeIoLibCpuIo/IoHighLevel.c @@ -48,7 +48,7 @@ IoOr8 ( IN UINT8 OrData
)
{
- return IoWrite8 (Port, IoRead8 (Port) | OrData);
+ return IoWrite8 (Port, (UINT8) (IoRead8 (Port) | OrData));
}
/**
@@ -76,7 +76,7 @@ IoAnd8 ( IN UINT8 AndData
)
{
- return IoWrite8 (Port, IoRead8 (Port) & AndData);
+ return IoWrite8 (Port, (UINT8) (IoRead8 (Port) & AndData));
}
/**
@@ -107,7 +107,7 @@ IoAndThenOr8 ( IN UINT8 OrData
)
{
- return IoWrite8 (Port, (IoRead8 (Port) & AndData) | OrData);
+ return IoWrite8 (Port, (UINT8) ((IoRead8 (Port) & AndData) | OrData));
}
/**
@@ -328,7 +328,7 @@ IoOr16 ( IN UINT16 OrData
)
{
- return IoWrite16 (Port, IoRead16 (Port) | OrData);
+ return IoWrite16 (Port, (UINT16) (IoRead16 (Port) | OrData));
}
/**
@@ -356,7 +356,7 @@ IoAnd16 ( IN UINT16 AndData
)
{
- return IoWrite16 (Port, IoRead16 (Port) & AndData);
+ return IoWrite16 (Port, (UINT16) (IoRead16 (Port) & AndData));
}
/**
@@ -387,7 +387,7 @@ IoAndThenOr16 ( IN UINT16 OrData
)
{
- return IoWrite16 (Port, (IoRead16 (Port) & AndData) | OrData);
+ return IoWrite16 (Port, (UINT16) ((IoRead16 (Port) & AndData) | OrData));
}
/**
@@ -1168,7 +1168,7 @@ MmioOr8 ( IN UINT8 OrData
)
{
- return MmioWrite8 (Address, MmioRead8 (Address) | OrData);
+ return MmioWrite8 (Address, (UINT8) (MmioRead8 (Address) | OrData));
}
/**
@@ -1196,7 +1196,7 @@ MmioAnd8 ( IN UINT8 AndData
)
{
- return MmioWrite8 (Address, MmioRead8 (Address) & AndData);
+ return MmioWrite8 (Address, (UINT8) (MmioRead8 (Address) & AndData));
}
/**
@@ -1228,7 +1228,7 @@ MmioAndThenOr8 ( IN UINT8 OrData
)
{
- return MmioWrite8 (Address, (MmioRead8 (Address) & AndData) | OrData);
+ return MmioWrite8 (Address, (UINT8) ((MmioRead8 (Address) & AndData) | OrData));
}
/**
@@ -1450,7 +1450,7 @@ MmioOr16 ( IN UINT16 OrData
)
{
- return MmioWrite16 (Address, MmioRead16 (Address) | OrData);
+ return MmioWrite16 (Address, (UINT16) (MmioRead16 (Address) | OrData));
}
/**
@@ -1478,7 +1478,7 @@ MmioAnd16 ( IN UINT16 AndData
)
{
- return MmioWrite16 (Address, MmioRead16 (Address) & AndData);
+ return MmioWrite16 (Address, (UINT16) (MmioRead16 (Address) & AndData));
}
/**
@@ -1510,7 +1510,7 @@ MmioAndThenOr16 ( IN UINT16 OrData
)
{
- return MmioWrite16 (Address, (MmioRead16 (Address) & AndData) | OrData);
+ return MmioWrite16 (Address, (UINT16) ((MmioRead16 (Address) & AndData) | OrData));
}
/**
diff --git a/MdePkg/Library/DxeIoLibCpuIo/IoLib.c b/MdePkg/Library/DxeIoLibCpuIo/IoLib.c index 4736c561dc..64ba3480ef 100644 --- a/MdePkg/Library/DxeIoLibCpuIo/IoLib.c +++ b/MdePkg/Library/DxeIoLibCpuIo/IoLib.c @@ -14,6 +14,8 @@ **/
+#include "DxeCpuIoLibInternal.h"
+
//
// Globle varible to cache pointer to CpuIo protocol.
//
|