1. Add address check for "RegisterForRuntime" APIs of PciLib, PciCf8Lib, PciExpressLib, and PciSegmentLib.

2. Update ASSERT condition for PciCf8Lib, and PciSegmentLib class.

3. According to MDE Lib Spec, add check for reserved bit field 63..48 for PCI segment address.


git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8311 6f19259b-4bc3-4df7-8a09-765794883524

1 files changed, 8 insertions, 7 deletions

diff --git a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c
index 6c327e2eb9..332d2a9b45 100644
--- a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c
+++ b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c
@@ -1,7 +1,7 @@
 /** @file

   PCI Segment Library implementation using PCI CFG2 PPI.

 

-  Copyright (c) 2007 - 2008, Intel Corporation All rights

+  Copyright (c) 2007 - 2009, Intel Corporation All rights

   reserved. This program and the accompanying materials are

   licensed and made available under the terms and conditions of

   the BSD License which accompanies this distribution.  The full

@@ -25,14 +25,14 @@
 

 /**

   Assert the validity of a PCI Segment address.

-  A valid PCI Segment address should not contain 1's in bits 31:28

+  A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63

 

   @param  A The address to validate.

   @param  M Additional bits to assert to be zero.

 

 **/

 #define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \

-  ASSERT (((A) & (0xf0000000 | (M))) == 0)

+  ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)

 

 /**

   Translate PCI Lib address into format of PCI CFG2 PPI.

@@ -165,7 +165,7 @@ PeiPciSegmentLibPciCfg2WriteWorker (
   Register a PCI device so PCI configuration registers may be accessed after 

   SetVirtualAddressMap().

   

-  If Address > 0x0FFFFFFF, then ASSERT().

+  If any reserved bits in Address are set, then ASSERT().

 

   @param  Address Address that encodes the PCI Bus, Device, Function and

                   Register.

@@ -185,6 +185,7 @@ PciSegmentRegisterForRuntimeAccess (
   IN UINTN  Address

   )

 {

+  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);

   return RETURN_UNSUPPORTED;

 }

 

@@ -218,7 +219,7 @@ PciSegmentRead8 (
   Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.

   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.

   

-  If Address > 0x0FFFFFFF, then ASSERT().

+  If any reserved bits in Address are set, then ASSERT().

 

   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.

   @param  Value       The value to write.

@@ -1208,7 +1209,7 @@ PciSegmentBitFieldAndThenOr32 (
   and 16-bit PCI configuration read cycles may be used at the beginning and the

   end of the range.

 

-  If StartAddress > 0x0FFFFFFF, then ASSERT().

+  If any reserved bits in StartAddress are set, then ASSERT().

   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().

   If Size > 0 and Buffer is NULL, then ASSERT().

 

@@ -1307,7 +1308,7 @@ PciSegmentReadBuffer (
   8-bit and 16-bit PCI configuration write cycles may be used at the beginning

   and the end of the range.

 

-  If StartAddress > 0x0FFFFFFF, then ASSERT().

+  If any reserved bits in StartAddress are set, then ASSERT().

   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().

   If Size > 0 and Buffer is NULL, then ASSERT().