Add missing PCI class code definition.

PCI22/PCI23/PCI30 spec were reviewed and the missing definitions were added to accordingly Pci22.h/Pci23.h/Pci30.h.
All other class code definitions that are not defined in PCI Local Bus specification but in PCI Code and ID Assignment specification are defined in PciCodeId.h.

Signed-off-by: Ruiyu Ni<ruiyu.ni@intel.com>
Reviewed-by: Liming Gao<liming.gao@intel.com>
Reviewed-by: Hot Tian<hot.tian@intel.com>
Reviewed-by: Elvin Li<elvin.li@intel.com>
Reviewed-by: Feng Tian<feng.tian@intel.com>
Reviewed-by: Jiewen Yao<jiewen.yao@intel.com>

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13919 6f19259b-4bc3-4df7-8a09-765794883524

5 files changed, 172 insertions, 10 deletions

diff --git a/MdePkg/Include/IndustryStandard/Pci.h b/MdePkg/Include/IndustryStandard/Pci.h
index ebaa0f5c2e..32dd543232 100644
--- a/MdePkg/Include/IndustryStandard/Pci.h
+++ b/MdePkg/Include/IndustryStandard/Pci.h
@@ -1,7 +1,7 @@
 /** @file

   Support for the latest PCI standard.

 

-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>

+Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>

 This program and the accompanying materials are licensed and made available under 

 the terms and conditions of the BSD License that accompanies this distribution.  

 The full text of the license may be found at

@@ -20,5 +20,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 

 #include <IndustryStandard/Pci30.h>

 #include <IndustryStandard/PciExpress21.h>

+#include <IndustryStandard/PciCodeId.h>

 

 #endif

diff --git a/MdePkg/Include/IndustryStandard/Pci22.h b/MdePkg/Include/IndustryStandard/Pci22.h
index bf06205bf9..ad4b79d43f 100644
--- a/MdePkg/Include/IndustryStandard/Pci22.h
+++ b/MdePkg/Include/IndustryStandard/Pci22.h
@@ -6,7 +6,7 @@
     PCI-to-PCI Bridge Architecture Specification, Revision 1.2

     PC Card Standard, 8.0

 

-  Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials                          

   are licensed and made available under the terms and conditions of the BSD License         

   which accompanies this distribution.  The full text of the license may be found at        

@@ -219,7 +219,7 @@ typedef struct {
 #define     PCI_IF_16550_MODEM            0x02

 #define     PCI_IF_16650_MODEM            0x03

 #define     PCI_IF_16750_MODEM            0x04

-#define   PCI_SUBCLASS_SCC_OTHER          0x80

+#define   PCI_SUBCLASS_SCC_OTHER        0x80

 

 #define PCI_CLASS_SYSTEM_PERIPHERAL   0x08

 #define   PCI_SUBCLASS_PIC              0x00

@@ -238,7 +238,7 @@ typedef struct {
 #define     PCI_IF_EISA_TIMER             0x02

 #define   PCI_SUBCLASS_RTC              0x03

 #define     PCI_IF_GENERIC_RTC            0x00

-#define     PCI_IF_ISA_RTC                0x00

+#define     PCI_IF_ISA_RTC                0x01

 #define   PCI_SUBCLASS_PNP_CONTROLLER   0x04    ///< HotPlug Controller

 #define   PCI_SUBCLASS_PERIPHERAL_OTHER 0x80

 

@@ -249,10 +249,12 @@ typedef struct {
 #define   PCI_SUBCLASS_SCAN_CONTROLLER  0x03

 #define   PCI_SUBCLASS_GAMEPORT         0x04

 #define     PCI_IF_GAMEPORT               0x00

-#define     PCI_IF_GAMEPORT1              0x01

+#define     PCI_IF_GAMEPORT1              0x10

 #define   PCI_SUBCLASS_INPUT_OTHER      0x80

 

 #define PCI_CLASS_DOCKING_STATION     0x0A

+#define   PCI_SUBCLASS_DOCKING_GENERIC  0x00

+#define   PCI_SUBCLASS_DOCKING_OTHER    0x80

 

 #define PCI_CLASS_PROCESSOR           0x0B

 #define   PCI_SUBCLASS_PROC_386         0x00

@@ -280,7 +282,7 @@ typedef struct {
 #define PCI_CLASS_WIRELESS            0x0D

 #define   PCI_SUBCLASS_IRDA             0x00

 #define   PCI_SUBCLASS_IR               0x01

-#define   PCI_SUBCLASS_RF               0x02

+#define   PCI_SUBCLASS_RF               0x10

 #define   PCI_SUBCLASS_WIRELESS_OTHER   0x80

 

 #define PCI_CLASS_INTELLIGENT_IO      0x0E

diff --git a/MdePkg/Include/IndustryStandard/Pci23.h b/MdePkg/Include/IndustryStandard/Pci23.h
index 5b7d3d44a1..467354429e 100644
--- a/MdePkg/Include/IndustryStandard/Pci23.h
+++ b/MdePkg/Include/IndustryStandard/Pci23.h
@@ -1,7 +1,7 @@
 /** @file

   Support for PCI 2.3 standard.

 

-  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials                          

   are licensed and made available under the terms and conditions of the BSD License         

   which accompanies this distribution.  The full text of the license may be found at        

@@ -27,11 +27,60 @@
 ///@}

 

 ///

+/// PCI_CLASS_NETWORK, Base Class 02h.

+///

+///@{

+#define PCI_CLASS_NETWORK_WORLDFIP              0x05

+#define PCI_CLASS_NETWORK_PICMG_MULTI_COMPUTING 0x06

+///@}

+

+///

+/// PCI_CLASS_BRIDGE, Base Class 06h.

+///

+///@{

+#define PCI_CLASS_BRIDGE_SEMI_TRANSPARENT_P2P        0x09

+#define   PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_PRIMARY   0x40

+#define   PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_SECONDARY 0x80

+#define PCI_CLASS_BRIDGE_INFINIBAND_TO_PCI           0x0A

+///@}

+

+///

+/// PCI_CLASS_SCC, Base Class 07h.

+///

+///@{

+#define PCI_SUBCLASS_GPIB          0x04

+#define PCI_SUBCLASS_SMART_CARD    0x05

+///@}

+

+///

 /// PCI_CLASS_SERIAL, Base Class 0Ch.

 ///

 ///@{

 #define   PCI_IF_EHCI                      0x20

 #define PCI_CLASS_SERIAL_IB              0x06

+#define PCI_CLASS_SERIAL_IPMI            0x07

+#define   PCI_IF_IPMI_SMIC                 0x00

+#define   PCI_IF_IPMI_KCS                  0x01 ///< Keyboard Controller Style

+#define   PCI_IF_IPMI_BT                   0x02 ///< Block Transfer

+#define PCI_CLASS_SERIAL_SERCOS          0x08

+#define PCI_CLASS_SERIAL_CANBUS          0x09

+///@}

+

+///

+/// PCI_CLASS_WIRELESS, Base Class 0Dh.

+///

+///@{

+#define PCI_SUBCLASS_BLUETOOTH    0x11

+#define PCI_SUBCLASS_BROADBAND    0x12

+///@}

+

+///

+/// PCI_CLASS_DPIO, Base Class 11h.

+///

+///@{

+#define PCI_SUBCLASS_PERFORMANCE_COUNTERS          0x01

+#define PCI_SUBCLASS_COMMUNICATION_SYNCHRONIZATION 0x10

+#define PCI_SUBCLASS_MANAGEMENT_CARD               0x20

 ///@}

 

 ///

diff --git a/MdePkg/Include/IndustryStandard/Pci30.h b/MdePkg/Include/IndustryStandard/Pci30.h
index 4c71385a18..a4ab909eb5 100644
--- a/MdePkg/Include/IndustryStandard/Pci30.h
+++ b/MdePkg/Include/IndustryStandard/Pci30.h
@@ -1,7 +1,7 @@
 /** @file

   Support for PCI 3.0 standard.

 

-  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials                          

   are licensed and made available under the terms and conditions of the BSD License         

   which accompanies this distribution.  The full text of the license may be found at        

@@ -19,13 +19,23 @@
 #include <IndustryStandard/Pci23.h>

 

 ///

-/// Definitions of PCI class bytes and manipulation macros.

+/// PCI_CLASS_MASS_STORAGE, Base Class 01h.

 ///

+///@{

 #define PCI_CLASS_MASS_STORAGE_SATADPA   0x06

 #define   PCI_IF_MASS_STORAGE_SATA         0x00

 #define   PCI_IF_MASS_STORAGE_AHCI         0x01

+///@}

 

-/**  

+///

+/// PCI_CLASS_WIRELESS, Base Class 0Dh.

+///

+///@{

+#define PCI_SUBCLASS_ETHERNET_80211A    0x20

+#define PCI_SUBCLASS_ETHERNET_80211B    0x21

+///@}

+

+/**

   Macro that checks whether device is a SATA controller.

 

   @param  _p      Specified device.

diff --git a/MdePkg/Include/IndustryStandard/PciCodeId.h b/MdePkg/Include/IndustryStandard/PciCodeId.h
new file mode 100644
index 0000000000..dba98565ba
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/PciCodeId.h
@@ -0,0 +1,100 @@
+/** @file

+  The file lists the PCI class codes only defined in PCI code and ID assignment specification

+  revision 1.3.

+

+  Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>

+  This program and the accompanying materials                          

+  are licensed and made available under the terms and conditions of the BSD License         

+  which accompanies this distribution.  The full text of the license may be found at        

+  http://opensource.org/licenses/bsd-license.php                                            

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             

+

+**/

+

+#ifndef __PCI_CODE_ID_H__

+#define __PCI_CODE_ID_H__

+

+

+///

+/// PCI_CLASS_MASS_STORAGE, Base Class 01h.

+///

+///@{

+#define   PCI_IF_MASS_STORAGE_SCSI_VENDOR_SPECIFIC          0x00

+#define   PCI_IF_MASS_STORAGE_SCSI_DEVICE_PQI               0x11

+#define   PCI_IF_MASS_STORAGE_SCSI_CONTROLLER_PQI           0x12

+#define   PCI_IF_MASS_STORAGE_SCSI_DEVICE_CONTROLLER_PQI    0x13

+#define   PCI_IF_MASS_STORAGE_SCSI_DEVICE_NVM_EXPRESS       0x21

+#define   PCI_IF_MASS_STORAGE_SATA_SERIAL_BUS               0x02

+#define PCI_CLASS_MASS_STORAGE_SAS                        0x07

+#define   PCI_IF_MASS_STORAGE_SAS                           0x00

+#define   PCI_IF_MASS_STORAGE_SAS_SERIAL_BUS                0x01

+#define PCI_CLASS_MASS_STORAGE_SOLID_STATE                0x08

+#define   PCI_IF_MASS_STORAGE_SOLID_STATE                   0x00

+#define   PCI_IF_MASS_STORAGE_SOLID_STATE_NVMHCI            0x01

+#define   PCI_IF_MASS_STORAGE_SOLID_STATE_ENTERPRISE_NVMHCI 0x02

+///@}

+

+///

+/// PCI_CLASS_NETWORK, Base Class 02h.

+///

+///@{

+#define PCI_CLASS_NETWORK_INFINIBAND   0x07

+///@}

+

+///

+/// PCI_CLASS_MEDIA, Base Class 04h.

+///

+///@{

+#define PCI_CLASS_MEDIA_MIXED_MODE   0x03

+///@}

+

+///

+/// PCI_CLASS_BRIDGE, Base Class 06h.

+///

+///@{

+#define PCI_CLASS_BRIDGE_ADVANCED_SWITCHING_TO_PCI      0x0B

+#define   PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_CUSTOM  0x00

+#define   PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_ASI_SIG 0x01

+///@}

+

+///

+/// PCI_CLASS_SYSTEM_PERIPHERAL, Base Class 08h.

+///

+///@{

+#define   PCI_IF_HPET                 0x03

+#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05

+#define PCI_SUBCLASS_IOMMU              0x06

+///@}

+

+///

+/// PCI_CLASS_PROCESSOR, Base Class 0Bh.

+///

+///@{

+#define PCI_SUBCLASS_PROC_OTHER 0x80

+///@}

+

+///

+/// PCI_CLASS_SERIAL, Base Class 0Ch.

+///

+///@{

+#define   PCI_IF_XHCI             0x30

+#define PCI_CLASS_SERIAL_OTHER  0x80

+///@}

+

+///

+/// PCI_CLASS_SATELLITE, Base Class 0Fh.

+///

+///@{

+#define PCI_SUBCLASS_SATELLITE_OTHER 0x80

+///@}

+

+///

+/// PCI_CLASS_PROCESSING_ACCELERATOR, Base Class 12h.

+///

+///@{

+#define PCI_CLASS_PROCESSING_ACCELERATOR  0x12

+///@}

+

+#endif