This check-in fixed the following bugs:

1.	Pci22.h EFI_LEGACY_EXPANSION_ROM_HEADER definition error
(MdePkg\Include\IndustryStandard\Pci22.h; Tools\CCode\Source\Include\IndustryStandard\Pci22.h)
2.	SetVariable() with DataSize=0xffffffff will cause system hang
(EdkModulePkg\Universal\Variable\RuntimeDxe\Variable.c)
3.	Windows XP Pro & XP HOME Fails to Install from Retail CD
(EdkModulePkg\Bus\Pci\Pcibus\Dxe\PciResourceSupport.c)
4.	Pci22.h header file needs to add some recent type
(MdePkg\Include\IndustryStandard\Pci22.h; Tools\CCode\Source\Include\IndustryStandard\Pci22.h)
5.	Fix issues when ODD cannot boot from Sil0680 PCI-IDE controller
(EdkModulePkg\Bus\Pci\PciBus\Dxe\PciOptionromSupport.c;
EdkModulePkg\Bus\Pci\PciBus\Dxe\PciBus.msa;
EdkModulePkg\ EdkModulePkg.spd)


git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@1900 6f19259b-4bc3-4df7-8a09-765794883524

1 files changed, 111 insertions, 3 deletions

diff --git a/MdePkg/Include/IndustryStandard/pci22.h b/MdePkg/Include/IndustryStandard/pci22.h
index 7fee279e80..b9098307a4 100644
--- a/MdePkg/Include/IndustryStandard/pci22.h
+++ b/MdePkg/Include/IndustryStandard/pci22.h
@@ -168,6 +168,65 @@ typedef struct {
 #define PCI_CLASS_BRIDGE_RACEWAY      0x08

 #define PCI_CLASS_BRIDGE_ISA_PDECODE  0x80

 #define PCI_CLASS_ISA_POSITIVE_DECODE 0x80  // obsolete

+

+#define PCI_CLASS_SCC                 0x07  // Simple communications controllers 

+#define PCI_SUBCLASS_SERIAL           0x00

+#define PCI_IF_GENERIC_XT             0x00

+#define PCI_IF_16450                  0x01

+#define PCI_IF_16550                  0x02

+#define PCI_IF_16650                  0x03

+#define PCI_IF_16750                  0x04

+#define PCI_IF_16850                  0x05

+#define PCI_IF_16950                  0x06

+#define PCI_SUBCLASS_PARALLEL         0x01

+#define PCI_IF_PARALLEL_PORT          0x00

+#define PCI_IF_BI_DIR_PARALLEL_PORT   0x01

+#define PCI_IF_ECP_PARALLEL_PORT      0x02

+#define PCI_IF_1284_CONTROLLER        0x03

+#define PCI_IF_1284_DEVICE            0xFE

+#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02

+#define PCI_SUBCLASS_MODEM            0x03

+#define PCI_IF_GENERIC_MODEM          0x00

+#define PCI_IF_16450_MODEM            0x01

+#define PCI_IF_16550_MODEM            0x02

+#define PCI_IF_16650_MODEM            0x03

+#define PCI_IF_16750_MODEM            0x04

+#define PCI_SUBCLASS_OTHER            0x80

+

+#define PCI_CLASS_SYSTEM_PERIPHERAL   0x08

+#define PCI_SUBCLASS_PIC              0x00

+#define PCI_IF_8259_PIC               0x00

+#define PCI_IF_ISA_PIC                0x01

+#define PCI_IF_EISA_PIC               0x02

+#define PCI_IF_APIC_CONTROLLER        0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory.  

+#define PCI_IF_APIC_CONTROLLER2       0x20 

+#define PCI_SUBCLASS_TIMER            0x02

+#define PCI_IF_8254_TIMER             0x00

+#define PCI_IF_ISA_TIMER              0x01

+#define PCI_EISA_TIMER                0x02

+#define PCI_SUBCLASS_RTC              0x03

+#define PCI_IF_GENERIC_RTC            0x00

+#define PCI_IF_ISA_RTC                0x00

+#define PCI_SUBCLASS_PNP_CONTROLLER   0x04 // HotPlug Controller

+

+#define PCI_CLASS_INPUT_DEVICE        0x09

+#define PCI_SUBCLASS_KEYBOARD         0x00

+#define PCI_SUBCLASS_PEN              0x01

+#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02

+#define PCI_SUBCLASS_SCAN_CONTROLLER  0x03

+#define PCI_SUBCLASS_GAMEPORT         0x04

+

+#define PCI_CLASS_DOCKING_STATION     0x0A

+

+#define PCI_CLASS_PROCESSOR           0x0B

+#define PCI_SUBCLASS_PROC_386         0x00

+#define PCI_SUBCLASS_PROC_486         0x01

+#define PCI_SUBCLASS_PROC_PENTIUM     0x02

+#define PCI_SUBCLASS_PROC_ALPHA       0x10

+#define PCI_SUBCLASS_PROC_POWERPC     0x20

+#define PCI_SUBCLASS_PROC_MIPS        0x30

+#define PCI_SUBCLASS_PROC_CO_PORC     0x40 // Co-Processor

+

 #define PCI_CLASS_SERIAL              0x0C

 #define PCI_CLASS_SERIAL_FIREWIRE     0x00

 #define PCI_CLASS_SERIAL_ACCESS_BUS   0x01

@@ -176,6 +235,25 @@ typedef struct {
 #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04

 #define PCI_CLASS_SERIAL_SMB          0x05

 

+#define PCI_CLASS_WIRELESS            0x0D

+#define PCI_SUBCLASS_IRDA             0x00

+#define PCI_SUBCLASS_IR               0x01

+#define PCI_SUBCLASS_RF               0x02

+

+#define PCI_CLASS_INTELLIGENT_IO      0x0E

+

+#define PCI_CLASS_SATELLITE           0x0F

+#define PCI_SUBCLASS_TV               0x01

+#define PCI_SUBCLASS_AUDIO            0x02

+#define PCI_SUBCLASS_VOICE            0x03

+#define PCI_SUBCLASS_DATA             0x04

+

+#define PCI_SECURITY_CONTROLLER       0x10 // Encryption and decryption controller

+#define PCI_SUBCLASS_NET_COMPUT       0x00

+#define PCI_SUBCLASS_ENTERTAINMENT    0x10 

+

+#define PCI_CLASS_DPIO                0x11

+

 #define IS_CLASS1(_p, c)              ((_p)->Hdr.ClassCode[2] == (c))

 #define IS_CLASS2(_p, c, s)           (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))

 #define IS_CLASS3(_p, c, s, p)        (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))

@@ -208,8 +286,8 @@ typedef struct {
 #define PCI_DEVICE_ROMBAR             0x30

 #define PCI_BRIDGE_ROMBAR             0x38

 

-#define PCI_MAX_BAR                   6

-#define PCI_MAX_CONFIG_OFFSET         0x100

+#define PCI_MAX_BAR                   0x0006

+#define PCI_MAX_CONFIG_OFFSET         0x0100

 //

 // bugbug: this is supported in PCI spec v2.3

 //

@@ -225,6 +303,18 @@ typedef struct {
 #define PCI_LATENCY_TIMER_OFFSET                    0x0D

 #define PCI_HEADER_TYPE_OFFSET                      0x0E

 #define PCI_BIST_OFFSET                             0x0F

+#define PCI_BASE_ADDRESSREG_OFFSET                  0x10

+#define PCI_CARDBUS_CIS_OFFSET                      0x28

+#define PCI_SVID_OFFSET                             0x2C // SubSystem Vendor id

+#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET              0x2C

+#define PCI_SID_OFFSET                              0x2E // SubSystem ID

+#define PCI_SUBSYSTEM_ID_OFFSET                     0x2E

+#define PCI_EXPANSION_ROM_BASE                      0x30

+#define PCI_CAPBILITY_POINTER_OFFSET                0x34

+#define PCI_INT_LINE_OFFSET                         0x3C // Interrupt Line Register

+#define PCI_INT_PIN_OFFSET                          0x3D // Interrupt Pin Register

+#define PCI_MAXGNT_OFFSET                           0x3E // Max Grant Register

+#define PCI_MAXLAT_OFFSET                           0x3F // Max Latency Register

 

 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E

 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E

@@ -328,7 +418,8 @@ typedef struct {
 typedef struct {

   UINT16  Signature;    // 0xaa55

   UINT8   Size512;

-  UINT8   Reserved[15];

+  UINT8   InitEntryPoint[3];

+  UINT8   Reserved[0x12];

   UINT16  PcirOffset;

 } EFI_LEGACY_EXPANSION_ROM_HEADER;

 

@@ -354,6 +445,23 @@ typedef struct {
   UINT16  Reserved1;

 } PCI_DATA_STRUCTURE;

 

+typedef struct {

+  UINT32  Signature;    // "PCIR"

+  UINT16  VendorId;

+  UINT16  DeviceId;

+  UINT16  DeviceListOffset;

+  UINT16  Length;

+  UINT8   Revision;

+  UINT8   ClassCode[3];

+  UINT16  ImageLength;

+  UINT16  CodeRevision;

+  UINT8   CodeType;

+  UINT8   Indicator;

+  UINT16  MaxRuntimeImageLength;

+  UINT16  ConfigUtilityCodeHeaderOffset;

+  UINT16  DMTFCLPEntryPointOffset;

+} PCI_3_0_DATA_STRUCTURE;

+

 //

 // PCI Capability List IDs and records

 //