Moving OMAP 3530 code out of BeagleBoard package into its own package

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9854 6f19259b-4bc3-4df7-8a09-765794883524

1 files changed, 164 insertions, 0 deletions

diff --git a/Omap35xxPkg/Include/Omap3530/Omap3530Prcm.h b/Omap35xxPkg/Include/Omap3530/Omap3530Prcm.h
new file mode 100644
index 0000000000..036f8bcece
--- /dev/null
+++ b/Omap35xxPkg/Include/Omap3530/Omap3530Prcm.h
@@ -0,0 +1,164 @@
+/** @file
+
+  Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
+
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __OMAP3530PRCM_H__
+#define __OMAP3530PRCM_H__
+
+#define CM_FCLKEN1_CORE   (0x48004A00)
+#define CM_FCLKEN3_CORE   (0x48004A08)
+#define CM_ICLKEN1_CORE   (0x48004A10)
+#define CM_ICLKEN3_CORE   (0x48004A18)
+#define CM_CLKEN2_PLL     (0x48004D04)
+#define CM_CLKSEL4_PLL    (0x48004D4C)
+#define CM_CLKSEL5_PLL    (0x48004D50)
+#define CM_FCLKEN_USBHOST (0x48005400)
+#define CM_ICLKEN_USBHOST (0x48005410)
+
+//Wakeup clock defintion
+#define CM_FCLKEN_WKUP    (0x48004C00)
+#define CM_ICLKEN_WKUP    (0x48004C10)
+
+//Peripheral clock definition
+#define CM_FCLKEN_PER     (0x48005000)
+#define CM_ICLKEN_PER     (0x48005010)
+#define CM_CLKSEL_PER     (0x48005040)
+
+//Reset management definition
+#define PRM_RSTCTRL       (0x48307250)
+#define PRM_RSTST         (0x48307258)
+
+//CORE clock
+#define CM_FCLKEN1_CORE_EN_I2C1_MASK    (1UL << 15)
+#define CM_FCLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
+#define CM_FCLKEN1_CORE_EN_I2C1_ENABLE  (1UL << 15)
+
+#define CM_ICLKEN1_CORE_EN_I2C1_MASK    (1UL << 15)
+#define CM_ICLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
+#define CM_ICLKEN1_CORE_EN_I2C1_ENABLE  (1UL << 15)
+
+#define CM_FCLKEN1_CORE_EN_MMC1_MASK    (1UL << 24)
+#define CM_FCLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
+#define CM_FCLKEN1_CORE_EN_MMC1_ENABLE  (1UL << 24)
+
+#define CM_FCLKEN3_CORE_EN_USBTLL_MASK    (1UL << 2)
+#define CM_FCLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
+#define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE  (1UL << 2)
+
+#define CM_ICLKEN1_CORE_EN_MMC1_MASK    (1UL << 24)
+#define CM_ICLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
+#define CM_ICLKEN1_CORE_EN_MMC1_ENABLE  (1UL << 24)
+
+#define CM_ICLKEN3_CORE_EN_USBTLL_MASK    (1UL << 2)
+#define CM_ICLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
+#define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE  (1UL << 2)
+
+#define CM_CLKEN_FREQSEL_075_100        (0x03UL << 4)
+#define CM_CLKEN_ENABLE                 (7UL << 0)
+
+#define CM_CLKSEL_PLL_MULT(x)           (((x) & 0x07FF) << 8)
+#define CM_CLKSEL_PLL_DIV(x)            ((((x) - 1) & 0x7F) << 0)
+  
+#define CM_CLKSEL_DIV_120M(x)           (((x) & 0x1F) << 0)
+
+#define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK    (1UL << 1)
+#define CM_FCLKEN_USBHOST_EN_USBHOST2_DISABLE (0UL << 1)
+#define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE  (1UL << 1)
+
+#define CM_FCLKEN_USBHOST_EN_USBHOST1_MASK    (1UL << 0)
+#define CM_FCLKEN_USBHOST_EN_USBHOST1_DISABLE (0UL << 0)
+#define CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE  (1UL << 0)
+
+#define CM_ICLKEN_USBHOST_EN_USBHOST_MASK     (1UL << 0)
+#define CM_ICLKEN_USBHOST_EN_USBHOST_DISABLE  (0UL << 0)
+#define CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE   (1UL << 0)
+
+//Wakeup functional clock
+#define CM_FCLKEN_WKUP_EN_GPIO1_DISABLE       (0UL << 3)
+#define CM_FCLKEN_WKUP_EN_GPIO1_ENABLE        (1UL << 3)
+
+#define CM_FCLKEN_WKUP_EN_WDT2_DISABLE        (0UL << 5)
+#define CM_FCLKEN_WKUP_EN_WDT2_ENABLE         (1UL << 5)
+
+//Wakeup interface clock
+#define CM_ICLKEN_WKUP_EN_GPIO1_DISABLE       (0UL << 3)
+#define CM_ICLKEN_WKUP_EN_GPIO1_ENABLE        (1UL << 3)
+
+#define CM_ICLKEN_WKUP_EN_WDT2_DISABLE        (0UL << 5)
+#define CM_ICLKEN_WKUP_EN_WDT2_ENABLE         (1UL << 5)
+
+//Peripheral functional clock
+#define CM_FCLKEN_PER_EN_GPT3_DISABLE         (0UL << 4)
+#define CM_FCLKEN_PER_EN_GPT3_ENABLE          (1UL << 4)
+
+#define CM_FCLKEN_PER_EN_GPT4_DISABLE         (0UL << 5)
+#define CM_FCLKEN_PER_EN_GPT4_ENABLE          (1UL << 5)
+
+#define CM_FCLKEN_PER_EN_UART3_DISABLE        (0UL << 11)
+#define CM_FCLKEN_PER_EN_UART3_ENABLE         (1UL << 11)
+
+#define CM_FCLKEN_PER_EN_GPIO2_DISABLE        (0UL << 13)
+#define CM_FCLKEN_PER_EN_GPIO2_ENABLE         (1UL << 13)
+
+#define CM_FCLKEN_PER_EN_GPIO3_DISABLE        (0UL << 14)
+#define CM_FCLKEN_PER_EN_GPIO3_ENABLE         (1UL << 14)
+
+#define CM_FCLKEN_PER_EN_GPIO4_DISABLE        (0UL << 15)
+#define CM_FCLKEN_PER_EN_GPIO4_ENABLE         (1UL << 15)
+
+#define CM_FCLKEN_PER_EN_GPIO5_DISABLE        (0UL << 16)
+#define CM_FCLKEN_PER_EN_GPIO5_ENABLE         (1UL << 16)
+
+#define CM_FCLKEN_PER_EN_GPIO6_DISABLE        (0UL << 17)
+#define CM_FCLKEN_PER_EN_GPIO6_ENABLE         (1UL << 17)
+
+//Peripheral interface clock
+#define CM_ICLKEN_PER_EN_GPT3_DISABLE         (0UL << 4)
+#define CM_ICLKEN_PER_EN_GPT3_ENABLE          (1UL << 4)
+
+#define CM_ICLKEN_PER_EN_GPT4_DISABLE         (0UL << 5)
+#define CM_ICLKEN_PER_EN_GPT4_ENABLE          (1UL << 5)
+
+#define CM_ICLKEN_PER_EN_UART3_DISABLE        (0UL << 11)
+#define CM_ICLKEN_PER_EN_UART3_ENABLE         (1UL << 11)
+
+#define CM_ICLKEN_PER_EN_GPIO2_DISABLE        (0UL << 13)
+#define CM_ICLKEN_PER_EN_GPIO2_ENABLE         (1UL << 13)
+
+#define CM_ICLKEN_PER_EN_GPIO3_DISABLE        (0UL << 14)
+#define CM_ICLKEN_PER_EN_GPIO3_ENABLE         (1UL << 14)
+
+#define CM_ICLKEN_PER_EN_GPIO4_DISABLE        (0UL << 15)
+#define CM_ICLKEN_PER_EN_GPIO4_ENABLE         (1UL << 15)
+
+#define CM_ICLKEN_PER_EN_GPIO5_DISABLE        (0UL << 16)
+#define CM_ICLKEN_PER_EN_GPIO5_ENABLE         (1UL << 16)
+
+#define CM_ICLKEN_PER_EN_GPIO6_DISABLE        (0UL << 17)
+#define CM_ICLKEN_PER_EN_GPIO6_ENABLE         (1UL << 17)
+
+//Timer source clock selection
+#define CM_CLKSEL_PER_CLKSEL_GPT3_32K         (0UL << 1)
+#define CM_CLKSEL_PER_CLKSEL_GPT3_SYS         (1UL << 1)
+
+#define CM_CLKSEL_PER_CLKSEL_GPT4_32K         (0UL << 2)
+#define CM_CLKSEL_PER_CLKSEL_GPT4_SYS         (1UL << 2)
+
+//Reset management (Global and Cold reset)
+#define RST_GS            (0x1UL << 1)
+#define RST_DPLL3         (0x1UL << 2)
+#define GLOBAL_SW_RST     (0x1UL << 1)
+#define GLOBAL_COLD_RST   (0x0UL << 0)
+
+#endif // __OMAP3530PRCM_H__
+