OvmfPkg: IndustryStandard/Q35MchIch9.h: add PCIEXBAR macros

Section 5.1.16 ("PCIEXBAR -- PCI Express Register Range Base Address") in
Intel document #316966-002 (already referenced near the top of this header
file) describes the Q35 DRAM Controller register that configures the
memory-mapped PCI config space (also known as MMCONFIG, and ECAM /
Enhanced Configuration Access Method).

In this patch we add the macros we'll need later. We'll only support the
256 MB memory-mapped config space -- enough for buses [0, 255].

Cc: Gabriel Somlo <somlo@cmu.edu>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Marcel Apfelbaum <marcel@redhat.com>
Cc: Michał Zegan <webczat_200@poczta.onet.pl>
Ref: https://github.com/tianocore/edk2/issues/32
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Gabriel Somlo <somlo@cmu.edu>
Tested-by: Michał Zegan <webczat_200@poczta.onet.pl>

1 files changed, 8 insertions, 0 deletions

diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
index 18b34a3d4f..4dc2c39901 100644
--- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
+++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
@@ -33,6 +33,14 @@
 #define MCH_GGC               0x52

 #define MCH_GGC_IVD             BIT1

 

+#define MCH_PCIEXBAR_LOW      0x60

+#define MCH_PCIEXBAR_LOWMASK    0x0FFFFFFF

+#define MCH_PCIEXBAR_BUS_FF     0

+#define MCH_PCIEXBAR_EN         BIT0

+

+#define MCH_PCIEXBAR_HIGH     0x64

+#define MCH_PCIEXBAR_HIGHMASK   0xFFFFFFF0

+

 #define MCH_SMRAM             0x9D

 #define MCH_SMRAM_D_LCK         BIT4

 #define MCH_SMRAM_G_SMRAME      BIT3