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| author | Gabriel Somlo <somlo@cmu.edu> | 2014-09-09 03:18:30 +0000 |
|---|---|---|
| committer | jljusten <jljusten@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-09-09 03:18:30 +0000 |
| commit | 41f80fbd9905cdc9a457e3cdf8110539f948c6b9 (patch) | |
| tree | 9e9afb0e163e17be01b86bc9e7630fdce39266fd /OvmfPkg/Library/AcpiTimerLib | |
| parent | 769e45317c60b07abe083d7da72ccfd69ad49d60 (diff) | |
| download | edk2-platforms-41f80fbd9905cdc9a457e3cdf8110539f948c6b9.tar.xz | |
OvmfPkg: AcpiTimerLib: Access power mgmt regs based on host bridge type
Pick the appropriate bus:dev.fn for accessing ACPI power management
registers (00:01.3 on PIIX4 vs. 00:1f.0 on Q35) based on the device
ID of the host bridge (assumed always present at 00:00.0).
With this patch, OVMF can boot QEMU's "-machine q35" x86 machine type.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gabriel Somlo <somlo@cmu.edu>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16066 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'OvmfPkg/Library/AcpiTimerLib')
| -rw-r--r-- | OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.c | 71 |
1 files changed, 63 insertions, 8 deletions
diff --git a/OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.c index c6441281b4..7d324cb815 100644 --- a/OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.c @@ -43,20 +43,75 @@ )
//
-// PIIX4 Power Management PCI Configuration Registers
+// PCI Location of Q35 Power Management PCI Configuration Registers
//
-#define PMBA PIIX4_PCI_POWER_MANAGEMENT_REGISTER (0x40)
+#define Q35_POWER_MANAGEMENT_BUS 0x00
+#define Q35_POWER_MANAGEMENT_DEVICE 0x1f
+#define Q35_POWER_MANAGEMENT_FUNCTION 0x00
+
+//
+// Macro to access Q35 Power Management PCI Configuration Registers
+//
+#define Q35_PCI_POWER_MANAGEMENT_REGISTER(Register) \
+ PCI_LIB_ADDRESS ( \
+ Q35_POWER_MANAGEMENT_BUS, \
+ Q35_POWER_MANAGEMENT_DEVICE, \
+ Q35_POWER_MANAGEMENT_FUNCTION, \
+ Register \
+ )
+
+//
+// PCI Location of Host Bridge PCI Configuration Registers
+//
+#define HOST_BRIDGE_BUS 0x00
+#define HOST_BRIDGE_DEVICE 0x00
+#define HOST_BRIDGE_FUNCTION 0x00
+
+//
+// Macro to access Host Bridge Configuration Registers
+//
+#define HOST_BRIDGE_REGISTER(Register) \
+ PCI_LIB_ADDRESS ( \
+ HOST_BRIDGE_BUS, \
+ HOST_BRIDGE_DEVICE, \
+ HOST_BRIDGE_FUNCTION, \
+ Register \
+ )
+
+//
+// Host Bridge Device ID (DID) Register
+//
+#define HOST_BRIDGE_DID HOST_BRIDGE_REGISTER (0x02)
+
+//
+// Host Bridge DID Register values
+//
+#define PCI_DEVICE_ID_INTEL_82441 0x1237 // DID value for PIIX4
+#define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29C0 // DID value for Q35
+
+//
+// Access Power Management PCI Config Regs based on Host Bridge type
+//
+#define PCI_POWER_MANAGEMENT_REGISTER(Register) \
+ ((PciRead16 (HOST_BRIDGE_DID) == PCI_DEVICE_ID_INTEL_Q35_MCH) ? \
+ Q35_PCI_POWER_MANAGEMENT_REGISTER (Register) : \
+ PIIX4_PCI_POWER_MANAGEMENT_REGISTER (Register))
+
+//
+// Power Management PCI Configuration Registers
+//
+#define PMBA PCI_POWER_MANAGEMENT_REGISTER (0x40)
#define PMBA_RTE BIT0
-#define PMREGMISC PIIX4_PCI_POWER_MANAGEMENT_REGISTER (0x80)
+#define PMREGMISC PCI_POWER_MANAGEMENT_REGISTER (0x80)
#define PMIOSE BIT0
//
-// The ACPI Time in the PIIX4 is a 24-bit counter
+// The ACPI Time is a 24-bit counter
//
#define ACPI_TIMER_COUNT_SIZE BIT24
//
-// Offset in the PIIX4 Power Management Base Address to the ACPI Timer
+// Offset in the Power Management Base Address to the ACPI Timer
//
#define ACPI_TIMER_OFFSET 0x8
@@ -76,12 +131,12 @@ AcpiTimerLibConstructor ( )
{
//
- // Check to see if the PIIX4 Power Management Base Address is already enabled
+ // Check to see if the Power Management Base Address is already enabled
//
if ((PciRead8 (PMREGMISC) & PMIOSE) == 0) {
//
- // If the PIIX4 Power Management Base Address is not programmed,
- // then program the PIIX4 Power Management Base Address from a PCD.
+ // If the Power Management Base Address is not programmed,
+ // then program the Power Management Base Address from a PCD.
//
PciAndThenOr32 (PMBA, (UINT32)(~0x0000FFC0), PcdGet16 (PcdAcpiPmBaseAddress));
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