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authorLaszlo Ersek <lersek@redhat.com>2015-05-13 09:31:44 +0000
committerlersek <lersek@Edk2>2015-05-13 09:31:44 +0000
commitbc9d05d6f2ba3267cbf2f339cecd59d2ebae4ffb (patch)
treeccdf4c3c0cf4150a403e923d67194e0be0f55519 /OvmfPkg/Library
parent6b225ace4b5b935f11eab11edd62ff13be66aa1a (diff)
downloadedk2-platforms-bc9d05d6f2ba3267cbf2f339cecd59d2ebae4ffb.tar.xz
OvmfPkg: consolidate POWER_MGMT_REGISTER_Q35() on "Q35MchIch9.h" macros
All POWER_MGMT_REGISTER_Q35() macro invocations in OvmfPkg should use the macros in "Q35MchIch9.h" as arguments. Cc: Gabriel Somlo <somlo@cmu.edu> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Acked-by: Gabriel Somlo <somlo@cmu.edu> Tested-by: Gabriel Somlo <somlo@cmu.edu> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17434 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'OvmfPkg/Library')
-rw-r--r--OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c7
-rw-r--r--OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c9
-rw-r--r--OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c2
-rw-r--r--OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c2
4 files changed, 9 insertions, 11 deletions
diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
index 58938b5d8b..c20f299304 100644
--- a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
@@ -23,7 +23,6 @@
//
#define PMBA_RTE BIT0
#define PIIX4_PMIOSE BIT0
-#define Q35_ACPI_EN BIT7
//
// Offset in the Power Management Base Address to the ACPI Timer
@@ -64,9 +63,9 @@ AcpiTimerLibConstructor (
AcpiEnBit = PIIX4_PMIOSE;
break;
case INTEL_Q35_MCH_DEVICE_ID:
- Pmba = POWER_MGMT_REGISTER_Q35 (0x40);
- AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (0x44); // ACPI_CNTL
- AcpiEnBit = Q35_ACPI_EN;
+ Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
+ AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
+ AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;
break;
default:
DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
index c9601d8e97..55f3572eef 100644
--- a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
@@ -24,7 +24,6 @@
//
#define PMBA_RTE BIT0
#define PIIX4_PMIOSE BIT0
-#define Q35_ACPI_EN BIT7
//
// Offset in the Power Management Base Address to the ACPI Timer
@@ -62,9 +61,9 @@ AcpiTimerLibConstructor (
AcpiEnBit = PIIX4_PMIOSE;
break;
case INTEL_Q35_MCH_DEVICE_ID:
- Pmba = POWER_MGMT_REGISTER_Q35 (0x40);
- AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (0x44); // ACPI_CNTL
- AcpiEnBit = Q35_ACPI_EN;
+ Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
+ AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
+ AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;
break;
default:
DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
@@ -118,7 +117,7 @@ InternalAcpiGetTimerTick (
Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
break;
case INTEL_Q35_MCH_DEVICE_ID:
- Pmba = POWER_MGMT_REGISTER_Q35 (0x40);
+ Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
break;
default:
DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
diff --git a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c
index 2be0793057..649b5c9a4d 100644
--- a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c
@@ -64,7 +64,7 @@ AcpiTimerLibConstructor (
Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
break;
case INTEL_Q35_MCH_DEVICE_ID:
- Pmba = POWER_MGMT_REGISTER_Q35 (0x40);
+ Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
break;
default:
DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
diff --git a/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c b/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c
index 1e87820e93..2521ea4e6a 100644
--- a/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c
+++ b/OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c
@@ -870,7 +870,7 @@ PciAcpiInitialization (
PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x63), 0x0a); // D
break;
case INTEL_Q35_MCH_DEVICE_ID:
- Pmba = POWER_MGMT_REGISTER_Q35 (0x40);
+ Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
//
// 00:1f.0 LPC Bridge (Q35) LNK routing targets
//