diff options
| author | jljusten <jljusten@6f19259b-4bc3-4df7-8a09-765794883524> | 2010-06-19 06:08:07 +0000 |
|---|---|---|
| committer | jljusten <jljusten@6f19259b-4bc3-4df7-8a09-765794883524> | 2010-06-19 06:08:07 +0000 |
| commit | daaad2703d654a6452a0de60eaf319b020af386c (patch) | |
| tree | fb7776d4a1500ff703bd20d501d8262930fe52c5 /PcAtChipsetPkg | |
| parent | cac2ab9556d7cb0d658098a9df0b657d862a55d5 (diff) | |
| download | edk2-platforms-daaad2703d654a6452a0de60eaf319b020af386c.tar.xz | |
PcAtChipsetPkg PciHostBridgeDxe: Fix build warning with GCC
Add default case to switch blocks to remove GCC compiler warning.
The default case code path should never be taken.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10592 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'PcAtChipsetPkg')
| -rw-r--r-- | PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c b/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c index edbe4a03b2..a33836569b 100644 --- a/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c @@ -914,6 +914,13 @@ RootBridgeIoMemRW ( case EfiPciWidthUint64:
MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
break;
+ default:
+ //
+ // The RootBridgeIoCheckParameter call above will ensure that this
+ // path is not taken.
+ //
+ ASSERT (FALSE);
+ break;
}
} else {
switch (OperationWidth) {
@@ -929,6 +936,13 @@ RootBridgeIoMemRW ( case EfiPciWidthUint64:
*((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
break;
+ default:
+ //
+ // The RootBridgeIoCheckParameter call above will ensure that this
+ // path is not taken.
+ //
+ ASSERT (FALSE);
+ break;
}
}
}
@@ -989,6 +1003,13 @@ RootBridgeIoIoRW ( case EfiPciWidthUint32:
IoWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
break;
+ default:
+ //
+ // The RootBridgeIoCheckParameter call above will ensure that this
+ // path is not taken.
+ //
+ ASSERT (FALSE);
+ break;
}
} else {
switch (OperationWidth) {
@@ -1001,6 +1022,13 @@ RootBridgeIoIoRW ( case EfiPciWidthUint32:
*((UINT32 *)Uint8Buffer) = IoRead32 ((UINTN)Address);
break;
+ default:
+ //
+ // The RootBridgeIoCheckParameter call above will ensure that this
+ // path is not taken.
+ //
+ ASSERT (FALSE);
+ break;
}
}
}
@@ -1074,6 +1102,13 @@ RootBridgeIoPciRW ( case EfiPciWidthUint32:
PciWrite32 (PcieRegAddr, *((UINT32 *)Uint8Buffer));
break;
+ default:
+ //
+ // The RootBridgeIoCheckParameter call above will ensure that this
+ // path is not taken.
+ //
+ ASSERT (FALSE);
+ break;
}
} else {
switch (OperationWidth) {
@@ -1086,6 +1121,13 @@ RootBridgeIoPciRW ( case EfiPciWidthUint32:
*((UINT32 *)Uint8Buffer) = PciRead32 (PcieRegAddr);
break;
+ default:
+ //
+ // The RootBridgeIoCheckParameter call above will ensure that this
+ // path is not taken.
+ //
+ ASSERT (FALSE);
+ break;
}
}
}
|