diff options
| author | zwei4 <david.wei@intel.com> | 2017-07-10 15:44:36 +0800 |
|---|---|---|
| committer | zwei4 <david.wei@intel.com> | 2017-07-10 15:44:36 +0800 |
| commit | 990ae5d7a341b881d623e8dcee9912227f55e613 (patch) | |
| tree | 1a68c0bb82d3257f7c73a358203a882c24a3d5b4 /Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem | |
| parent | e7bc47efaae843fa7dd2346532a1f5031d4e7629 (diff) | |
| download | edk2-platforms-990ae5d7a341b881d623e8dcee9912227f55e613.tar.xz | |
LPDDR4 Configuration.
Change LPDDR4 configuration for Benson Glacier.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david.wei@intel.com>
Diffstat (limited to 'Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem')
| -rw-r--r-- | Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/BoardInitMiscs.c | 34 |
1 files changed, 27 insertions, 7 deletions
diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/BoardInitMiscs.c index bb1c9bfaeb..5424df06f0 100644 --- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/BoardInitMiscs.c +++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/BoardInitMiscs.c @@ -83,13 +83,6 @@ BgUpdateFspmUpd ( }
}
- //
- // override RankEnable settings for Benson
- //
- FspUpdRgn->FspmConfig.Ch0_RankEnable = 1;
- FspUpdRgn->FspmConfig.Ch1_RankEnable = 1;
- FspUpdRgn->FspmConfig.Ch2_RankEnable = 1;
- FspUpdRgn->FspmConfig.Ch3_RankEnable = 1;
DEBUG ((DEBUG_INFO, "UpdateFspmUpd - gEfiPlatformInfoGuid\n"));
Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
@@ -104,10 +97,37 @@ BgUpdateFspmUpd ( ASSERT (FALSE);
}
+ FspUpdRgn->FspmConfig.Package = 1;
+ FspUpdRgn->FspmConfig.Profile = 11;
+ FspUpdRgn->FspmConfig.MemoryDown = 1;
+ FspUpdRgn->FspmConfig.DDR3LPageSize = 0;
+ FspUpdRgn->FspmConfig.DDR3LASR = 0;
+ FspUpdRgn->FspmConfig.MemorySizeLimit = 0x1800;
+ FspUpdRgn->FspmConfig.DIMM0SPDAddress = 0;
+ FspUpdRgn->FspmConfig.DIMM1SPDAddress = 0;
+ FspUpdRgn->FspmConfig.DDR3LPageSize = 0;
+ FspUpdRgn->FspmConfig.DDR3LASR = 0;
+
+ FspUpdRgn->FspmConfig.Ch0_RankEnable = 1;
+ FspUpdRgn->FspmConfig.Ch0_DeviceWidth = 2;
FspUpdRgn->FspmConfig.Ch0_DramDensity = 2;
+ FspUpdRgn->FspmConfig.Ch0_Option = 3;
+
+ FspUpdRgn->FspmConfig.Ch1_RankEnable = 1;
+ FspUpdRgn->FspmConfig.Ch1_DeviceWidth = 2;
FspUpdRgn->FspmConfig.Ch1_DramDensity = 2;
+ FspUpdRgn->FspmConfig.Ch1_Option = 3;
+
+ FspUpdRgn->FspmConfig.Ch2_RankEnable = 1;
+ FspUpdRgn->FspmConfig.Ch2_DeviceWidth = 2;
FspUpdRgn->FspmConfig.Ch2_DramDensity = 2;
+ FspUpdRgn->FspmConfig.Ch2_Option = 3;
+
+ FspUpdRgn->FspmConfig.Ch3_RankEnable = 1;
+ FspUpdRgn->FspmConfig.Ch3_DeviceWidth = 2;
FspUpdRgn->FspmConfig.Ch3_DramDensity = 2;
+ FspUpdRgn->FspmConfig.Ch3_Option = 3;
+
return EFI_SUCCESS;
}
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