diff options
| author | Rytkonen, Teemu S <teemu.s.rytkonen@intel.com> | 2017-11-15 01:16:05 +0800 |
|---|---|---|
| committer | zwei4 <david.wei@intel.com> | 2017-11-15 13:12:47 +0800 |
| commit | fb26da182091a7fd547af208363314b8e21464fc (patch) | |
| tree | b9a2a8d64b5f0f1d6ca8ea04433ba8f441c79464 /Platform/BroxtonPlatformPkg/Board/BensonGlacier | |
| parent | ea234bbec77b843748f08e490ddb70fe2787281c (diff) | |
| download | edk2-platforms-fb26da182091a7fd547af208363314b8e21464fc.tar.xz | |
BensonGlacier: Enable generic SPI device
-Enable generic SPI device for BensonGlacier config to be
used with SenseHat board.
-Enable GPIO config to enable SenseHat board programming
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Teemu Rytkonen <teemu.s.rytkonen@intel.com>
Diffstat (limited to 'Platform/BroxtonPlatformPkg/Board/BensonGlacier')
| -rw-r--r-- | Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h index d5accbc176..0278ea388a 100644 --- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h +++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h @@ -80,13 +80,13 @@ BXT_GPIO_PAD_INIT mBenson_GpioInitData_N[] = BXT_GPIO_PAD_CONF(L"GPIO_14", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0070, NORTH),//Feature: LB
BXT_GPIO_PAD_CONF(L"GPIO_15", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0078, NORTH),//Feature: LB
BXT_GPIO_PAD_CONF(L"GPIO_16", M0 , GPI , NA , NA , Edge , Wake_Disabled, P_20K_H, Inverted,IOAPIC, HizRx0I ,DisPuPd, GPIO_PADBAR+0x0080, NORTH),//Feature:SIM Card Detect Net in Sch: SIM_CON_CD1, falling edge trigger
- BXT_GPIO_PAD_CONF(L"GPIO_17", M0 , GPI , GPIO_D, NA , Edge , Wake_Disabled, P_NONE , NA ,IOAPIC, NA ,DisPuPd, GPIO_PADBAR+0x0088, NORTH), // SOC_LSE_HOST_IRQ_N + BXT_GPIO_PAD_CONF(L"GPIO_17", M0 , GPI , GPIO_D, NA , Edge , Wake_Disabled, P_NONE , NA ,IOAPIC, NA ,DisPuPd, GPIO_PADBAR+0x0088, NORTH), // SOC_LSE_HOST_IRQ_N
BXT_GPIO_PAD_CONF(L"GPIO_18", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA, GPIO_PADBAR+0x0090, NORTH),//Feature: LB
BXT_GPIO_PAD_CONF(L"GPIO_19", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA, GPIO_PADBAR+0x0098, NORTH),//Feature: LB
BXT_GPIO_PAD_CONF(L"GPIO_20", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA, GPIO_PADBAR+0x00A0, NORTH),//Feature: LB
BXT_GPIO_PAD_CONF(L"GPIO_21", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA, GPIO_PADBAR+0x00A8, NORTH),//Feature: LB
BXT_GPIO_PAD_CONF(L"GPIO_22", M0 , GPIO ,GPIO_D , NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA, GPIO_PADBAR+0x00B0, NORTH),//Feature: LB
- BXT_GPIO_PAD_CONF(L"GPIO_23", M0 , GPO ,GPIO_D, LO , NA , Wake_Disabled, P_20K_H, NA , NA, NA , EnPu, GPIO_PADBAR+0x00B8, NORTH), // SOC_SUE_RST_N + BXT_GPIO_PAD_CONF(L"GPIO_23", M0 , GPO ,GPIO_D, LO , NA , Wake_Disabled, P_20K_H, NA , NA, NA , EnPu, GPIO_PADBAR+0x00B8, NORTH), // SOC_SUE_RST_N
BXT_GPIO_PAD_CONF(L"GPIO_24", M0 , GPO ,GPIO_D , NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA, GPIO_PADBAR+0x00C0, NORTH),//SATA_DEVSLP0
BXT_GPIO_PAD_CONF(L"GPIO_25", M0 , GPO ,GPIO_D , NA , Level , Wake_Disabled, P_20K_H, Inverted, SCI, NA , NA, GPIO_PADBAR+0x00C8, NORTH),//Feature:ODD MD/DA SCI Net in Sch: SATA_ODD_DA_IN
BXT_GPIO_PAD_CONF(L"GPIO_26", M0 , GPIO ,GPIO_D , NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA, GPIO_PADBAR+0x00D0, NORTH),//SATA_LEDN
@@ -216,16 +216,16 @@ BXT_GPIO_PAD_INIT mBenson_GpioInitData_NW [] = BXT_GPIO_PAD_CONF(L"GPIO_106 GP_SSP_0_FS1", M0 , GPI , GPIO_D , NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , EnPd, GPIO_PADBAR+0x01F8, NORTHWEST),
BXT_GPIO_PAD_CONF(L"GPIO_109 GP_SSP_0_RXD", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , EnPd, GPIO_PADBAR+0x0200, NORTHWEST),
BXT_GPIO_PAD_CONF(L"GPIO_110 GP_SSP_0_TXD", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , EnPd, GPIO_PADBAR+0x0208, NORTHWEST),
- BXT_GPIO_PAD_CONF(L"GPIO_111 GP_SSP_1_CLK", M0 , GPI ,GPIO_D, NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0210, NORTHWEST),//Not used on RVP
- BXT_GPIO_PAD_CONF(L"GPIO_112 GP_SSP_1_FS0", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0218, NORTHWEST),
- BXT_GPIO_PAD_CONF(L"GPIO_113 GP_SSP_1_FS1", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0220, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_111 GP_SSP_1_CLK", M0 , GPI ,GPIO_D, NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0210, NORTHWEST),//Not used on RVP
+ BXT_GPIO_PAD_CONF(L"GPIO_112 GP_SSP_1_FS0", M0 , GPI ,GPIO_D, NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0218, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_113 GP_SSP_1_FS1", M0 , GPO ,GPIO_D, NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0220, NORTHWEST),
BXT_GPIO_PAD_CONF(L"GPIO_116 GP_SSP_1_RXD", M2 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0228, NORTHWEST),//Feature: LPSS UART Hdr
BXT_GPIO_PAD_CONF(L"GPIO_117 GP_SSP_1_TXD", M0 , GPIO , GPIO_D , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0230, NORTHWEST),//Feature: LPSS UART Hdr
- BXT_GPIO_PAD_CONF(L"GPIO_118 GP_SSP_2_CLK", M0 , GPIO , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0238, NORTHWEST),
- BXT_GPIO_PAD_CONF(L"GPIO_119 GP_SSP_2_FS0", M0 , GPIO , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0240, NORTHWEST),
- BXT_GPIO_PAD_CONF(L"GPIO_120 GP_SSP_2_FS1", M0 , GPIO , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0248, NORTHWEST),
- BXT_GPIO_PAD_CONF(L"GPIO_121 GP_SSP_2_FS2", M0 , GPIO , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0250, NORTHWEST),
- BXT_GPIO_PAD_CONF(L"GPIO_122 GP_SSP_2_RXD", M0 , GPIO , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0258, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_118 GP_SSP_2_CLK", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0238, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_119 GP_SSP_2_FS0", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0240, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_120 GP_SSP_2_FS1", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0248, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_121 GP_SSP_2_FS2", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0250, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_122 GP_SSP_2_RXD", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0258, NORTHWEST),
BXT_GPIO_PAD_CONF(L"GPIO_123 GP_SSP_2_TXD", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0260, NORTHWEST),
BXT_GPIO_PAD_CONF(L"GPIO_191 DBI_SDA", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0020, NORTHWEST),//Feature: DBI_SDA
BXT_GPIO_PAD_CONF(L"GPIO_192 DBI_SCL", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0028, NORTHWEST),//Feature: DBI_SCL
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