BroxtonPlatformPkg: Add LeafHill/BoardInitPreMem

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>

7 files changed, 1122 insertions, 0 deletions

diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInit.c b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInit.c
new file mode 100644
index 0000000000..5dab22514a
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInit.c
@@ -0,0 +1,181 @@
+/** @file

+  Board Init driver.

+

+  Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>

+

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php.

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+**/

+

+#include <PiPei.h>

+#include <Library/PeiServicesLib.h>

+#include <Library/PcdLib.h>

+#include <Library/BaseMemoryLib.h>

+#include <Library/DebugLib.h>

+#include <Guid/PlatformInfo_Aplk.h>

+#include <Ppi/BoardInitSignalling.h>

+#include "BoardInit.h"

+#include "PlatformId.h"

+#include "BoardInitMiscs.h"

+

+EFI_STATUS

+EFIAPI

+LeafHillPreMemInit (

+  IN CONST EFI_PEI_SERVICES     **PeiServices,

+  IN PEI_BOARD_PRE_MEM_INIT_PPI *This

+  );

+

+static PEI_BOARD_PRE_MEM_INIT_PPI mPreMemInitPpiInstance = {

+  LeafHillPreMemInit

+};

+

+static EFI_PEI_PPI_DESCRIPTOR mLeafHillPreMemInitPpi = {

+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),

+  &gBoardPreMemInitPpiGuid,

+  &mPreMemInitPpiInstance

+};

+

+static EFI_PEI_PPI_DESCRIPTOR mLeafHillPreMemInitDonePpi = {

+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),

+  &gBoardPreMemInitDoneGuid,

+  NULL

+};

+

+EFI_STATUS

+EFIAPI

+LeafHillPreMemInit (

+  IN CONST EFI_PEI_SERVICES     **PeiServices,

+  IN PEI_BOARD_PRE_MEM_INIT_PPI *This

+  )

+{

+  EFI_STATUS                       Status;

+  VOID                             *Instance;

+  UINT8                            BoardId;

+  UINT8                            FabId;

+

+  BoardId = 0;

+  FabId = 0;

+  Status = PeiServicesLocatePpi (

+             &gBoardPreMemInitDoneGuid,

+             0,

+             NULL,

+             &Instance

+             );

+  if (!EFI_ERROR (Status)) {

+     DEBUG ((EFI_D_INFO,  "LeafHill PreMem Init: Skip\n"));

+    return EFI_SUCCESS;

+  }

+  DEBUG ((EFI_D_INFO,  "LeafHill Pre Mem Init\n"));

+

+  //

+  // Pre Mem Board Init

+  //

+  Status = GetEmbeddedBoardIdFabId (PeiServices, &BoardId, &FabId);

+  if (BoardId != (UINT8) BOARD_ID_LFH_CRB) {

+    DEBUG ((EFI_D_INFO,  "Not a Leaf Hill Board - skip\n"));

+    return EFI_SUCCESS;

+  }

+

+  PcdSet8 (PcdBoardId, BoardId);

+  PcdSet8 (PcdFabId, FabId);

+

+  //

+  // Set board specific function as dynamic PCD to be called by common platform code

+  //

+  PcdSet64 (PcdUpdateFspmUpdFunc, (UINT64) (UINTN) mLhUpdateFspmUpdPtr);

+  PcdSet64 (PcdDramCreatePolicyDefaultsFunc, (UINT64) (UINTN) mLhDramCreatePolicyDefaultsPtr);

+

+  //

+  // Install a flag signalling a board is detected and pre-mem init is done

+  //

+  Status = PeiServicesInstallPpi (&mLeafHillPreMemInitDonePpi);

+

+  return EFI_SUCCESS;

+}

+

+

+/**

+  This function performs Board initialization in Pre-Memory.

+

+  @retval     EFI_SUCCESS           The PPI is installed and initialized.

+  @retval     EFI ERRORS            The PPI is not successfully installed.

+  @retval     EFI_OUT_OF_RESOURCES  No enough resoruces (such as out of memory).

+

+**/

+EFI_STATUS

+EFIAPI

+LeafHillInitConstructor (

+  IN       EFI_PEI_FILE_HANDLE  FileHandle,

+  IN CONST EFI_PEI_SERVICES     **PeiServices

+  )

+{

+  EFI_STATUS                       Status;

+  VOID                             *Ppi;

+  EFI_PEI_PPI_DESCRIPTOR           *PeiPpiDescriptor;

+  UINTN                            Instance;

+

+  DEBUG ((EFI_D_INFO,  "LeafHill Pre Mem Init Constructor \n"));

+

+  Status = PeiServicesLocatePpi (

+             &gBoardPreMemInitDoneGuid,

+             0,

+             &PeiPpiDescriptor,

+             &Ppi

+             );

+  if (!EFI_ERROR (Status)) {

+    //

+    // Board detection previously done, so this is a re-invocation shadowed in memory.

+    // Reinstall PPIs to eliminate PPI descriptors in torn down temp RAM.

+    //

+    //

+    // Reinstall PreMemInit Done PPI

+    //

+    DEBUG ((EFI_D_INFO,  "Reinstall Pre Mem Init Done PPI\n"));

+    Status = PeiServicesReInstallPpi (

+               PeiPpiDescriptor,

+               &mLeafHillPreMemInitDonePpi

+               );

+    ASSERT_EFI_ERROR (Status);

+

+    //

+    // Reinstall all instances of Pre Mem Init PPIs.

+    // These PPIs are no longer used so it doesn't matter which board's instance is finally installed.

+    // According to PeiServicesReInstallPpi behavior:

+    // The first run of this loop would replace all descrioptors with a singe in-RAM descriptor;

+    // Subsequent runs of this loop will only replace the first (already in-RAM) descriptor.

+    // As long as all descriptors are in ram, we are fine.

+    //

+    Instance = 0;

+    do {

+      Status = PeiServicesLocatePpi (

+                 &gBoardPreMemInitPpiGuid,

+                 Instance,

+                 &PeiPpiDescriptor,

+                 &Ppi

+                 );

+      if (Status == EFI_NOT_FOUND) {

+        break;

+      }

+      ASSERT_EFI_ERROR (Status);

+      DEBUG ((EFI_D_INFO,  "Reinstall Pre Mem Init PPI\n"));

+      Status = PeiServicesReInstallPpi (

+                 PeiPpiDescriptor,

+                 &mLeafHillPreMemInitPpi

+                 );

+      ASSERT_EFI_ERROR (Status);

+      Instance++;

+    } while (TRUE);

+    return Status;

+  }

+  DEBUG ((EFI_D_INFO,  "Install Pre Mem Init PPI \n"));

+  Status = PeiServicesInstallPpi (&mLeafHillPreMemInitPpi);

+

+  return Status;

+}

+

diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInit.h b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInit.h
new file mode 100644
index 0000000000..373b203127
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInit.h
@@ -0,0 +1,29 @@
+/** @file

+  GPIO setting for CherryView.

+  This file includes package header files, library classes.

+

+  Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>

+

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php.

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+**/

+

+#ifndef _BOARDINIT_H_

+#define _BOARDINIT_H_

+

+#include <PiPei.h>

+#include <Library/IoLib.h>

+#include <Library/HobLib.h>

+#include <Library/Timerlib.h>

+#include <Guid/PlatformInfo_Aplk.h>

+

+VOID GpioTest (VOID);

+

+#endif

+

diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c
new file mode 100644
index 0000000000..0a932015e0
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c
@@ -0,0 +1,448 @@
+/** @file

+  This file does Multiplatform initialization.

+

+  Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>

+

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php.

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+**/

+

+#include "BoardInitMiscs.h"

+

+UPDATE_FSPM_UPD_FUNC mLhUpdateFspmUpdPtr = LhUpdateFspmUpd;

+DRAM_CREATE_POLICY_DEFAULTS_FUNC   mLhDramCreatePolicyDefaultsPtr = LhDramCreatePolicyDefaults;

+

+EFI_STATUS

+EFIAPI

+LhUpdateFspmUpd (

+  IN CONST EFI_PEI_SERVICES  **PeiServices,

+  IN FSPM_UPD                *FspUpdRgn

+  )

+{

+  EFI_PEI_HOB_POINTERS           Hob;

+  EFI_PLATFORM_INFO_HOB          *PlatformInfo = NULL;

+  DRAM_POLICY_PPI                *DramPolicy;

+  EFI_STATUS                     Status;

+

+  Status = (*PeiServices)->LocatePpi (

+                             PeiServices,

+                             &gDramPolicyPpiGuid,

+                             0,

+                             NULL,

+                             (VOID **) &DramPolicy

+                             );

+

+  if (!EFI_ERROR (Status)) {

+    FspUpdRgn->FspmConfig.Package                           = DramPolicy->Package;

+    FspUpdRgn->FspmConfig.Profile                           = DramPolicy->Profile;

+    FspUpdRgn->FspmConfig.MemoryDown                        = DramPolicy->MemoryDown;

+    FspUpdRgn->FspmConfig.DDR3LPageSize                     = DramPolicy->DDR3LPageSize;

+    FspUpdRgn->FspmConfig.DDR3LASR                          = DramPolicy->DDR3LASR;

+    FspUpdRgn->FspmConfig.MemorySizeLimit                   = DramPolicy->SystemMemorySizeLimit;

+    FspUpdRgn->FspmConfig.DIMM0SPDAddress                   = DramPolicy->SpdAddress[0];

+    FspUpdRgn->FspmConfig.DIMM1SPDAddress                   = DramPolicy->SpdAddress[1];

+    FspUpdRgn->FspmConfig.DDR3LPageSize                     = DramPolicy->DDR3LPageSize;

+    FspUpdRgn->FspmConfig.DDR3LASR                          = DramPolicy->DDR3LASR;

+    FspUpdRgn->FspmConfig.HighMemoryMaxValue                = DramPolicy->HighMemMaxVal;

+    FspUpdRgn->FspmConfig.LowMemoryMaxValue                 = DramPolicy->LowMemMaxVal;

+    FspUpdRgn->FspmConfig.DisableFastBoot                   = DramPolicy->DisableFastBoot;

+    FspUpdRgn->FspmConfig.RmtMode                           = DramPolicy->RmtMode;

+    FspUpdRgn->FspmConfig.RmtCheckRun                       = DramPolicy->RmtCheckRun;

+    FspUpdRgn->FspmConfig.RmtMarginCheckScaleHighThreshold  = DramPolicy->RmtMarginCheckScaleHighThreshold;

+    FspUpdRgn->FspmConfig.MsgLevelMask                      = DramPolicy->MsgLevelMask;

+

+    FspUpdRgn->FspmConfig.ChannelHashMask                   = DramPolicy->ChannelHashMask;

+    FspUpdRgn->FspmConfig.SliceHashMask                     = DramPolicy->SliceHashMask;

+    FspUpdRgn->FspmConfig.ChannelsSlicesEnable              = DramPolicy->ChannelsSlicesEnabled;

+    FspUpdRgn->FspmConfig.ScramblerSupport                  = DramPolicy->ScramblerSupport;

+    FspUpdRgn->FspmConfig.InterleavedMode                   = DramPolicy->InterleavedMode;

+    FspUpdRgn->FspmConfig.MinRefRate2xEnable                = DramPolicy->MinRefRate2xEnabled;

+    FspUpdRgn->FspmConfig.DualRankSupportEnable             = DramPolicy->DualRankSupportEnabled;

+    FspUpdRgn->FspmArchUpd.NvsBufferPtr                     = (VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr;

+    FspUpdRgn->FspmConfig.MrcBootDataPtr                    = (VOID *)(UINT32)DramPolicy->MrcBootDataPtr;

+

+    CopyMem (&(FspUpdRgn->FspmConfig.Ch0_RankEnable), &DramPolicy->ChDrp, sizeof (DramPolicy->ChDrp));

+    CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), &DramPolicy->ChSwizzle, sizeof (DramPolicy->ChSwizzle));

+  }

+  //

+  // override RankEnable settings for Minnow

+  //

+  FspUpdRgn->FspmConfig.Ch0_RankEnable   = 1;

+  FspUpdRgn->FspmConfig.Ch1_RankEnable   = 1;

+  FspUpdRgn->FspmConfig.Ch2_RankEnable   = 1;

+  FspUpdRgn->FspmConfig.Ch3_RankEnable   = 1;

+

+  DEBUG ((DEBUG_INFO, "UpdateFspmUpd - gEfiPlatformInfoGuid\n"));

+  Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);

+  ASSERT (Hob.Raw != NULL);

+  PlatformInfo = GET_GUID_HOB_DATA (Hob.Raw);

+

+  DEBUG ((DEBUG_INFO, "***** LeafHill - UpdateFspmUpd,BoardId = %d\n", PlatformInfo->BoardId));

+

+  if (PlatformInfo->BoardId != BOARD_ID_LFH_CRB) {

+    //

+    // ASSERT false if BoardId isn't LeafHill

+    //

+    ASSERT (FALSE);

+  }

+

+  FspUpdRgn->FspmConfig.Package         = 1;

+  FspUpdRgn->FspmConfig.Profile         = 11;

+  FspUpdRgn->FspmConfig.MemoryDown      = 1;

+  FspUpdRgn->FspmConfig.DDR3LPageSize   = 0;

+  FspUpdRgn->FspmConfig.DDR3LASR        = 0;

+  FspUpdRgn->FspmConfig.MemorySizeLimit = 0x1800;

+  FspUpdRgn->FspmConfig.DIMM0SPDAddress = 0;

+  FspUpdRgn->FspmConfig.DIMM1SPDAddress = 0;

+  FspUpdRgn->FspmConfig.DDR3LPageSize   = 0;

+  FspUpdRgn->FspmConfig.DDR3LASR        = 0;

+

+  FspUpdRgn->FspmConfig.Ch0_RankEnable   = 3;

+  FspUpdRgn->FspmConfig.Ch0_DeviceWidth  = 1;

+  FspUpdRgn->FspmConfig.Ch0_DramDensity  = 2;

+  FspUpdRgn->FspmConfig.Ch0_Option       = 3;

+

+  FspUpdRgn->FspmConfig.Ch1_RankEnable   = 3;

+  FspUpdRgn->FspmConfig.Ch1_DeviceWidth  = 1;

+  FspUpdRgn->FspmConfig.Ch1_DramDensity  = 2;

+  FspUpdRgn->FspmConfig.Ch1_Option       = 3;

+

+  FspUpdRgn->FspmConfig.Ch2_RankEnable   = 3;

+  FspUpdRgn->FspmConfig.Ch2_DeviceWidth  = 1;

+  FspUpdRgn->FspmConfig.Ch2_DramDensity  = 2;

+  FspUpdRgn->FspmConfig.Ch2_Option       = 3;

+

+  FspUpdRgn->FspmConfig.Ch3_RankEnable   = 3;

+  FspUpdRgn->FspmConfig.Ch3_DeviceWidth  = 1;

+  FspUpdRgn->FspmConfig.Ch3_DramDensity  = 2;

+  FspUpdRgn->FspmConfig.Ch3_Option       = 3;

+

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[0]   = 0x09;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[1]   = 0x0e;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[2]   = 0x0c;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[3]   = 0x0d;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[4]   = 0x0a;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[5]   = 0x0b;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[6]   = 0x08;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[7]   = 0x0f;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[8]   = 0x05;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[9]   = 0x06;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[10]  = 0x01;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[11]  = 0x00;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[12]  = 0x02;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[13]  = 0x07;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[14]  = 0x04;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[15]  = 0x03;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[16]  = 0x1a;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[17]  = 0x1f;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[18]  = 0x1c;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[19]  = 0x1b;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[20]  = 0x1d;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[21]  = 0x19;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[22]  = 0x18;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[23]  = 0x1e;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[24]  = 0x14;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[25]  = 0x16;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[26]  = 0x17;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[27]  = 0x11;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[28]  = 0x12;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[29]  = 0x13;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[30]  = 0x10;

+  FspUpdRgn->FspmConfig.Ch0_Bit_swizzling[31]  = 0x15;

+

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[0]   = 0x06;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[1]   = 0x07;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[2]   = 0x05;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[3]   = 0x04;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[4]   = 0x03;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[5]   = 0x01;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[6]   = 0x00;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[7]   = 0x02;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[8]   = 0x0c;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[9]   = 0x0a;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[10]  = 0x0b;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[11]  = 0x0d;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[12]  = 0x0e;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[13]  = 0x08;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[14]  = 0x09;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[15]  = 0x0f;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[16]  = 0x14;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[17]  = 0x10;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[18]  = 0x16;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[19]  = 0x15;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[20]  = 0x12;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[21]  = 0x11;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[22]  = 0x13;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[23]  = 0x17;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[24]  = 0x1e;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[25]  = 0x1c;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[26]  = 0x1d;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[27]  = 0x19;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[28]  = 0x18;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[29]  = 0x1a;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[30]  = 0x1b;

+  FspUpdRgn->FspmConfig.Ch1_Bit_swizzling[31]  = 0x1f;

+

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[0]   = 0x0f;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[1]   = 0x09;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[2]   = 0x08;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[3]   = 0x0b;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[4]   = 0x0c;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[5]   = 0x0d;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[6]   = 0x0e;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[7]   = 0x0a;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[8]   = 0x05;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[9]   = 0x02;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[10]  = 0x00;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[11]  = 0x03;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[12]  = 0x06;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[13]  = 0x07;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[14]  = 0x01;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[15]  = 0x04;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[16]  = 0x19;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[17]  = 0x1c;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[18]  = 0x1e;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[19]  = 0x1f;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[20]  = 0x1a;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[21]  = 0x1b;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[22]  = 0x18;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[23]  = 0x1d;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[24]  = 0x14;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[25]  = 0x17;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[26]  = 0x16;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[27]  = 0x15;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[28]  = 0x12;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[29]  = 0x13;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[30]  = 0x10;

+  FspUpdRgn->FspmConfig.Ch2_Bit_swizzling[31]  = 0x11;

+

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[0]   = 0x03;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[1]   = 0x04;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[2]   = 0x06;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[3]   = 0x05;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[4]   = 0x00;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[5]   = 0x01;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[6]   = 0x02;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[7]   = 0x07;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[8]   = 0x0b;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[9]   = 0x0a;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[10]  = 0x08;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[11]  = 0x09;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[12]  = 0x0e;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[13]  = 0x0c;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[14]  = 0x0f;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[15]  = 0x0d;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[16]  = 0x11;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[17]  = 0x17;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[18]  = 0x13;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[19]  = 0x10;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[20]  = 0x15;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[21]  = 0x16;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[22]  = 0x14;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[23]  = 0x12;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[24]  = 0x1c;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[25]  = 0x1d;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[26]  = 0x1a;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[27]  = 0x19;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[28]  = 0x1e;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[29]  = 0x1b;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[30]  = 0x18;

+  FspUpdRgn->FspmConfig.Ch3_Bit_swizzling[31]  = 0x1f;

+

+  FspUpdRgn->FspmConfig.ChannelHashMask       = 0;

+  FspUpdRgn->FspmConfig.SliceHashMask         = 0;

+  FspUpdRgn->FspmConfig.ChannelsSlicesEnable  = 0;

+  FspUpdRgn->FspmConfig.ScramblerSupport      = 1;

+  FspUpdRgn->FspmConfig.InterleavedMode       = 0;

+  FspUpdRgn->FspmConfig.MinRefRate2xEnable    = 0;

+  FspUpdRgn->FspmConfig.DualRankSupportEnable = 1;

+

+  return EFI_SUCCESS;

+}

+

+

+/**

+  DramCreatePolicyDefaults creates the default setting of Dram Policy.

+

+  @param[out] DramPolicyPpi           The pointer to get Dram Policy PPI instance

+

+  @retval     EFI_SUCCESS             The policy default is initialized.

+  @retval     EFI_OUT_OF_RESOURCES    Insufficient resources to create buffer

+

+**/

+EFI_STATUS

+EFIAPI

+LhDramCreatePolicyDefaults (

+  IN  EFI_PEI_READ_ONLY_VARIABLE2_PPI  *VariablePpi,

+  OUT DRAM_POLICY_PPI                  **DramPolicyPpi,

+  IN  IAFWDramConfig                   *DramConfigData,

+  IN  UINTN                            *MrcTrainingDataAddr,

+  IN  UINTN                            *MrcBootDataAddr,

+  IN  UINT8                            BoardId

+  )

+{

+  DRAM_POLICY_PPI                     *DramPolicy;

+  SYSTEM_CONFIGURATION                SystemConfiguration;

+  UINTN                               VariableSize;

+  EFI_STATUS                          Status;

+  DRP_DRAM_POLICY                     *DrpPtr;

+  UINT8                               (*ChSwizlePtr)[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS];

+  PlatfromDramConf                    *DramConfig;

+  BOOLEAN                             ReadSetupVars;

+  EFI_PLATFORM_INFO_HOB               *PlatformInfoHob = NULL;

+  EFI_PEI_HOB_POINTERS                Hob;

+

+  DEBUG ((EFI_D_INFO, "*** Leaf Hill DramCreatePolicyDefaults\n"));

+  DramPolicy = (DRAM_POLICY_PPI *) AllocateZeroPool (sizeof (DRAM_POLICY_PPI));

+  if (DramPolicy == NULL) {

+    ASSERT (FALSE);

+    return EFI_OUT_OF_RESOURCES;

+  }

+

+  ReadSetupVars = FALSE;

+  DrpPtr        = NULL;

+  ChSwizlePtr   = NULL;

+  DramConfig    = NULL;

+

+  VariableSize = sizeof (SYSTEM_CONFIGURATION);

+  Status = VariablePpi->GetVariable (

+                          VariablePpi,

+                          PLATFORM_SETUP_VARIABLE_NAME,

+                          &gEfiSetupVariableGuid,

+                          NULL,

+                          &VariableSize,

+                          &SystemConfiguration

+                          );

+

+#if !(ONLY_USE_SMIP_DRAM_POLICY == 1)

+  Status = EFI_UNSUPPORTED;

+#endif

+

+  if (!EFI_ERROR (Status)) {

+    DEBUG ((EFI_D_INFO, "Using setup options data for DRAM policy\n"));

+    ReadSetupVars = TRUE;

+    DramPolicy->ChannelHashMask         = SystemConfiguration.ChannelHashMask;

+    DramPolicy->SliceHashMask           = SystemConfiguration.SliceHashMask;

+    DramPolicy->ChannelsSlicesEnabled   = SystemConfiguration.ChannelsSlicesEnabled;

+    DramPolicy->ScramblerSupport        = SystemConfiguration.ScramblerSupport;

+    DramPolicy->InterleavedMode         = SystemConfiguration.InterleavedMode;

+    DramPolicy->MinRefRate2xEnabled     = SystemConfiguration.MinRefRate2xEnabled;

+    DramPolicy->DualRankSupportEnabled  = SystemConfiguration.DualRankSupportEnabled;

+  }

+

+  DramConfig = &(DramConfigData->PlatformDram4);

+

+  DEBUG ((EFI_D_INFO, "Using smip platform override: %d\n", DramConfigData->Platform_override));

+  switch (DramConfigData->Platform_override) {

+    case 0:

+      DramConfig = &(DramConfigData->PlatformDram0);

+      break;

+    case 1:

+      DramConfig = &(DramConfigData->PlatformDram1);

+      break;

+    case 2:

+      DramConfig = &(DramConfigData->PlatformDram2);

+      break;

+    case 3:

+      DramConfig = &(DramConfigData->PlatformDram3);

+      break;

+    case 4:

+      DramConfig = &(DramConfigData->PlatformDram4);

+      break;

+    default:

+      //

+      // Do nothing if the override value does not exist. 0xFF is the

+      // default Platform_override value when no override is selected

+      //

+      break;

+    }

+

+  DramPolicy->Package                            = DramConfig->Package;

+  DramPolicy->Profile                            = DramConfig->Profile;

+  DramPolicy->MemoryDown                         = DramConfig->MemoryDown;

+  DramPolicy->DDR3LPageSize                      = DramConfig->DDR3LPageSize;

+  DramPolicy->DDR3LASR                           = DramConfig->DDR3LASR;

+  DramPolicy->SystemMemorySizeLimit              = DramConfig->MemorySizeLimit;

+  DramPolicy->SpdAddress[0]                      = DramConfig->SpdAddress0;

+  DramPolicy->SpdAddress[1]                      = DramConfig->SpdAddress1;

+  DramPolicy->DDR3LPageSize                      = DramConfig->DDR3LPageSize;

+  DramPolicy->DDR3LASR                           = DramConfig->DDR3LASR;

+  DramPolicy->HighMemMaxVal                      = DramConfig->HighMemMaxVal;

+  DramPolicy->LowMemMaxVal                       = DramConfig->LowMemMaxVal;

+  DramPolicy->DisableFastBoot                    = DramConfig->DisableFastBoot;

+  DramPolicy->RmtMode                            = DramConfig->RmtMode;

+  DramPolicy->RmtCheckRun                        = DramConfig->RmtCheckRun;

+  DramPolicy->RmtMarginCheckScaleHighThreshold   = DramConfig->RmtMarginCheckScaleHighThreshold;

+

+  DramPolicy->MsgLevelMask                       = DramConfigData->Message_level_mask;

+  DrpPtr                                         = (DRP_DRAM_POLICY *) (&(DramConfig->Ch0RankEnabled));

+  ChSwizlePtr                                    = (UINT8(*)[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS]) (&(DramConfig->Ch0_Bit00_swizzling));

+

+  if (!ReadSetupVars) {

+    DEBUG ((EFI_D_INFO, "Using smip data for DRAM policy\n"));

+    DramPolicy->ChannelHashMask         = DramConfig->ChannelHashMask;

+    DramPolicy->SliceHashMask           = DramConfig->SliceHashMask;

+    DramPolicy->ChannelsSlicesEnabled   = DramConfig->ChannelsSlicesEnabled;

+    DramPolicy->ScramblerSupport        = DramConfig->ScramblerSupport;

+    DramPolicy->InterleavedMode         = DramConfig->InterleavedMode;

+    DramPolicy->MinRefRate2xEnabled     = DramConfig->MinRefRate2xEnabled;

+    DramPolicy->DualRankSupportEnabled  = DramConfig->DualRankSupportEnabled;

+  }

+

+  if (DrpPtr != NULL) {

+    CopyMem (DramPolicy->ChDrp, DrpPtr, sizeof (DramPolicy->ChDrp));

+  }

+

+  Status = VariablePpi->GetVariable (

+                          VariablePpi,

+                          PLATFORM_SETUP_VARIABLE_NAME,

+                          &gEfiSetupVariableGuid,

+                          NULL,

+                          &VariableSize,

+                          &SystemConfiguration

+                          );

+

+  if (!EFI_ERROR (Status)) {

+    if (SystemConfiguration.Max2G == 0) {

+      DramPolicy->SystemMemorySizeLimit = 0x800;

+    }

+  }

+

+  if (ChSwizlePtr != NULL) CopyMem (DramPolicy->ChSwizzle, ChSwizlePtr, sizeof (DramPolicy->ChSwizzle));

+

+  DramPolicy->MrcTrainingDataPtr = (EFI_PHYSICAL_ADDRESS) *MrcTrainingDataAddr;

+  DramPolicy->MrcBootDataPtr     = (EFI_PHYSICAL_ADDRESS) *MrcBootDataAddr;

+

+  //

+  // WA for MH board to 6GB. We just apply it if memory size has not been override in smip XML.

+  //

+  if (DramPolicy->SystemMemorySizeLimit == 0) {

+    DramPolicy->SystemMemorySizeLimit = 0x1800;

+    if ((DramPolicy->ChDrp[2].RankEnable == 0) && (DramPolicy->ChDrp[3].RankEnable == 0)) {  //half config

+      DramPolicy->SystemMemorySizeLimit /= 2;

+    }

+  }

+

+  //

+  // Get Platform Info HOB

+  //

+  Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);

+  ASSERT (Hob.Raw != NULL);

+  PlatformInfoHob = GET_GUID_HOB_DATA (Hob.Raw);

+

+  if (PlatformInfoHob->BoardRev == FAB_ID_D) {

+    DramPolicy->SystemMemorySizeLimit = 0;

+    DEBUG ((EFI_D_INFO, "Detect Micron memory\n"));

+  }

+

+  *DramPolicyPpi = DramPolicy;

+

+  return EFI_SUCCESS;

+}

+

diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.h b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.h
new file mode 100644
index 0000000000..57296b2258
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.h
@@ -0,0 +1,46 @@
+/** @file

+  Multiplatform initialization header file.

+  This file includes package header files, library classes.

+

+  Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>

+

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php.

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+**/

+

+#ifndef _MULTIPLATFORM_LIB_H_

+#define _MULTIPLATFORM_LIB_H_

+

+#include <BoardFunctionsPei.h>

+#include <Guid/SetupVariable.h>

+#include <Library/MemoryAllocationLib.h>

+

+extern UPDATE_FSPM_UPD_FUNC mLhUpdateFspmUpdPtr;

+extern DRAM_CREATE_POLICY_DEFAULTS_FUNC mLhDramCreatePolicyDefaultsPtr;

+

+EFI_STATUS

+EFIAPI

+LhUpdateFspmUpd (

+  IN CONST EFI_PEI_SERVICES  **PeiServices,

+  IN FSPM_UPD                *FspUpdRgn

+  );

+

+EFI_STATUS

+EFIAPI

+LhDramCreatePolicyDefaults (

+  IN  EFI_PEI_READ_ONLY_VARIABLE2_PPI  *VariablePpi,

+  OUT DRAM_POLICY_PPI                  **DramPolicyPpi,

+  IN  IAFWDramConfig                   *DramConfigData,

+  IN  UINTN                            *MrcTrainingDataAddr,

+  IN  UINTN                            *MrcBootDataAddr,

+  IN  UINT8                            BoardId

+  );

+

+#endif

+

diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitPreMem.inf b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitPreMem.inf
new file mode 100644
index 0000000000..97ed7b2342
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitPreMem.inf
@@ -0,0 +1,56 @@
+## @file

+#  Board detected module for Intel(R) Atom(TM) x5 Processor Series.

+#  It will detect the board ID.

+#

+#  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>

+#

+#  This program and the accompanying materials

+#  are licensed and made available under the terms and conditions of the BSD License

+#  which accompanies this distribution. The full text of the license may be found at

+#  http://opensource.org/licenses/bsd-license.php.

+#

+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+#

+##

+

+[Defines]

+  INF_VERSION                    = 0x00010017

+  BASE_NAME                      = LeafHillInitPreMem

+  FILE_GUID                      = 10B1B97A-1DC2-41E0-B2FD-8AD549D6782F

+  VERSION_STRING                 = 1.0

+  MODULE_TYPE                    = PEIM

+  CONSTRUCTOR                    = LeafHillInitConstructor

+

+[Sources]

+  BoardInit.c

+  PlatformId.c

+  BoardInitMiscs.c

+

+[LibraryClasses]

+  PeiServicesLib

+  PcdLib

+

+[Packages]

+  MdePkg/MdePkg.dec

+  BroxtonPlatformPkg/PlatformPkg.dec

+  BroxtonSiPkg/BroxtonSiPkg.dec

+  BroxtonFspPkg/BroxtonFspPkg.dec

+  IntelFsp2Pkg/IntelFsp2Pkg.dec

+  BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec

+  IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec

+

+[Pcd]

+  gPlatformModuleTokenSpaceGuid.PcdBoardId

+  gPlatformModuleTokenSpaceGuid.PcdFabId

+  gPlatformModuleTokenSpaceGuid.PcdUpdateFspmUpdFunc

+  gPlatformModuleTokenSpaceGuid.PcdDramCreatePolicyDefaultsFunc

+  gMinnowModuleTokenSpaceGuid.PcdDefaultFabId            ## CONSUMES

+  gMinnowModuleTokenSpaceGuid.PcdMinnowBoardDetectionRun ## CONSUMES

+  gMinnowModuleTokenSpaceGuid.PcdMinnowBoardDetected     ## CONSUMES

+

+[Guids]

+

+[Ppis]

+  gBoardPreMemInitPpiGuid

+  gBoardPreMemInitDoneGuid

diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/PlatformId.c b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/PlatformId.c
new file mode 100644
index 0000000000..19c1bb561d
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/PlatformId.c
@@ -0,0 +1,281 @@
+/** @file

+  Implement Platform ID code.

+

+  Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>

+

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php.

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+**/

+

+#include <Uefi.h>

+#include <Library/BaseMemoryLib.h>

+#include <Library/I2CLib.h>

+#include <Library/GpioLib.h>

+#include <Guid/PlatformInfo.h>

+#include "PlatformId.h"

+

+/**

+  Read in GPIO state and return it.

+

+**/

+BOOLEAN

+IsThisMinnow (

+  VOID

+  )

+{

+  UINT32           CommAndOffset      = NW_GPIO_215;

+  BXT_CONF_PAD0    PadConfg0;

+  BXT_CONF_PAD1    PadConfg1;

+  BOOLEAN          ReturnValue;

+

+  if (PcdGetBool (PcdMinnowBoardDetectionRun)) {

+    //

+    // Already detected this. Return stored value.

+    //

+    ReturnValue = PcdGetBool (PcdMinnowBoardDetected);

+    DEBUG ((EFI_D_INFO, "Already detected. Returning stored value = %x\n", ReturnValue));

+  } else {

+    //

+    // Enable GPI mode with a pull-up

+    //

+    PadConfg0.padCnf0       = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);

+    PadConfg1.padCnf1       = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET);

+    PadConfg0.r.PMode       = M0;      // Set to GPIO mode

+    PadConfg0.r.GPIORxTxDis = GPI;     // Set to GPI

+    PadConfg1.r.IOSTerm     = EnPu;    // Enable pull-up

+    PadConfg1.r.Term        = P_20K_H; // Set to 20K pull-up

+    GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, PadConfg0.padCnf0);

+    GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, PadConfg1.padCnf1);

+

+    //

+    // Read in GPI state and set return value

+    //

+    PadConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);

+    ReturnValue       = (BOOLEAN) PadConfg0.r.GPIORxState;

+

+    //

+    // Set detection PCDs

+    //

+    PcdSetBoolS (PcdMinnowBoardDetectionRun, TRUE);

+    PcdSetBoolS (PcdMinnowBoardDetected, ReturnValue);

+  }

+

+  //

+  // Return answer

+  //

+  return ReturnValue;

+}

+

+

+EFI_STATUS

+EFIAPI

+GetEmbeddedBoardIdFabId(

+  IN CONST EFI_PEI_SERVICES     **PeiServices,

+  OUT UINT8                     *BoardId,

+  OUT UINT8                     *FabId

+  )

+{

+  BXT_CONF_PAD0   padConfg0;

+  BXT_CONF_PAD1   padConfg1;

+  IN UINT32       CommAndOffset;

+

+  DEBUG ((DEBUG_INFO, "GetEmbeddedBoardIdFabId++\n"));

+

+  //

+  // Set BoardId & FabId

+  //

+  if (IsThisMinnow ()) {

+    //

+    // NW_PMIC_PWRGOOD says this is a Minnow board. Force Minnow defaults.

+    //

+    *BoardId = BOARD_ID_MINNOW;

+    *FabId   = PcdGet8 (PcdDefaultFabId);

+

+    DEBUG ((EFI_D_INFO,  "BoardId forced from NW_GPIO_215 detection: %02X\n", *BoardId));

+    DEBUG ((EFI_D_INFO,  "  FabId forced from NW_GPIO_215 detection: %02X\n", *FabId));

+  } else {

+    //

+    // Board_ID0: PMIC_STDBY

+    //

+    CommAndOffset = GetCommOffset (NORTHWEST, 0x00F0);

+    padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);

+    padConfg0.r.PMode = 0;         // Set to GPIO mode

+    padConfg0.r.GPIORxTxDis = 0x1; // Set to GPI

+    GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);

+    padConfg1.padCnf1 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET);

+    //

+    // Set to Pull Up 20K

+    //

+    padConfg1.r.Term = 0xC;

+    GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);

+    //

+    // Board_ID1: PMIC_SDWN_B

+    //

+    CommAndOffset = GetCommOffset (NORTHWEST, 0x00D0);

+    padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);

+    padConfg0.r.PMode = 0;

+    padConfg0.r.GPIORxTxDis = 0x1;

+    GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);

+    //

+    // Board_ID2: PMIC_RESET_B

+    //

+    CommAndOffset = GetCommOffset (NORTHWEST, 0x00C8);

+    padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);

+    padConfg0.r.PMode = 0;

+    padConfg0.r.GPIORxTxDis = 0x1;

+    GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);

+    //

+    // Board_ID3: PMIC_PWRGOOD

+    //

+    CommAndOffset = GetCommOffset (NORTHWEST, 0x00C0);

+    padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);

+    padConfg0.r.PMode = 0;

+    padConfg0.r.GPIORxTxDis = 0x1;

+    GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);

+    *BoardId = (UINT8) (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00F0) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) | \

+                       (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00D0) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 1) | \

+                       (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00C8) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 2));

+

+    DEBUG ((DEBUG_INFO,  "BoardId from PMIC strap: %02X\n", *BoardId));

+    //

+    // Fab_ID0: PMIC_I2C_SDA

+    //

+    CommAndOffset = GetCommOffset (NORTHWEST, 0x0108);

+    padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);

+    padConfg0.r.PMode = 0;

+    padConfg0.r.GPIORxTxDis = 0x1;

+    GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);

+    //

+    // Set to Pull Up 20K

+    //

+    padConfg1.r.Term = 0xC;

+    GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);

+    //

+    // Fab_ID1: PMIC_I2C_SCL

+    //

+    CommAndOffset = GetCommOffset (NORTHWEST, 0x0100);

+    padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);

+    padConfg0.r.PMode = 0;

+    padConfg0.r.GPIORxTxDis = 0x1;

+    GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);

+    //

+    // Set to Pull Up 20K

+    //

+    padConfg1.r.Term = 0xC;

+    GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);

+    //

+    // Fab_ID2: PMIC_BCUDISW2

+    //

+    CommAndOffset = GetCommOffset (NORTHWEST, 0x00D8);

+    padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);

+    padConfg0.r.PMode = 0;

+    padConfg0.r.GPIORxTxDis = 0x1;

+    GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);

+    //

+    // Set to Pull Up 20K

+    //

+    padConfg1.r.Term = 0xC;

+    GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);

+    //

+    // Fab_ID3: PMIC_BCUDISCRIT

+    //

+    CommAndOffset = GetCommOffset (NORTHWEST, 0x00E0);

+    padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);

+    padConfg0.r.PMode = 0;

+    padConfg0.r.GPIORxTxDis = 0x1;

+    GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);

+    //

+    // Set to Pull Up 20K

+    //

+    padConfg1.r.Term = 0xC;

+    GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);

+

+    *FabId = (UINT8) (((GpioPadRead (GetCommOffset (NORTHWEST, 0x0108) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) | \

+                     (((GpioPadRead (GetCommOffset (NORTHWEST, 0x0100) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 1) | \

+                     (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00D8) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 2) | \

+                     (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00E0) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 3));

+

+    DEBUG ((EFI_D_INFO,  "FabId from PMIC strap: %02X\n", *FabId));

+  }

+

+  return EFI_SUCCESS;

+}

+

+

+EFI_STATUS

+EFIAPI

+GetIVIBoardIdFabId (

+  IN CONST EFI_PEI_SERVICES     **PeiServices,

+  OUT UINT8                     *BoardId,

+  OUT UINT8                     *FabId

+  )

+{

+  BXT_CONF_PAD0   padConfg0;

+  BXT_CONF_PAD1   padConfg1;

+  IN UINT32       CommAndOffset;

+

+  DEBUG ((DEBUG_INFO, "GetIVIBoardIdFabId++\n"));

+

+  //

+  // Board_ID0: GPIO_62

+  //

+  CommAndOffset = GetCommOffset (NORTH, 0x0190);

+  padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);

+  padConfg0.r.PMode = 0;

+  padConfg0.r.GPIORxTxDis = 0x1;

+  GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);

+  padConfg1.padCnf1 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET);

+  padConfg1.r.IOSTerm = 0x3; //Enable Pullup

+  padConfg1.r.Term = 0xC;    //20k wpu

+  GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);

+  //

+  // Board_ID1: GPIO_63

+  //

+  CommAndOffset = GetCommOffset (NORTH, 0x0198);

+  padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);

+  padConfg0.r.PMode = 0;

+  padConfg0.r.GPIORxTxDis = 0x1;

+  GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);

+  padConfg1.padCnf1 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET);

+  padConfg1.r.IOSTerm = 0x3; //Enable Pullup

+  padConfg1.r.Term = 0xC;    //20k wpu

+  GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);

+  //

+  // Board_ID2: GPIO_64

+  //

+  CommAndOffset = GetCommOffset (NORTH, 0x01A0);

+  padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);

+  padConfg0.r.PMode = 0;

+  padConfg0.r.GPIORxTxDis = 0x1;

+  GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);

+  padConfg1.padCnf1 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET);

+  padConfg1.r.IOSTerm = 0x3; //Enable Pullup

+  padConfg1.r.Term = 0xC;    //20k wpu

+  GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);

+  //

+  // Board_ID3: GPIO_65

+  //

+  CommAndOffset = GetCommOffset (NORTH, 0x01A8);

+  padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);

+  padConfg0.r.PMode = 0;

+  padConfg0.r.GPIORxTxDis = 0x1;

+  GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);

+  padConfg1.padCnf1 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET);

+  padConfg1.r.IOSTerm = 0x3; //Enable Pullup

+  padConfg1.r.Term = 0xC;    //20k wpu

+  GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);

+

+  *BoardId = (UINT8) (((GpioPadRead (GetCommOffset (NORTH, 0x0190) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) | \

+                     (((GpioPadRead (GetCommOffset (NORTH, 0x0198) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 1) | \

+                     (((GpioPadRead (GetCommOffset (NORTH, 0x01A0) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 2) | \

+                     (((GpioPadRead (GetCommOffset (NORTH, 0x01A8) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 3));

+

+  return EFI_SUCCESS;

+}

+

diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/PlatformId.h b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/PlatformId.h
new file mode 100644
index 0000000000..3999aaa726
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/PlatformId.h
@@ -0,0 +1,81 @@
+/** @file

+  Header file for the Platform ID code.

+

+  Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>

+

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php.

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+**/

+

+#ifndef __PLATFORM_ID_H__

+#define __PLATFORM_ID_H__

+

+//

+// Strap Fw Cfg ID define

+//

+#define IO_EXPANDER_I2C_BUS_NO   0x06

+#define IO_EXPANDER_SLAVE_ADDR   0x22

+#define IO_EXPANDER_INPUT_REG_0  0x00

+#define IO_EXPANDER_INPUT_REG_1  0x01

+#define IO_EXPANDER_INPUT_REG_2  0x02

+

+EFI_STATUS

+EFIAPI

+GetFwCfgId (

+  IN CONST EFI_PEI_SERVICES     **PeiServices,

+  OUT UINT8                     *FwCfgId

+  );

+

+EFI_STATUS

+EFIAPI

+GetBoardIdFabId (

+  IN CONST EFI_PEI_SERVICES     **PeiServices,

+  OUT UINT8                     *BoardId,

+  OUT UINT8                     *FabId

+  );

+

+EFI_STATUS

+EFIAPI

+GetEmbeddedBoardIdFabId (

+  IN CONST EFI_PEI_SERVICES     **PeiServices,

+  OUT UINT8                     *BoardId,

+  OUT UINT8                     *FabId

+  );

+

+EFI_STATUS

+EFIAPI

+GetIVIBoardIdFabId (

+  IN CONST EFI_PEI_SERVICES     **PeiServices,

+  OUT UINT8                     *BoardId,

+  OUT UINT8                     *FabId

+  );

+

+EFI_STATUS

+EFIAPI

+GetDockId (

+  IN CONST EFI_PEI_SERVICES     **PeiServices,

+  OUT UINT8                     *DockId

+  );

+

+EFI_STATUS

+EFIAPI

+GetOsSelPss (

+  IN CONST EFI_PEI_SERVICES     **PeiServices,

+  OUT UINT8                     *OsSelPss

+  );

+

+EFI_STATUS

+EFIAPI

+GetBomIdPss (

+  IN CONST EFI_PEI_SERVICES     **PeiServices,

+  OUT UINT8                     *BomIdPss

+  );

+

+#endif

+