diff options
| author | Guo Mang <mang.guo@intel.com> | 2017-02-16 11:24:18 +0800 |
|---|---|---|
| committer | Guo Mang <mang.guo@intel.com> | 2017-02-16 11:42:19 +0800 |
| commit | 5b487d3ffd763fa78550ac94e845c7414fbbbdd9 (patch) | |
| tree | 9852c3c79b9037cdc68539714d7362ffee52ce45 /Platform/BroxtonPlatformPkg/Board/LeafHill | |
| parent | bb93dfde8c07c08ddcff0b73f0d223c4309ec4e8 (diff) | |
| download | edk2-platforms-5b487d3ffd763fa78550ac94e845c7414fbbbdd9.tar.xz | |
Fix MRC restore issue
MCR parameter restored in the second time of boot, so the boot time is less than the first time of boot.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Reviewed-by: zwei4 <david.wei@intel.com>
Diffstat (limited to 'Platform/BroxtonPlatformPkg/Board/LeafHill')
| -rw-r--r-- | Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c | 17 | ||||
| -rw-r--r-- | Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitPreMem.inf | 1 |
2 files changed, 16 insertions, 2 deletions
diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c index 5af2faeae1..fe8ece0b88 100644 --- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c +++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c @@ -14,6 +14,7 @@ **/
#include "BoardInitMiscs.h"
+#include "MmrcData.h"
UPDATE_FSPM_UPD_FUNC mLhUpdateFspmUpdPtr = LhUpdateFspmUpd;
DRAM_CREATE_POLICY_DEFAULTS_FUNC mLhDramCreatePolicyDefaultsPtr = LhDramCreatePolicyDefaults;
@@ -29,6 +30,9 @@ LhUpdateFspmUpd ( EFI_PLATFORM_INFO_HOB *PlatformInfo = NULL;
DRAM_POLICY_PPI *DramPolicy;
EFI_STATUS Status;
+ MRC_NV_DATA_FRAME *MrcNvData;
+ MRC_PARAMS_SAVE_RESTORE *MrcParamsHob;
+ BOOT_VARIABLE_NV_DATA *BootVariableNvDataHob;
Status = (*PeiServices)->LocatePpi (
PeiServices,
@@ -64,11 +68,20 @@ LhUpdateFspmUpd ( FspUpdRgn->FspmConfig.InterleavedMode = DramPolicy->InterleavedMode;
FspUpdRgn->FspmConfig.MinRefRate2xEnable = DramPolicy->MinRefRate2xEnabled;
FspUpdRgn->FspmConfig.DualRankSupportEnable = DramPolicy->DualRankSupportEnabled;
- FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr;
- FspUpdRgn->FspmConfig.MrcBootDataPtr = (VOID *)(UINT32)DramPolicy->MrcBootDataPtr;
CopyMem (&(FspUpdRgn->FspmConfig.Ch0_RankEnable), &DramPolicy->ChDrp, sizeof (DramPolicy->ChDrp));
CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), &DramPolicy->ChSwizzle, sizeof (DramPolicy->ChSwizzle));
+
+ if (((VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr != 0) &&
+ ((VOID *)(UINT32)DramPolicy->MrcBootDataPtr != 0)) {
+ MrcNvData = (MRC_NV_DATA_FRAME *) AllocateZeroPool (sizeof (MRC_NV_DATA_FRAME));
+ MrcParamsHob = (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcTrainingDataPtr);
+ BootVariableNvDataHob = (BOOT_VARIABLE_NV_DATA*)((UINT32)DramPolicy->MrcBootDataPtr);
+ CopyMem(&(MrcNvData->MrcParamsSaveRestore), MrcParamsHob, sizeof (MRC_PARAMS_SAVE_RESTORE));
+ CopyMem(&(MrcNvData->BootVariableNvData), BootVariableNvDataHob, sizeof (BOOT_VARIABLE_NV_DATA));
+ FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)MrcNvData;
+ }
+
}
//
// override RankEnable settings for Minnow
diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitPreMem.inf b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitPreMem.inf index c1708397eb..c526bc2c09 100644 --- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitPreMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitPreMem.inf @@ -39,6 +39,7 @@ IntelFsp2Pkg/IntelFsp2Pkg.dec
BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ Silicon\BroxtonSoC\BroxtonSiPkg\NorthCluster\MemoryInit\MemoryInit.dec
[Pcd]
gPlatformModuleTokenSpaceGuid.PcdBoardId
|