diff options
| author | zwei4 <david.wei@intel.com> | 2017-07-17 10:32:23 +0800 |
|---|---|---|
| committer | zwei4 <david.wei@intel.com> | 2017-07-17 10:32:23 +0800 |
| commit | aabfb97f0734bb9ba27c3dd2f36503af9c672db2 (patch) | |
| tree | c5230bfee2915407888621ba3ebcfc39e2d12ca3 /Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem | |
| parent | 3bfaf23e95c68881bcbbfedececdece4cdff95f8 (diff) | |
| download | edk2-platforms-aabfb97f0734bb9ba27c3dd2f36503af9c672db2.tar.xz | |
WIFI Pin Setting
Configure GPIO pins of on-board WIFI.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david.wei@intel.com>
Diffstat (limited to 'Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem')
| -rw-r--r-- | Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h index 1bf848995a..77d4090267 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h @@ -73,7 +73,7 @@ BXT_GPIO_PAD_INIT mMinnow3_GpioInitData_N[] = BXT_GPIO_PAD_CONF(L"GPIO_7", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, SAME, GPIO_PADBAR+0x0038, NORTH),//Mux with DISP1_TOUCH_INT_N based on the SW3 switch
BXT_GPIO_PAD_CONF(L"GPIO_8", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, SAME, GPIO_PADBAR+0x0040, NORTH),//Mux with DISP1_TOUCH_RST_N based on the SW3 switch
BXT_GPIO_PAD_CONF(L"GPIO_9", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0048, NORTH),//Feature: LB
- BXT_GPIO_PAD_CONF(L"GPIO_10", M0 , GPO , GPIO_D , HI , Level , Wake_Enabled , P_20K_L, NA, NA, TxDRxE , NA, GPIO_PADBAR+0x0050, NORTH),//Feature: LB
+ BXT_GPIO_PAD_CONF(L"GPIO_10", M0 , GPO , GPIO_D , LO , Level , Wake_Enabled , P_20K_L, NA, NA, NA , NA, GPIO_PADBAR+0x0050, NORTH),//Feature: LB
BXT_GPIO_PAD_CONF(L"GPIO_11", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0058, NORTH),//Feature: LB
BXT_GPIO_PAD_CONF(L"GPIO_12", M1 , NA , NA , NA , NA , Wake_Enabled , P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0060, NORTH),//Feature: LB
BXT_GPIO_PAD_CONF(L"GPIO_13", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0068, NORTH),//Feature: LB
@@ -259,7 +259,7 @@ BXT_GPIO_PAD_INIT mMinnow3_GpioInitData_W [] = BXT_GPIO_PAD_CONF(L"GPIO_151 ISH_GPIO_5", M0 , GPO ,GPIO_D, HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA , GPIO_PADBAR+0x00A8, WEST),//Feature: RF_KILL_WWAN Net in Sch: NGFF_WWAN_RF_KILL_1P8_N
BXT_GPIO_PAD_CONF(L"GPIO_152 ISH_GPIO_6", M2 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA , GPIO_PADBAR+0x00B0, WEST),//Feature: AVS_I2S5_SDI
BXT_GPIO_PAD_CONF(L"GPIO_153 ISH_GPIO_7", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x00B8, WEST),
- BXT_GPIO_PAD_CONF(L"GPIO_154 ISH_GPIO_8", M0 , GPO ,GPIO_D, HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA , GPIO_PADBAR+0x00C0, WEST),//Feature: BT_Disable Net in Sch: BT_DISABLE2_1P8_N
+ BXT_GPIO_PAD_CONF(L"GPIO_154 ISH_GPIO_8", M0 , GPO ,GPIO_D, LO , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA , GPIO_PADBAR+0x00C0, WEST),//Feature: BT_Disable Net in Sch: BT_DISABLE2_1P8_N
BXT_GPIO_PAD_CONF(L"GPIO_155 ISH_GPIO_9", M2 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, SAME, GPIO_PADBAR+0x00C8, WEST),//CG2000 PDB: If PDB = 0: power-down; If PDB = 1: power-up, it is the same in ISH/LPSS mode
BXT_GPIO_PAD_CONF(L"GPIO_209 PCIE_CLKREQ0_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_NONE, NA , NA, HizRx0I, EnPd, GPIO_PADBAR+0x00D0, WEST),
BXT_GPIO_PAD_CONF(L"GPIO_210 PCIE_CLKREQ1_B", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, EnPd, GPIO_PADBAR+0x00D8, WEST),
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