diff options
author | Guo Mang <mang.guo@intel.com> | 2017-07-28 14:51:13 +0800 |
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committer | Guo Mang <mang.guo@intel.com> | 2017-07-28 14:51:13 +0800 |
commit | e094e85fbd2e10e6635f07f4c4624354bef5f1f9 (patch) | |
tree | 07f2e6f26e73a01970bb340cb248d07303ad366b /Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem | |
parent | 9d76578cf4304e42b1f5fee7d38d351a9a9b38e9 (diff) | |
download | edk2-platforms-e094e85fbd2e10e6635f07f4c4624354bef5f1f9.tar.xz |
Integrate MR3 FSP
Change code to integrate MR3 FSP.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Guo Mang <mang.guo@intel.com>
Diffstat (limited to 'Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem')
-rw-r--r-- | Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c index 7e0b525608..0c5307811d 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c @@ -30,7 +30,8 @@ Mb3UpdateFspmUpd ( EFI_PLATFORM_INFO_HOB *PlatformInfo = NULL;
DRAM_POLICY_PPI *DramPolicy;
EFI_STATUS Status;
- MRC_NV_DATA_FRAME *MrcNvData;
+ MRC_PARAMS_SAVE_RESTORE *MrcNvData;
+ BOOT_VARIABLE_NV_DATA *BootVariableNvData;
MRC_PARAMS_SAVE_RESTORE *MrcParamsHob;
BOOT_VARIABLE_NV_DATA *BootVariableNvDataHob;
@@ -74,12 +75,17 @@ Mb3UpdateFspmUpd ( if (((VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr != 0) &&
((VOID *)(UINT32)DramPolicy->MrcBootDataPtr != 0)) {
- MrcNvData = (MRC_NV_DATA_FRAME *) AllocateZeroPool (sizeof (MRC_NV_DATA_FRAME));
- MrcParamsHob = (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcTrainingDataPtr);
+ DEBUG ((DEBUG_INFO, "UpdateFspmUpd - NvsBufferPtr\n"));
+ MrcNvData = (MRC_PARAMS_SAVE_RESTORE *) AllocateZeroPool (sizeof (MRC_PARAMS_SAVE_RESTORE));
+ BootVariableNvData = (BOOT_VARIABLE_NV_DATA *) AllocateZeroPool (sizeof (BOOT_VARIABLE_NV_DATA));
+
+ MrcParamsHob = (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcTrainingDataPtr);
BootVariableNvDataHob = (BOOT_VARIABLE_NV_DATA*)((UINT32)DramPolicy->MrcBootDataPtr);
- CopyMem(&(MrcNvData->MrcParamsSaveRestore), MrcParamsHob, sizeof (MRC_PARAMS_SAVE_RESTORE));
- CopyMem(&(MrcNvData->BootVariableNvData), BootVariableNvDataHob, sizeof (BOOT_VARIABLE_NV_DATA));
- FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)MrcNvData;
+
+ CopyMem(MrcNvData, MrcParamsHob, sizeof (MRC_PARAMS_SAVE_RESTORE));
+ CopyMem(BootVariableNvData, BootVariableNvDataHob, sizeof (BOOT_VARIABLE_NV_DATA));
+ FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)MrcNvData;
+ FspUpdRgn->FspmConfig.VariableNvsBufferPtr = (VOID *)(UINT32)BootVariableNvData;
}
}
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