diff options
| author | Guo Mang <mang.guo@intel.com> | 2017-02-08 18:21:03 +0800 |
|---|---|---|
| committer | Guo Mang <mang.guo@intel.com> | 2017-05-09 13:03:09 +0800 |
| commit | 6b9f32df9d318a159493449e6e718d10fa6243e2 (patch) | |
| tree | 3c28e8bf4bbf87c9f9f670296b79c13377813062 /Platform/BroxtonPlatformPkg/Board/MinnowBoard3 | |
| parent | 61a97ff3e685984af81eaf95481820adbd43e15f (diff) | |
| download | edk2-platforms-6b9f32df9d318a159493449e6e718d10fa6243e2.tar.xz | |
Change MRC parameter
These code cause HDMI cable of some vendor couldn't work.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Reviewed-by: lushifex <shifeix.a.lu@intel.com>
Diffstat (limited to 'Platform/BroxtonPlatformPkg/Board/MinnowBoard3')
| -rw-r--r-- | Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c | 17 | ||||
| -rw-r--r-- | Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf | 1 |
2 files changed, 2 insertions, 16 deletions
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c index 9e535ca8e9..ece8a881a0 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c @@ -14,7 +14,6 @@ **/
#include "BoardInitMiscs.h"
-#include "MmrcData.h"
UPDATE_FSPM_UPD_FUNC mMb3UpdateFspmUpdPtr = Mb3UpdateFspmUpd;
DRAM_CREATE_POLICY_DEFAULTS_FUNC mMb3DramCreatePolicyDefaultsPtr = Mb3DramCreatePolicyDefaults;
@@ -30,9 +29,6 @@ Mb3UpdateFspmUpd ( EFI_PLATFORM_INFO_HOB *PlatformInfo = NULL;
DRAM_POLICY_PPI *DramPolicy;
EFI_STATUS Status;
- MRC_NV_DATA_FRAME *MrcNvData;
- MRC_PARAMS_SAVE_RESTORE *MrcParamsHob;
- BOOT_VARIABLE_NV_DATA *BootVariableNvDataHob;
Status = (*PeiServices)->LocatePpi (
PeiServices,
@@ -68,20 +64,11 @@ Mb3UpdateFspmUpd ( FspUpdRgn->FspmConfig.InterleavedMode = DramPolicy->InterleavedMode;
FspUpdRgn->FspmConfig.MinRefRate2xEnable = DramPolicy->MinRefRate2xEnabled;
FspUpdRgn->FspmConfig.DualRankSupportEnable = DramPolicy->DualRankSupportEnabled;
+ FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr;
+ FspUpdRgn->FspmConfig.MrcBootDataPtr = (VOID *)(UINT32)DramPolicy->MrcBootDataPtr;
CopyMem (&(FspUpdRgn->FspmConfig.Ch0_RankEnable), &DramPolicy->ChDrp, sizeof(DramPolicy->ChDrp));
CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), &DramPolicy->ChSwizzle, sizeof (DramPolicy->ChSwizzle));
-
- if (((VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr != 0) &&
- ((VOID *)(UINT32)DramPolicy->MrcBootDataPtr != 0)) {
- MrcNvData = (MRC_NV_DATA_FRAME *) AllocateZeroPool (sizeof (MRC_NV_DATA_FRAME));
- MrcParamsHob = (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcTrainingDataPtr);
- BootVariableNvDataHob = (BOOT_VARIABLE_NV_DATA*)((UINT32)DramPolicy->MrcBootDataPtr);
- CopyMem(&(MrcNvData->MrcParamsSaveRestore), MrcParamsHob, sizeof (MRC_PARAMS_SAVE_RESTORE));
- CopyMem(&(MrcNvData->BootVariableNvData), BootVariableNvDataHob, sizeof (BOOT_VARIABLE_NV_DATA));
- FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)MrcNvData;
- }
-
}
//
// override RankEnable settings for Minnow
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf index 9135fb8612..f64ab8fe5c 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf @@ -39,7 +39,6 @@ IntelFsp2Pkg/IntelFsp2Pkg.dec
BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
- Silicon\BroxtonSoC\BroxtonSiPkg\NorthCluster\MemoryInit\MemoryInit.dec
[Pcd]
gPlatformModuleTokenSpaceGuid.PcdBoardId
|