diff options
| author | Guo Mang <mang.guo@intel.com> | 2016-12-23 13:37:43 +0800 |
|---|---|---|
| committer | Guo Mang <mang.guo@intel.com> | 2016-12-26 19:15:14 +0800 |
| commit | a56cf5fd57d9853b8ee62c8a5dc6c1ca374d3c15 (patch) | |
| tree | 2268e7fa8aac2ecf28729e08481be069cdafa0d8 /Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3 | |
| parent | 3532120b547da58720f7e23a11863e4868a6c0b7 (diff) | |
| download | edk2-platforms-a56cf5fd57d9853b8ee62c8a5dc6c1ca374d3c15.tar.xz | |
BroxtonPlatformPkg: Add AcpiTablesPCAT
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Diffstat (limited to 'Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3')
6 files changed, 1613 insertions, 0 deletions
diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtPcie.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtPcie.asl new file mode 100644 index 0000000000..82465f0a59 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtPcie.asl @@ -0,0 +1,312 @@ +/** @file
+ ACPI RTD3 SSDT table for BXT PCIe
+
+ Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Name(WKEN, 0)
+
+ Method(_S0W, 0)
+ {
+ /// This method returns the lowest D-state supported by PCIe root port during S0 state
+
+ ///- PMEs can be generated from D3Cold for ULT
+ Return(4)
+
+ /** @defgroup pcie_s0W PCIE _S0W **/
+ } // End _S0W
+
+
+ Method(_DSW, 3)
+ {
+ /// This method is used to enable/disable wake from PCIe (WKEN)
+ If (Arg1) { /// If entering Sx, need to disable WAKE# from generating runtime PME
+ Store(0, WKEN)
+ } Else { /// If Staying in S0
+ If (LAnd(Arg0, Arg2)) {
+ ///- Check if Exiting D0 and arming for wake
+ ///- Set PME
+ Store(1, WKEN)
+ } Else { ///- Disable runtime PME, either because staying in D0 or disabling wake
+ Store(0, WKEN)
+ }
+ }
+
+ /** @defgroup pcie_dsw PCIE _DSW **/
+ } // End _DSW
+
+
+ PowerResource(PXP, 0, 0)
+ {
+ /// Define the PowerResource for PCIe slot
+ /// Method: _STA(), _ON(), _OFF()
+ /** @defgroup pcie_pxp PCIE Power Resource **/
+
+ Method(_STA, 0)
+ {
+ /// Returns the status of PCIe slot core power
+
+ // detect power pin status
+ if (LNotEqual(DeRefOf(Index(PWRG, 0)),0)) {
+ if (LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode
+ if (LEqual(\_SB.GGOV(DeRefOf(Index(PWRG, 2))),DeRefOf(Index(PWRG, 3)))) {
+ Return (1)
+ } Else {
+ Return (0)
+ }
+ } // GPIO mode
+ }
+ // detect reset pin status
+ if (LNotEqual(DeRefOf(Index(RSTG, 0)),0)) {
+ if (LEqual(DeRefOf(Index(RSTG, 0)),1)) { // GPIO mode
+ if (LEqual(\_SB.GGOV(DeRefOf(Index(RSTG, 2))),DeRefOf(Index(RSTG, 3)))) {
+ Return (1)
+ } Else {
+ Return (0)
+ }
+ } // GPIO mode
+ }
+ Return (0)
+ } /** @defgroup pcie_sta PCIE _STA method **/
+
+ Method(_ON,0,Serialized) /// Turn on core power to PCIe Slot
+ {
+ Name(PCIA, 0)
+ //
+ // Windows will call _ON for all devices,regardless
+ // of the device enable state.
+ // We need to exit when the device is not present
+ // to prevent driving power to the device.
+ //
+ if (LEqual(SLOT, 1)) {
+ ShiftRight(RPA1, 1, PCIA)
+ Or(0xE0000000, PCIA, PCIA)
+ PON(PCIA)
+ } elseif(LEqual(SLOT, 2)) {
+ ShiftRight(RPA2, 1, PCIA)
+ Or(0xE0000000, PCIA, PCIA)
+ PON(PCIA)
+ } elseif(LEqual(SLOT, 3)) {
+ ShiftRight(RPA3, 1, PCIA)
+ Or(0xE0000000, PCIA, PCIA)
+ PON(PCIA)
+ } elseif(LEqual(SLOT, 4)) {
+ ShiftRight(RPA4, 1, PCIA)
+ Or(0xE0000000, PCIA, PCIA)
+ PON(PCIA)
+ } elseif(LEqual(SLOT, 5)) {
+ ShiftRight(RPA5, 1, PCIA)
+ Or(0xE0000000, PCIA, PCIA)
+ PON(PCIA)
+ } elseif(LEqual(SLOT, 6)) {
+ ShiftRight(RPA6, 1, PCIA)
+ Or(0xE0000000, PCIA, PCIA)
+ PON(PCIA)
+ }
+ }
+
+ Method(PON, 1, Serialized) {
+ OperationRegion(PX02,SystemMemory, Arg0,0x380)
+ Field(PX02,AnyAcc, NoLock, Preserve)
+ {
+ Offset(0),
+ VD02, 32,
+ Offset(0x50), // LCTL - Link Control Register
+ L0SE, 1, // 0, L0s Entry Enabled
+ , 3,
+ LDIS, 1,
+ Offset(0x52), // LSTS - Link Status Register
+ , 13,
+ LASX, 1, // 0, Link Active Status
+ Offset(0xE2), // RPPGEN - Root Port Power Gating Enable
+ , 2,
+ L23E, 1, // 2, L23_Rdy Entry Request (L23ER)
+ L23R, 1, // 3, L23_Rdy to Detect Transition (L23R2DT)
+ Offset(0xF4), // BLKPLLEN
+ , 10,
+ BPLL, 1,
+ Offset(0x324),
+ , 3,
+ LEDM, 1, // PCIEDBG.DMIL1EDM
+ Offset(0x338),
+ , 26,
+ BDQA, 1 // BLKDQDA
+ }
+ /// Turn ON Power for PCIe Slot
+ if (LNotEqual(DeRefOf(Index(WAKG, 0)),0)) { // if power gating enabled
+ if (LEqual(DeRefOf(Index(WAKG, 0)),1)) { // GPIO mode
+ \_SB.SGOV(DeRefOf(Index(WAKG, 2)),DeRefOf(Index(WAKG, 3)))
+ // \_SB.SHPO(DeRefOf(Index(WAKG, 2)), 0) // set gpio ownership to ACPI(0=ACPI mode, 1=GPIO mode)
+ Store(\_SB.GPC0(DeRefOf(Index(WAKG, 2))), Local1)
+ Or(Local1, 0x400000, Local1)
+ And(Local1, 0xFFFFFBFF, Local1)
+ \_SB.SPC0(DeRefOf(Index(WAKG, 2)), Local1)
+ }
+ }
+
+ If (LEqual(DeRefOf(Index(SCLK,0)), 1)) {
+ Store(\_SB.GPC0(DeRefOf(Index(SCLK,1))), Local1)
+ And(Local1, 0xFFBFFFFF, Local1)
+ \_SB.SPC0(DeRefOf(Index(SCLK,1)), Local1)
+ }
+
+ \_SB.SGOV(DeRefOf(Index(RSTG, 2)),DeRefOf(Index(RSTG, 3)))
+
+ Store(0, BDQA) // Set BLKDQDA to 0
+ Store(0, BPLL) // Set BLKPLLEN to 0
+
+ /// Set L23_Rdy to Detect Transition (L23R2DT)
+ Store(1, L23R)
+ Sleep(16)
+ Store(0, Local0)
+ /// Wait up to 12 ms for transition to Detect
+ While(L23R) {
+ If(Lgreater(Local0, 4)) // Debug - Wait for 5 ms
+ {
+ Break
+ }
+ Sleep(16)
+ Increment(Local0)
+ }
+ }
+
+ Method(_OFF,0,Serialized) /// Turn off core power to PCIe Slot
+ {
+ Name(PCIA, 0)
+
+ Switch(ToInteger(SLOT)) {
+ Case(1) {
+ ShiftRight(RPA1, 1, PCIA)
+ Or(0xE0000000, PCIA, PCIA)
+ }
+ Case(2) {
+ ShiftRight(RPA2, 1, PCIA)
+ Or(0xE0000000, PCIA, PCIA)
+ }
+ Case(3) {
+ ShiftRight(RPA3, 1, PCIA)
+ Or(0xE0000000, PCIA, PCIA)
+ }
+ Case(4) {
+ ShiftRight(RPA4, 1, PCIA)
+ Or(0xE0000000, PCIA, PCIA)
+ }
+ Case(5) {
+ ShiftRight(RPA5, 1, PCIA)
+ Or(0xE0000000, PCIA, PCIA)
+ }
+ Case(6) {
+ ShiftRight(RPA6, 1, PCIA)
+ Or(0xE0000000, PCIA, PCIA)
+ }
+ Default {
+ }
+ }
+
+ // Dynamic Opregion needed to access registers when the controller is in D3 cold
+ OperationRegion(PX02,SystemMemory,PCIA,0x380)
+ Field(PX02,AnyAcc, NoLock, Preserve)
+ {
+ Offset(0x50), // LCTL - Link Control Register
+ L0SE, 1, // 0, L0s Entry Enabled
+ , 3,
+ LDIS, 1,
+ Offset(0xE2), // RPPGEN - Root Port Power Gating Enable
+ , 2,
+ L23E, 1, // 2, L23_Rdy Entry Request (L23ER)
+ L23R, 1, // 3, L23_Rdy to Detect Transition (L23R2DT)
+ Offset(0xF4), // BLKPLLEN
+ , 10,
+ BPLL, 1,
+ Offset(0x324),
+ , 3,
+ LEDM, 1, // PCIEDBG.DMIL1EDM
+ Offset(0x338),
+ , 26,
+ BDQA, 1 // BLKDQDA
+ }
+ /// Set L23_Rdy Entry Request (L23ER)
+ Store(1, L23E)
+ Sleep(16)
+ Store(0, Local0)
+ While(L23E) {
+ If (Lgreater(Local0, 4)) {
+ /// Debug - Wait for 5 ms
+ Break
+ }
+ Sleep(16)
+ Increment(Local0)
+ }
+
+ Store(1, BDQA) // Set BLKDQDA to 1
+ Store(1, BPLL) // Set BLKPLLEN to 1
+
+ if (LNotEqual(DeRefOf(Index(WAKG, 0)),0)) {
+ // if power gating enabled
+ if (LEqual(DeRefOf(Index(WAKG, 0)),1)) {
+ // GPIO mode
+ Store(\_SB.GPC0(DeRefOf(Index(WAKG, 2))), Local1)
+ Or(Local1, 0x400, Local1)
+ And(Local1, 0xFFBFFFFF, Local1)
+ \_SB.SPC0(DeRefOf(Index(WAKG, 2)), Local1)
+ }
+ }
+
+ /// Assert Reset Pin
+ if (LNotEqual(DeRefOf(Index(RSTG, 0)),0)) {
+ // if reset pin enabled
+ if (LEqual(DeRefOf(Index(RSTG, 0)),1)) {
+ // GPIO mode
+ \_SB.SGOV(DeRefOf(Index(RSTG, 2)),Xor(DeRefOf(Index(RSTG, 3)),1))
+ }
+ }
+
+
+ /// assert CLK_REQ MSK
+ if (LEqual(DeRefOf(Index(SCLK, 0)),1)) {
+ // if power gating enabled
+ Store(\_SB.GPC0(DeRefOf(Index(SCLK, 1))), Local1)
+ Or(Local1, 0x400000, Local1)
+ \_SB.SPC0(DeRefOf(Index(SCLK, 1)), Local1)
+ }
+
+ /** @defgroup pcie_off PCIE _OFF method **/
+ } // End of Method_OFF
+ } // End PXP
+
+ Name(_PR0, Package(){PXP})
+ Name(_PR3, Package(){PXP})
+
+ //
+ // _SxW, in Sx, the lowest power state supported to wake up the system
+ // _SxD, in Sx, the highest power state supported by the device
+ // If OSPM supports _PR3 (_OSC, Arg3[2]), 3 represents D3hot; 4 represents D3cold, otherwise 3 represents D3.
+ //
+
+ Method (_S3D, 0, Serialized)
+ {
+ Return (0x2)
+ }
+ Method (_S3W, 0, Serialized)
+ {
+ Return (0x3)
+ }
+ Method (_S4D, 0, Serialized)
+ {
+ Return (0x2)
+ }
+ Method (_S4W, 0, Serialized)
+ {
+ Return (0x3)
+ }
+
+
diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtSata.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtSata.asl new file mode 100644 index 0000000000..f6b6f15659 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtSata.asl @@ -0,0 +1,216 @@ +/** @file
+ ACPI RTD3 SSDT table for BXT SATA
+
+ Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ Method(_DSW, 3, Serialized)
+ {
+ }
+
+ /// _S0W method returns the lowest D-state can be supported in state S0.
+ Method(_S0W, 0)
+ {
+ Return(4) // return 4 (D3cold)
+ } // End _S0W
+
+ Method(_PR0) {
+ If (LAnd(LAnd(LAnd(And(RCG0, 0x01), 0x01), LGreaterEqual(\OSYS, 2012)), LEqual(PORT, 0))) {
+ // Return ODPR for ZPODD
+ Return(Package(){ODPR})
+ } ElseIf (LAnd(LGreaterEqual(\OSYS, 2015), LEqual(\EMOD, 1))) {
+ If (CondRefOf(\_SB.MODS)) {
+ Return(Package(){\_SB.MODS})
+ }
+ } Else {
+ If (CondRefOf(SPPR)) {
+ Return(Package(){SPPR})
+ }
+ }
+ Return(Package() {})
+ }
+ Method(_PR3) {
+ If (LAnd(LAnd(LAnd(And(RCG0, 0x01), 0x01), LGreaterEqual(\OSYS, 2012)), LEqual(PORT, 0))) {
+ // Return ODPR for ZPODD
+ Return(Package(){ODPR})
+ } ElseIf (LAnd(LGreaterEqual(\OSYS, 2015), LEqual(\EMOD, 1))) {
+ If (CondRefOf(\_SB.MODS)) {
+ Return(Package(){\_SB.MODS})
+ }
+ } Else {
+ If (CondRefOf(SPPR)) {
+ Return(Package(){SPPR})
+ }
+ }
+ Return(Package() {})
+ }
+
+ PowerResource(SPPR, 0, 0)
+ {
+ Method(_STA)
+ {
+ If (LEqual(\EMOD, 1)) {
+ Return(0x01)
+ } Else {
+ Return(SPSA())
+ }
+ }
+
+ Method(_ON) {
+ If (LEqual(\EMOD, 1)) {
+ // Do nothing
+ } Else {
+ SPON() // _ON Method
+ Sleep(16) // Delay for power ramp.
+ }
+ }
+
+ Method(_OFF) {
+ If (LEqual(\EMOD, 1)) {
+ // Do nothing
+ } Else {
+ SPOF()
+ }
+ }
+ } // end SPPR
+
+ Name(OFTM, Zero) /// OFTM: Time returned by Timer() when the Power resource was turned OFF
+ Method(SPSA) {
+
+ // check power control enable
+ If (LNotEqual(DeRefOf(Index(PWRG, 0)), 0)) {
+ // read power pin status
+ If (LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode
+ if (LEqual(\_SB.GGOV(DeRefOf(Index(PWRG, 2))), DeRefOf(Index(PWRG, 3)))) {
+ Return(0x01)
+ } Else {
+ Return(0x00)
+ }
+ }
+ }
+ Return(0x00) // disabled
+ } /// @defgroup sata_prt1_sta SATA Port 1 PowerResource _STA Method
+
+ Method(SPON, 0) {
+ If (LNotEqual(^OFTM, Zero)) { /// if OFTM != 0 => Disk was turned OFF by asl
+ Divide(Subtract(Timer(), ^OFTM), 10000, , Local0) ///- Store Elapsed time in ms
+ Store(Zero, ^OFTM) ///- Reset OFTM to zero to indicate minimum 50ms requirement does not apply when _ON called next time
+ If (LLess(Local0, 50)) ///- Do not sleep if already past the delay requirement
+ {
+ Sleep(Subtract(50, Local0)) ///- Sleep 50ms - time elapsed
+ }
+ }
+ // drive power pin "ON"
+ if (LNotEqual(DeRefOf(Index(PWRG, 0)),0)) { // if power gating enabled
+ if (LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode
+ \_SB.SGOV(DeRefOf(Index(PWRG, 2)),DeRefOf(Index(PWRG, 3)))
+ }
+ }
+ }
+
+ Method(SPOF, 0) {
+
+ Add(\_SB.PCI0.SATA.MBR6, PBAR, Local0)
+ /// if S0Ix enabled
+ If (LEqual(S0ID, 1)) {
+ OperationRegion(PSTS, SystemMemory, Local0, 0x18)
+ Field(PSTS, DWordAcc, NoLock, Preserve)
+ {
+ Offset(0x0),
+ CMST, 1, //PxCMD.ST
+ CSUD, 1, //PxCMD.SUD
+ , 2,
+ CFRE, 1, //PxCMD.FRE
+ Offset(0x10),
+ SDET, 4, //PxSSTS.DET
+ Offset(0x14),
+ CDET, 4 //PxSCTL.DET
+ }
+
+ // Execute offline flow only if Device detected and Phy not offline
+ If (LOr(LEqual(SDET, 1), LEqual(SDET, 3))) {
+
+ ///- Clear ST (PxCMD.ST)
+ Store(0, CMST) // PBAR[0]
+ ///- Clear FRE
+ Store(0, CFRE) // PBAR[4]
+ ///- Clear SUD (PxCMD.SUD)
+ Store(0, CSUD) // PBAR[1]
+ ///- Set DET to 4 (PxSCTL.DET)
+ Store(4, CDET) // PBAR+0x14[3:0]
+ Sleep(16)
+ ///- Wait until PxSSTS.DET == 4
+ While(LNotEqual(SDET, 4)){
+ Sleep(16)
+ }
+ }
+ } // if S0Ix enabled
+ // drive power pin "OFF"
+ If (LNotEqual(DeRefOf(Index(PWRG, 0)),0)) { // if power gating enabled
+ if (LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode
+ \_SB.SGOV(DeRefOf(Index(PWRG, 2)),Xor(DeRefOf(Index(PWRG, 3)),1))
+ }
+ }
+
+ Store(Timer(), ^OFTM) /// Store time when Disk turned OFF(non-zero OFTM indicate minimum 50ms requirement does apply when _ON called next time)
+ } // end _OFF
+
+ //
+ // Power Resource for RTD3 ZPODD
+ //
+ PowerResource(ODPR, 0, 0)
+ {
+ Method(_STA)
+ {
+ Return(ODSA())
+ }
+
+ Method(_ON)
+ {
+ ODON() // _ON Method
+ Sleep(800) // Delay for power ramp.
+ }
+
+ Method(_OFF)
+ {
+ ODOF() // _OFF Method
+ }
+
+ } // end PZPR
+
+ Method(ODSA)
+ {
+ // check power control enable
+ // read power pin status
+ If (LEqual(\_SB.GGOV(N_GPIO_22), 0x01)) {
+ Return(0x01)
+ } Else {
+ Return(0x00)
+ }
+ }
+
+ Method(ODON, 0)
+ {
+ // drive power pin "ON"
+ If (LAnd(LAnd(LAnd(And(RCG0, 0x01), 0x01), LGreaterEqual(\OSYS, 2012)), LEqual(PORT, 0))) {
+ Store (1, \_SB.GPO0.ODPW)
+ }
+ }
+
+ Method(ODOF, 0)
+ {
+ // drive power pin "OFF"
+ If (LAnd(LAnd(LAnd(And(RCG0, 0x01), 0x01), LGreaterEqual(\OSYS, 2012)), LEqual(PORT, 0))) {
+ Store (0, \_SB.GPO0.ODPW)
+ }
+ }
+
diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtUsb.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtUsb.asl new file mode 100644 index 0000000000..f4e168f6b3 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtUsb.asl @@ -0,0 +1,63 @@ +/** @file
+ Power resource and wake capability for USB ports
+
+ Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ //
+ // Define _PR0, _PR3 PowerResource Package
+ //
+ Name (_PR0, Package(){UPPR})
+ Name (_PR3, Package(){UPPR})
+
+ PowerResource(UPPR, 0, 0)
+ {
+ Method(_STA)
+ {
+ Return(0x01)
+ }
+
+ Method(_ON)
+ {
+ }
+
+ Method(_OFF)
+ {
+ }
+ }
+
+ //
+ // _SxW, in Sx, the lowest power state supported to wake up the system
+ // _SxD, in Sx, the highest power state supported by the device
+ // If OSPM supports _PR3 (_OSC, Arg3[2]), 3 represents D3hot; 4 represents D3cold, otherwise 3 represents D3.
+ //
+ Method(_S0W, 0, Serialized)
+ {
+ Return(0x3) // return 3 (D3hot)
+ }
+ Method (_S3D, 0, Serialized)
+ {
+ Return (0x2)
+ }
+ Method (_S3W, 0, Serialized)
+ {
+ Return (0x3)
+ }
+ Method (_S4D, 0, Serialized)
+ {
+ Return (0x2)
+ }
+ Method (_S4W, 0, Serialized)
+ {
+ Return (0x3)
+ }
+
diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtUsbWwan.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtUsbWwan.asl new file mode 100644 index 0000000000..787d7cd704 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtUsbWwan.asl @@ -0,0 +1,90 @@ +/** @file
+ Power resource and wake capability for USB ports hosting WWAN module
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ // USB Port 3 power resource
+
+ PowerResource(PX03, 0, 0) {
+ Name(WOFF, 0) // Last OFF Time stamp (WOFF): The time stamp of the last power resource _OFF method evaluation
+
+ Method(_STA)
+ {
+ If (LEqual(\_SB.GGOV(NW_GPIO_78), 1)) {
+ Return(0x01)
+ } Else {
+ Return(0x00)
+ }
+ }
+
+ Method(_ON, 0) /// _ON Method
+ {
+ If (LNotEqual(^WOFF, Zero)) {
+ Divide(Subtract(Timer(), ^WOFF), 10000, , Local0) // Store Elapsed time in ms, ignore remainder
+ If (LLess(Local0,100)) { // If Elapsed time is less than 100ms
+ Sleep(Subtract(100,Local0)) // Sleep for the remaining time
+ }
+ }
+ \_SB.SGOV(NW_GPIO_78,1) // set power pin to high
+ \_SB.SGOV(NW_GPIO_117,1) // set reset pin to high
+ }
+
+ Method(_OFF, 0) /// _OFF Method
+ {
+ \_SB.SGOV(NW_GPIO_117,0) // set reset pin to low
+ \_SB.SGOV(NW_GPIO_78,0) // set power pin to low
+
+ Store(Timer(), ^WOFF) // Start OFF timer here.
+ }
+ } // End PX03
+
+ Name(_PR0,Package(){PX03}) // Power Resource required to support D0
+ Name(_PR2,Package(){PX03}) // Power Resource required to support D2
+ Name(_PR3,Package(){PX03}) // Power Resource required to support D3
+
+ //
+ // WWAN Modem device with the same power resource as its composite parent device
+ //
+ Device (MODM) {
+ Name(_ADR, 0x3)
+ Name(_PR0,Package(){PX03}) // Power Resource required to support D0
+ Name(_PR2,Package(){PX03}) // Power Resource required to support D2
+ Name(_PR3,Package(){PX03}) // Power Resource required to support D3
+ }
+
+ //
+ // _SxW, in Sx, the lowest power state supported to wake up the system
+ // _SxD, in Sx, the highest power state supported by the device
+ // If OSPM supports _PR3 (_OSC, Arg3[2]), 3 represents D3hot; 4 represents D3cold, otherwise 3 represents D3.
+ //
+ Method(_S0W, 0, Serialized)
+ {
+ Return(0x3) // return 3 (D3hot)
+ }
+ Method (_S3D, 0, Serialized)
+ {
+ Return (0x2)
+ }
+ Method (_S3W, 0, Serialized)
+ {
+ Return (0x3)
+ }
+ Method (_S4D, 0, Serialized)
+ {
+ Return (0x2)
+ }
+ Method (_S4W, 0, Serialized)
+ {
+ Return (0x3)
+ }
+
diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3Common.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3Common.asl new file mode 100644 index 0000000000..0e95dd8774 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3Common.asl @@ -0,0 +1,91 @@ +/** @file
+ ACPI RTD3 SSDT table
+
+ Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+External(\_SB.OSCO)
+External(\_SB.PCI0, DeviceObj)
+
+External(\_SB.PCI0.RP01, DeviceObj)
+External(\_SB.PCI0.RP02, DeviceObj)
+External(\_SB.PCI0.RP03, DeviceObj)
+External(\_SB.PCI0.RP04, DeviceObj)
+External(\_SB.PCI0.RP05, DeviceObj)
+External(\_SB.PCI0.RP06, DeviceObj)
+External(\_SB.PCI0.RP01.VDID)
+External(\_SB.PCI0.RP02.VDID)
+External(\_SB.PCI0.RP03.VDID)
+External(\_SB.PCI0.RP04.VDID)
+External(\_SB.PCI0.RP05.VDID)
+External(\_SB.PCI0.RP06.VDID)
+External(\_SB.PCI0.SATA, DeviceObj)
+External(\_SB.PCI0.SATA.PRT0, DeviceObj)
+External(\_SB.PCI0.SATA.PRT1, DeviceObj)
+
+External(\_SB.PCI0.XHC, DeviceObj)
+External(\_SB.PCI0.XHC.RHUB, DeviceObj)
+
+External(\_SB.PCI0.XHC.RHUB.HS01, DeviceObj)
+External(\_SB.PCI0.XHC.RHUB.HS02, DeviceObj)
+External(\_SB.PCI0.XHC.RHUB.HS03, DeviceObj)
+External(\_SB.PCI0.XHC.RHUB.HS04, DeviceObj)
+External(\_SB.PCI0.XHC.RHUB.HS05, DeviceObj)
+External(\_SB.PCI0.XHC.RHUB.HS06, DeviceObj)
+External(\_SB.PCI0.XHC.RHUB.HS07, DeviceObj)
+External(\_SB.PCI0.XHC.RHUB.HS08, DeviceObj)
+
+External(\_SB.PCI0.XHC.RHUB.SSP1, DeviceObj)
+External(\_SB.PCI0.XHC.RHUB.SSP2, DeviceObj)
+External(\_SB.PCI0.XHC.RHUB.SSP3, DeviceObj)
+External(\_SB.PCI0.XHC.RHUB.SSP4, DeviceObj)
+External(\_SB.PCI0.XHC.RHUB.SSP5, DeviceObj)
+External(\_SB.PCI0.XHC.RHUB.SSP6, DeviceObj)
+External(\_SB.PCI0.XHC.RHUB.SSP7, DeviceObj)
+
+External(\_SB.PCI0.XDCI, DeviceObj)
+
+External(\_SB.PCI0.SDHA, DeviceObj)
+External(\_SB.PCI0.SDIO, DeviceObj)
+
+External(\_SB.PCI0.PWM, DeviceObj)
+External(\_SB.PCI0.I2C0, DeviceObj)
+External(\_SB.PCI0.I2C1, DeviceObj)
+External(\_SB.PCI0.I2C2, DeviceObj)
+External(\_SB.PCI0.I2C3, DeviceObj)
+External(\_SB.PCI0.I2C4, DeviceObj)
+External(\_SB.PCI0.I2C5, DeviceObj)
+External(\_SB.PCI0.I2C6, DeviceObj)
+External(\_SB.PCI0.I2C7, DeviceObj)
+External(\_SB.PCI0.SPI1, DeviceObj)
+External(\_SB.PCI0.SPI2, DeviceObj)
+External(\_SB.PCI0.SPI3, DeviceObj)
+External(\_SB.PCI0.URT1, DeviceObj)
+External(\_SB.PCI0.URT2, DeviceObj)
+External(\_SB.PCI0.URT3, DeviceObj)
+External(\_SB.PCI0.URT4, DeviceObj)
+
+External(\GPRW, MethodObj)
+External(P8XH, MethodObj)
+External(XDST, IntObj)
+
+//
+// Externs common to ULT0RTD3.asl and FFRDRTD3.asl and exclude for BRRTD3.asl
+//
+
+// GPIO methods
+External(\_SB.GPC0, MethodObj)
+External(\_SB.SPC0, MethodObj)
+
+// IO expander methods
+// RTD3 devices and variables
+
diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/RvpRtd3.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/RvpRtd3.asl new file mode 100644 index 0000000000..6ce5b22afa --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/RvpRtd3.asl @@ -0,0 +1,841 @@ +/** @file
+ ACPI RTD3 SSDT table for APLK
+
+ Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+DefinitionBlock (
+ "Rtd3.aml",
+ "SSDT",
+ 2,
+ "AcpiRef",
+ "RVPRtd3",
+ 0x1000
+ )
+{
+External(RTD3, IntObj)
+External(EMOD, IntObj)
+External(RCG0, IntObj)
+External(RPA1, IntObj)
+External(RPA2, IntObj)
+External(RPA3, IntObj)
+External(RPA4, IntObj)
+External(RPA5, IntObj)
+External(RPA6, IntObj)
+External(\_SB.GPO0.AVBL, IntObj)
+External(\_SB.GPO0.ODPW, IntObj)
+External(\_SB.GGOV, MethodObj)
+External(\_SB.SGOV, MethodObj)
+External(OSYS)
+External(HGEN)
+External(S0ID)
+
+Include ("BxtPGpioDefine.asl")
+Include ("Rtd3Common.asl")
+
+//
+// PCIe root ports - START
+//
+ ///
+ /// PCIe RTD3 - SLOT#1
+ ///
+ Scope(\_SB.PCI0.RP01)
+ {
+ // reset pin = N_GPIO_13
+ // power pin = N_GPIO_17
+ // wake pin = SW_GPIO_207
+ // CLK_REQ = Mask Enable of Mapped CLKREQ# for CLKOUT_SRC2 (MSKCRQSRC2):
+ Name(SLOT, 1) // port #1
+
+ Name(RSTG, Package() {
+ 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander)
+ 0, // IOEX #
+ N_GPIO_13, // GPIO pad #/IOEX pin #
+ 1 // reset pin de-assert polarity
+ })
+ Name(PWRG, Package() {
+ 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander)
+ 0, // IOEX #
+ N_GPIO_17, // GPIO pad #/IOEX pin #
+ 1 // power on polarity
+ })
+ Name(WAKG, Package() {
+ 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander)
+ 0, // IOEX #
+ SW_GPIO_207, // MSKCRQSRC2
+ 0 // wake en polarity
+ })
+ Name(SCLK, Package() {
+ 0, // 0-disable, 1-enable
+ W_GPIO_211, // MSKCRQSRC2
+ 0 // assert polarity, ICC should be LOW-activated
+ })
+
+ Include("Rtd3BxtPcie.asl")
+ }
+
+ ///
+ /// PCIe RTD3 - SLOT#2
+ ///
+ Scope(\_SB.PCI0.RP02)
+ {
+ Name (PCA2, 0)
+ // reset pin = N_GPIO_15
+ // power pin = N_GPIO_17
+ // wake pin = SW_GPIO_208
+ // CLK_REQ = Mask Enable of Mapped CLKREQ# for CLKOUT_SRC1 (MSKCRQSRC1):
+ Name(SLOT, 2) // port #2
+
+ Name(RSTG, Package() {
+ 1, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander)
+ 0, // IOEX #
+ N_GPIO_15, // GPIO pad #/IOEX pin #
+ 1 // reset pin de-assert polarity
+ })
+ Name(PWRG, Package() {
+ 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander)
+ 0, // IOEX #
+ N_GPIO_17, // GPIO pad #/IOEX pin #
+ 1 // power on polarity
+ })
+ Name(WAKG, Package() {
+ 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander)
+ 0, // IOEX #
+ SW_GPIO_208, // GPIO pad #/IOEX pin #
+ 1 // wake en polarity
+ })
+ Name(SCLK, Package() {
+ 1, // 0-disable, 1-enable
+ W_GPIO_212, // MSKCRQSRC1
+ 0 // assert polarity, ICC should be LOW-activated
+ })
+
+ Include("Rtd3BxtPcie.asl")
+ }
+
+ ///
+ /// PCIe RTD3 - SLOT#3
+ ///
+ If (LEqual (HGEN, 0)) {
+ Scope(\_SB.PCI0.RP03)
+ {
+ Name (PCA3, 0)
+ // reset pin = W_GPIO_152
+ // power pin = N_GPIO_19
+ // wake pin = SW_GPIO_205
+ // CLK_REQ = W_GPIO_209
+ Name(SLOT, 3) // port #3
+
+ Name(RSTG, Package() {
+ 1, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander)
+ 0, // IOEX #
+ W_GPIO_152, // GPIO pad #/IOEX pin #
+ 1 // reset pin de-assert polarity
+ })
+ Name(PWRG, Package() {
+ 1, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander)
+ 0, // IOEX #
+ N_GPIO_19, // GPIO pad #/IOEX pin #
+ 1 // power on polarity
+ })
+ Name(WAKG, Package() {
+ 1, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander)
+ 0, // IOEX #
+ SW_GPIO_205, // GPIO pad #/IOEX pin #
+ 1 // wake en polarity
+ })
+ Name(SCLK, Package() {
+ 1, // 0-disable, 1-enable
+ W_GPIO_209, // MSKCRQSRCx
+ 0 // assert polarity, ICC should be LOW-activated
+ })
+ Include("Rtd3BxtPcie.asl")
+ }
+ }
+
+ ///
+ /// PCIe RTD3 - SLOT#4
+ ///
+ Scope(\_SB.PCI0.RP04)
+ {
+ Name (PCA4, 0)
+ // reset pin = none
+ // power pin = none
+ // wake pin = none
+ // CLK_REQ = Mask Enable of Mapped CLKREQ# for CLKOUT_SRC5 (MSKCRQSRC5)
+ Name(SLOT, 4) ///- Slot #4
+
+ Name(RSTG, Package() {
+ 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander)
+ 0, // IOEX #
+ 0, // GPIO pad #/IOEX pin #
+ 0 // reset pin de-assert polarity
+ })
+ Name(PWRG, Package() {
+ 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander)
+ 0, // IOEX #
+ 0, // GPIO pad #/IOEX pin #
+ 0 // power on polarity
+ })
+ Name(WAKG, Package() {
+ 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander)
+ 0, // IOEX #
+ 0, // GPIO pad #/IOEX pin #
+ 0 // wake en polarity
+ })
+ Name(SCLK, Package() {
+ 0, // 0-disable, 1-enable
+ 0, // MSKCRQSRC5
+ 0 // assert polarity, ICC should be LOW-activated
+ })
+
+ Include("Rtd3BxtPcie.asl")
+ }
+
+ ///
+ /// PCIe RTD3 - SLOT#5
+ ///
+ Scope(\_SB.PCI0.RP05)
+ {
+ Name (PCA5, 0)
+ // reset pin = none
+ // power pin = none
+ // wake pin = none
+ // CLK_REQ = Mask Enable of Mapped CLKREQ# for CLKOUT_SRC4 (MSKCRQSRC4)
+ Name(SLOT, 5) ///- port #5
+
+ Name(RSTG, Package() {
+ 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander)
+ 0, // IOEX #
+ 0, // GPIO pad #/IOEX pin #
+ 0 // reset pin de-assert polarity
+ })
+ Name(PWRG, Package() {
+ 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander)
+ 0, // IOEX #
+ 0, // GPIO pad #/IOEX pin #
+ 0 // power on polarity
+ })
+ Name(WAKG, Package() {
+ 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander)
+ 0, // IOEX #
+ 0, // GPIO pad #/IOEX pin #
+ 0 // wake en polarity
+ })
+ Name(SCLK, Package() {
+ 0, // 0-disable, 1-enable
+ 0, // MSKCRQSRC4
+ 0 // assert polarity, ICC should be LOW-activated
+ })
+
+ Include("Rtd3BxtPcie.asl")
+ }
+
+ ///
+ /// PCIe RTD3 - SLOT#6
+ ///
+ Scope(\_SB.PCI0.RP06)
+ {
+ Name (PCA6, 0)
+ // reset pin = none
+ // power pin = none
+ // wake pin = none
+ // CLK_REQ = Mask Enable of Mapped CLKREQ# for CLKOUT_SRC4 (MSKCRQSRC4)
+ Name(SLOT, 6) ///- port #6
+
+ Name(RSTG, Package() {
+ 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander)
+ 0, // IOEX #
+ 0, // GPIO pad #/IOEX pin #
+ 0 // reset pin de-assert polarity
+ })
+ Name(PWRG, Package() {
+ 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander)
+ 0, // IOEX #
+ 0, // GPIO pad #/IOEX pin #
+ 0 // power on polarity
+ })
+ Name(WAKG, Package() {
+ 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander)
+ 0, // IOEX #
+ 0, // GPIO pad #/IOEX pin #
+ 0 // wake en polarity
+ })
+ Name(SCLK, Package() {
+ 0, // 0-disable, 1-enable
+ 0, // MSKCRQSRC4
+ 0 // assert polarity, ICC should be LOW-activated
+ })
+
+ Include("Rtd3BxtPcie.asl")
+ }
+//
+// PCIe root ports - END
+//
+
+//
+// SATA - START
+//
+
+ Scope(\_SB.PCI0.SATA) {
+
+ OperationRegion (PMCS, PCI_Config, 0x74, 0x4)
+ Field (PMCS, WordAcc, NoLock, Preserve) {
+ PMSR, 32, // 0x74, PMCSR - Power Management Control and Status
+ }
+
+ /// _PS0 Method for SATA HBA
+ Method(_PS0,0,Serialized)
+ {
+
+ }
+
+ /// _PS3 Method for SATA HBA
+ Method(_PS3,0,Serialized)
+ {
+ }
+
+ /// Define SATA PCI Config OperationRegion
+ OperationRegion(SMIO,PCI_Config,0x24,4)
+ Field(SMIO,AnyAcc, NoLock, Preserve) {
+ Offset(0x00), ///- SATA MABR6
+ MBR6, 32, ///- SATA ABAR
+ }
+
+ Scope(PRT0) {
+ // Define _PR0, _PR3 PowerResource Package
+ // P0 command port = ABAR + 0x118
+ // power pin = N_GPIO_22
+ Name(PORT, 0)
+ Name(PBAR, 0x118) // port0 command port address
+ Name(PWRG, Package() {
+ 1, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander)
+ 0, // GPIO group #/IOEX #
+ N_GPIO_22, // GPIO pad #/IOEX pin #
+ 1 // power on polarity
+ })
+ Include("Rtd3BxtSata.asl")
+ } // end device(PRT0)
+
+ Scope(PRT1) {
+ // Define _PR0, _PR3 PowerResource Package
+ // P1 command port = ABAR + 0x198
+ // power pin = none
+ Name(PORT, 1)
+ Name(PBAR, 0x198) // port1 command port address
+ Name(PWRG, Package() {
+ 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander)
+ 0, // GPIO group #/IOEX #
+ 0, // GPIO pad #/IOEX pin #
+ 0 // power on polarity
+ })
+ Include("Rtd3BxtSata.asl")
+ } // end device(PRT1)
+
+ ///
+ /// _DSM Device Specific Method supporting AHCI DEVSLP
+ ///
+ /// Arg0: UUID Unique function identifier \n
+ /// Arg1: Integer Revision Level \n
+ /// Arg2: Integer Function Index \n
+ /// Arg3: Package Parameters \n
+ ///
+ /// Variables:
+ Name(DRV, 0) /// Storage for _DSM Arg3 parameter 0
+ Name(PWR, 0) /// Storage for _DSM Arg3 parameter 1
+
+ Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) {
+
+ /// Check UUID of _DSM defined by Microsoft
+ If (LEqual(Arg0, ToUUID ("E4DB149B-FCFE-425b-A6D8-92357D78FC7F"))) {
+ ///
+ /// Switch by function index
+ ///
+ Switch (ToInteger(Arg2)) {
+ Case (0) { /// case 0:
+ ///- Standard query - A bitmask of functions supported
+ ///- Supports function 0-3
+ Return(0x0f)
+ }
+ Case (1) { /// case 1:
+ ///- Query Device IDs (Addresses) of children where drive power and/or DevSleep are supported.
+ ///- SATA HBA provides autonomous link (DevSleep) support, return a package of 0 elements
+ Return( Package(){}) ///- SATA HBA provides native DevSleep
+ }
+ Case (2) { /// Case 2: Control power to device.
+ Store(ToInteger(DerefOf(Index(Arg3, Zero))), DRV)
+ Store(ToInteger(DerefOf(Index(Arg3, One))), PWR)
+
+ Switch(ToInteger(DRV)){
+ Case (0x0000FFFF){
+ If (LAnd(LAnd(And(RCG0, 0x01), 0x01), LGreaterEqual(\OSYS, 2012))) {
+ ///- Turn on drive and link power to all drives. Note that even though
+ If(PWR){ // Applying Power
+ \_SB.PCI0.SATA.PRT0.ODPR._ON() ///- apply power to port 0
+ }
+ } Else {
+ If(PWR){ // Applying Power
+ \_SB.PCI0.SATA.PRT0.SPPR._ON() ///- apply power to port 0
+ }
+ }
+ }
+ } //Switch(DRV)
+ Return (0)
+ } //Case (2)
+ Case (3){ /// Case 3: Current status of Device/Link of Port
+ Store(ToInteger(DerefOf(Index(Arg3, Zero))), DRV)
+ Switch(ToInteger(DRV)){ /// Check for SATA port
+ Case (0x0000FFFF) { ///- SATA Port 0
+ ///- Bit0 => Device power state
+ If (LAnd(LAnd(And(RCG0, 0x01), 0x01), LGreaterEqual(\OSYS, 2012))) {
+ If(LEqual(\_SB.PCI0.SATA.PRT0.ODPR._STA(), 0)){
+ Store(0, Local0)
+ }Else{
+ Store(1, Local0)
+ }
+ } Else {
+ ///- Bit0 => Device power state
+ If (LEqual(\_SB.PCI0.SATA.PRT0.SPPR._STA(), 0)){
+ Store(0, Local0)
+ } Else {
+ Store(1, Local0)
+ }
+ }
+ Return (Local0)
+ }
+ Case (0x0001FFFF){ ///- SATA Port 1
+ ///- Bit0 => Device power state
+ If (LEqual(\_SB.PCI0.SATA.PRT1.SPPR._STA(), 0)) {
+ Store(0, Local0)
+ } Else {
+ Store(1, Local0)
+ }
+ Return (Local0)
+ }
+ Default { ///- Invalid SATA Port - error
+ Return (Ones)
+ }
+ }
+ }
+ Default {
+ Return (0)
+ }
+ }
+ } Else { // UUID does not match
+ Return (0)
+ }
+ } /// @defgroup sata_dsm SATA _DSM Method
+
+ } //Scope(\_SB.PCI0.SATA)
+//
+// SATA - END
+//
+
+ Scope(\_SB.PCI0.XHC.RHUB) { //USB XHCI RHUB
+ //
+ // No specific power control (GPIO) to USB connectors (p2/p4/p5),
+ // declare power resource with null functions and specify its wake ability
+ // Please refer to ACPI 5.0 spec CH7.2
+ //
+ Scope (HS02) {
+ Name(PORT, 2)
+ Include ("Rtd3BxtUsb.asl")
+ }
+ Scope (SSP2) {
+ Name(PORT, 10)
+ Include ("Rtd3BxtUsb.asl")
+ }
+
+ Scope (HS04) {
+ Name(PORT, 4)
+ Include ("Rtd3BxtUsb.asl")
+ }
+ Scope (SSP4) {
+ Name(PORT, 12)
+ Include ("Rtd3BxtUsb.asl")
+ }
+
+ Scope (HS05) {
+ Name(PORT, 5)
+ Include ("Rtd3BxtUsb.asl")
+ }
+ Scope (SSP5) {
+ Name(PORT, 13)
+ Include ("Rtd3BxtUsb.asl")
+ }
+
+ ///
+ /// WWAN RTD3 support, associate _PR0, PR2, PR3 for USB High speed Port 3
+ Scope (HS03) {
+ Name(PORT, 3)
+ Include ("Rtd3BxtUsbWwan.asl")
+ }
+
+ } // RHUB
+
+ Scope(\_SB){
+ PowerResource(SDPR, 0, 0) {
+ Name(_STA, One)
+ Method(_ON, 0, Serialized) {
+
+ }
+
+ Method(_OFF, 0, Serialized) {
+
+ }
+
+ } //End of PowerResource(SDPR, 0, 0)
+ } //End of Scope(\_SB)
+
+ Scope(\_SB.PCI0.SDHA)
+ {
+
+ Name(_PR0, Package(){SDPR}) // TBD
+ Name(_PR3, Package(){SDPR}) // TBD
+ } //Scope(\_SB.PCI0.SDHA)
+
+ Scope(\_SB.PCI0.SDIO)
+ {
+
+ Name(_PR0, Package(){SDPR}) // TBD
+ Name(_PR3, Package(){SDPR}) // TBD
+ } //Scope(\_SB.PCI0.SDIO)
+
+ Scope(\_SB)
+ {
+ //
+ // Dummy power resource for USB D3 cold support
+ //
+ PowerResource(USBC, 0, 0)
+ {
+ Method(_STA) { Return (0x1) }
+ Method(_ON) {}
+ Method(_OFF) {}
+ }
+ }
+
+ Scope(\_SB.PCI0.XDCI)
+ {
+ Method (_RMV, 0, NotSerialized) // _RMV: Removal Status
+ {
+ Return (Zero)
+ }
+
+ Method (_PR3, 0, NotSerialized) // _PR3: Power Resources for D3hot
+ {
+ Return (Package (0x01)
+ {
+ USBC // return dummy package
+ })
+ }
+
+ OperationRegion (PMCS, PCI_Config, 0x74, 0x4)
+ Field (PMCS, WordAcc, NoLock, Preserve) {
+ PMSR, 32, // 0x74, PMCSR - Power Management Control and Status
+ }
+
+ Method (_PS0, 0, NotSerialized) { // _PS0: Power State 0
+ }
+
+ Method (_PS3, 0, NotSerialized) { // _PS3: Power State 3
+ //
+ // dummy read PMCSR
+ //
+
+ Store (PMSR, Local0)
+ And (Local0, 1, Local0) // Dummy operation on Local0
+ }
+ } // Scope(\_SB.PCI0.XDCI)
+
+//
+// XDCI - end
+//
+
+//Power Resource for Audio Codec
+ Scope(\_SB.PCI0)
+ {
+ PowerResource(PAUD, 0, 0) {
+
+ /// Namespace variable used:
+ Name(PSTA, One) /// PSTA: Physical Power Status of Codec 0 - OFF; 1-ON
+ Name(ONTM, Zero) /// ONTM: 0 - Not in Speculative ON ; Non-Zero - elapsed time in Nanosecs after Physical ON
+
+ Name(_STA, One) /// _STA: PowerResource Logical Status 0 - OFF; 1-ON
+
+ ///@defgroup pr_paud Power Resource for onboard Audio CODEC
+
+ Method(_ON, 0){ /// _ON method \n
+
+ Store(One, _STA) ///- Set Logocal power state
+ PUAM() ///- Call PUAM() to tansition Physical state to match current logical state
+ ///@addtogroup pr_paud
+ } // End _ON
+
+ Method(_OFF, 0){ /// _OFF method \n
+
+ Store(Zero, _STA) ///- Set the current power state
+ PUAM() ///- Call PUAM() to tansition Physical state to match current logical state
+ ///@addtogroup pr_paud
+ } // End _OFF
+
+ /// PUAM - Power Resource User Absent Mode for onboard Audio CODEC
+ /// Arguments:
+ ///
+ /// Uses:
+ /// _STA - Variable updated by Power Resource _ON/_OFF methods \n
+ /// \\UAMS - Variable updated by GUAM method to show User absent present \n
+ /// ONTM - Local variable to store ON time during Speculative ON \n
+ /// ______________________________
+ // | Inputs | Outputs |
+ // ______________________________
+ // | _STA | \UAMS | GPIO | ONTM |
+ // ______________________________
+ // | 1 | 0 | ON | !0 |
+ // | 1 | !0 | ON | !0 |
+ // | 0 | 0 | ON | !0 |
+ // | 0 | !0 | OFF | 0 |
+ // ______________________________
+ /**
+ <table>
+ <tr> <th colspan="2"> Inputs <th colspan="2"> Output
+ <tr> <th>_STA <th> \\UAMS <th> GPIO <th>ONTM
+ <tr> <td>1 <td>0 <td>ON <td>!0
+ <tr> <td>1 <td>!0<td>ON <td>!0
+ <tr> <td>0 <td>0 <td>ON <td>!0
+ <tr> <td>0 <td>!0<td>OFF<td> 0
+ </table>
+ **/
+ ///@addtogroup pr_paud_puam
+ Method(PUAM, 0, Serialized)
+ {
+ If (LEqual(^_STA, Zero)) {
+ } Else { /// New state = ON (_STA=1) or (_STA=0 and \UAMS=0)
+ }
+ } //PUAM
+ } //PAUD
+ } //Scope(\_SB.PCI0)
+//Power Resource for Audio Codec End
+
+// I2C1 - TouchPanel Power control
+
+//Serial IO End
+
+ // Modern Standby N:1 Power Resource definition. Place Holder.
+ If (LEqual(\EMOD, 1)) {
+ Scope(\_SB){
+ Name(GBPS, 0) // Power state flag for Modern Standby. Initial value = 1 (On).
+ PowerResource(MODS, 0, 0){ /// Modern Standby Power Resource
+
+ Method(_STA) { /// _STA method
+ If (LGreaterEqual(OSYS, 2015)) {
+ Return(GBPS)
+ }
+ Return(0)
+ }
+
+ Method(_ON, 0) { /// _ON Method
+ If (LGreaterEqual(OSYS, 2015)) {
+ \_SB.PCI0.SATA.PRT0.SPON()
+ Store(1, GBPS) // Indicate devices are ON
+ }
+ }
+
+ Method(_OFF, 0) { /// _OFF Method
+ If (LGreaterEqual(OSYS, 2015)) {
+ \_SB.PCI0.SATA.PRT0.SPOF()
+ Store(0, GBPS)
+ }
+ }
+ } // End MODS
+ } // \_SB
+ } // End If ((LEqual(EMOD, 1))
+
+ Scope(\_SB.PCI0) {
+ Method(LPD3, 0, Serialized) {
+ //
+ // Memory Region to access to the PCI Configuration Space
+ // and dummy read PMCSR
+ //
+ OperationRegion (PMCS, PCI_Config, 0x84, 0x4)
+ Field (PMCS, WordAcc, NoLock, Preserve) {
+ PMSR, 32, // 0x84, PMCSR - Power Management Control and Status
+ }
+ //
+ // Dummy PMCSR read
+ //
+ Store (PMSR, Local0)
+ And (Local0, 1, Local0) // Dummy operation on Local0
+ }
+
+ PowerResource (LSPR, 0, 0) {
+ //
+ // LPSS Power Resource
+ //
+ Name (_STA, One)
+ Method (_ON, 0, Serialized) {
+
+ }
+
+ Method (_OFF, 0, Serialized) {
+
+ }
+ } //End of PowerResource(SDPR, 0, 0)
+ }
+
+ Scope(\_SB.PCI0.PWM)
+ {
+ //
+ // Dummy Power Resource declaration
+ //
+ Name(_PR0, Package(){LSPR}) // TBD
+ Name(_PR3, Package(){LSPR}) // TBD
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ } //Scope(\_SB.PCI0.PWM)
+
+ Scope(\_SB.PCI0.I2C0)
+ {
+ Name(_PR0, Package(){LSPR}) // TBD
+ Name(_PR3, Package(){LSPR}) // TBD
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ } //Scope(\_SB.PCI0.I2C0)
+
+ Scope(\_SB.PCI0.I2C1)
+ {
+ //
+ // Dummy Power Resource declaration
+ //
+ Name(_PR0, Package(){LSPR}) // TBD
+ Name(_PR3, Package(){LSPR}) // TBD
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ } //Scope(\_SB.PCI0.I2C1)
+
+ Scope(\_SB.PCI0.I2C2)
+ {
+ Name(_PR0, Package(){LSPR}) // TBD
+ Name(_PR3, Package(){LSPR}) // TBD
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ } //Scope(\_SB.PCI0.I2C2)
+
+ Scope(\_SB.PCI0.I2C3)
+ {
+ //
+ // Dummy Power Resource declaration
+ //
+ Name(_PR0, Package(){LSPR}) // TBD
+ Name(_PR3, Package(){LSPR}) // TBD
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ } //Scope(\_SB.PCI0.I2C3)
+
+ Scope(\_SB.PCI0.I2C4)
+ {
+ Name(_PR0, Package(){LSPR}) // TBD
+ Name(_PR3, Package(){LSPR}) // TBD
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ } //Scope(\_SB.PCI0.I2C4)
+
+ Scope(\_SB.PCI0.I2C5)
+ {
+ //
+ // Dummy Power Resource declaration
+ //
+ Name(_PR0, Package(){LSPR}) // TBD
+ Name(_PR3, Package(){LSPR}) // TBD
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ } //Scope(\_SB.PCI0.I2C5)
+
+ Scope(\_SB.PCI0.I2C6)
+ {
+ Name(_PR0, Package(){LSPR}) // TBD
+ Name(_PR3, Package(){LSPR}) // TBD
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ } //Scope(\_SB.PCI0.I2C6)
+
+ Scope(\_SB.PCI0.I2C7)
+ {
+ //
+ // Dummy Power Resource declaration
+ //
+ Name(_PR0, Package(){LSPR}) // TBD
+ Name(_PR3, Package(){LSPR}) // TBD
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ } //Scope(\_SB.PCI0.I2C7)
+
+ Scope(\_SB.PCI0.SPI1)
+ {
+ Name(_PR0, Package(){LSPR}) // TBD
+ Name(_PR3, Package(){LSPR}) // TBD
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ } //Scope(\_SB.PCI0.SPI1)
+
+ Scope(\_SB.PCI0.SPI2)
+ {
+ //
+ // Dummy Power Resource declaration
+ //
+ Name(_PR0, Package(){LSPR}) // TBD
+ Name(_PR3, Package(){LSPR}) // TBD
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ } //Scope(\_SB.PCI0.SPI2)
+
+ Scope(\_SB.PCI0.SPI3)
+ {
+ Name(_PR0, Package(){LSPR}) // TBD
+ Name(_PR3, Package(){LSPR}) // TBD
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ } //Scope(\_SB.PCI0.SPI3)
+
+ Scope(\_SB.PCI0.URT1)
+ {
+ Name(_PR0, Package(){LSPR}) // TBD
+ Name(_PR3, Package(){LSPR}) // TBD
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ } //Scope(\_SB.PCI0.URT1)
+
+ Scope(\_SB.PCI0.URT2)
+ {
+ Name(_PR0, Package(){LSPR}) // TBD
+ Name(_PR3, Package(){LSPR}) // TBD
+ Method (_PS0) { }
+ Method (_PS3) { LPD3 () }
+ } //Scope(\_SB.PCI0.URT2)
+
+ Scope(\_SB.PCI0.URT3)
+ {
+ Name(_PR0, Package(){LSPR}) // TBD
+ Name(_PR3, Package(){LSPR}) // TBD
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ } //Scope(\_SB.PCI0.URT3)
+
+ Scope(\_SB.PCI0.URT4)
+ {
+ Name(_PR0, Package(){LSPR}) // TBD
+ Name(_PR3, Package(){LSPR}) // TBD
+ Method (_PS0) { }
+ Method (_PS3) {LPD3 ()}
+ } //Scope(\_SB.PCI0.URT4)
+
+} // End SSDT
+
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